JP2007110006A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method free from a problem of plasma damage on a silicon substrate, and capable of preventing difference from occurring between coarse and dense patterns due to a mask aperture diameter, improving groove shape machining accuracy, and preventing degradation in breakdown voltage of a gate oxide film in the vicinity of an edge of a shallow groove. <P>SOLUTION: The manufacturing method includes steps of forming a laminated film consisting of underlying films 11 and 12, and an oxidization prevention film 13 on the silicon substrate 10; selectively dry-etching the laminated film to form an aperture to have the surface of the silicon substrate 10 exposed; etching the exposed region of the silicon substrate to form an isolation groove 18; and burying an insulation film 16a in the separation groove to form an element isolation layer. In the step of forming the isolation groove, an inverted trapezoidal groove is formed on the exposed region of the silicon substrate by wet etching, and the groove is deepened by dry etching. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as an LSI and a manufacturing method thereof.

  In recent years, STI (Shallow Trench Isolation) technology has attracted attention as an element isolation process of CMOS-LSI. Hereinafter, a conventional STI formation method will be described with reference to FIGS.

First, as shown in FIG. 13A, an SiO ₂ film 41 as a base film, a polysilicon film 42, a silicon nitride film 43 as an antioxidant film, an antireflection film on a silicon substrate 40 on the (100) main surface. (ARC) 44 and a resist pattern 45 subjected to exposure opening processing are formed.

Next, as shown in FIG. 13B, the antireflection film 44, the silicon nitride film 43, the polysilicon film 42, and the SiO ₂ film 41 are removed by dry etching and oxygen ashing. As a result, the silicon substrate 40 is exposed to the opening.

  Next, as shown in FIG. 14A, anisotropic etching is performed on the silicon substrate 40 by dry etching using a CF-based gas.

  Next, as shown in FIG. 14B, the resist 45 and the antireflection film 44 are removed by a hydrogen peroxide cleaning process, and after the wet etching process of one bath, as a protective oxidation of the separation groove, as an oxygen radical oxidation method An oxidation treatment is performed at 1000 to 1150 ° C. using ISSG (In-Situ Stream Generation) annealing, and the separation groove is rounded and oxidized. The sulfurized water is a mixed solution of sulfuric acid and hydrogen peroxide water.

  Next, as shown in FIG. 14C, an HDP-NSG film 46 is deposited at about 550 to 700 nm.

  Next, as shown in FIG. 15A, an RO resist 47 is deposited.

  Next, as shown in FIG. 15B, after the RO dry etching process is performed by the oxide film dry etching process, the protruded RO resist 47 and the HDP-NSG film 46 are washed with sulfuric acid and chemical mechanical polishing. Flatten.

Next, as shown in FIG. 15C, the silicon nitride film 43 is removed by dry etching, and the polysilicon film 42 and the SiO ₂ film 41 are removed by wet etching. As described above, the STI by the conventional forming method is formed.
Japanese Patent Laid-Open No. 7-161808 (page 3, Fig. 1-2)

  However, in the conventional technique, when forming a groove having a difference in the size of the mask opening diameter, a dry etching process using a CF-based gas as shown in FIG. Thus, grooves having different facets on the side surfaces are formed. Thereby, the shape from which the curvature radius of a shallow groove part differs is formed. That is, there arises a problem that the groove shape processing accuracy is reduced due to the difference between the density patterns depending on the mask opening diameter. In particular, in the case of a shape having a large facet angle, such as the groove on the left side of FIG. 15C, there is a concern that the gate oxide film withstand voltage deteriorates due to the thin gate oxide film formed near the edge of the shallow groove portion. . Also in Patent Document 1, there is a concern that the groove shape processing accuracy is reduced due to the difference between the density patterns.

  An object of the present invention is to make it possible to form an STI while overcoming the above-mentioned problems.

A method for manufacturing a semiconductor device according to the present invention includes:
(100) forming a laminated film of a base film and an antioxidant film on a silicon substrate;
Selectively etching the laminated film to form an opening to expose the surface of the silicon substrate;
Etching the exposed portion of the silicon substrate to form a separation groove;
A step of embedding an insulating film in the isolation trench to form an element isolation layer,
The step of forming the separation groove includes:
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by wet etching;
And a step of performing a groove deepening process by dry etching.

  In the conventional case, when the separation groove is formed, dry etching using a CF-based gas is performed, so that plasma damage to the silicon substrate is irregular, and the separation groove having a large mask opening diameter and the mask opening diameter are According to the present invention, an inverted trapezoidal groove is formed by wet etching in the first stage and a groove deepening process is performed by dry etching in the second stage. There is no problem of plasma damage to the silicon substrate, and the occurrence of a density pattern difference due to the mask opening diameter can be suppressed. That is, the groove shape processing accuracy can be improved. As a result, it is possible to suppress the breakdown voltage deterioration of the gate oxide film near the edge of the shallow groove portion.

In the above manufacturing method, for the step of forming the separation groove,
Forming a shallow groove having a width wider than the opening in the silicon substrate located under the opening by isotropic wet etching using an acid solution to the base film in the vicinity of the opening of the silicon substrate;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution to the shallow groove portion;
There is a preferable aspect that includes a step of performing a trench deepening process by dry etching of the opening to the exposed portion of the silicon substrate.

  Here, the acid solution is preferably BHF (buffered hydrofluoric acid) or the like. Moreover, ammonium hydroxide etc. are preferable as an alkaline solution. According to this aspect, by using anisotropic etching with an alkaline solution when forming the shallow groove portion, the etching proceeds along the plane orientation (111) surface of the silicon substrate, so that it is easy to ensure the groove shape processing accuracy. It will be a thing.

In the above manufacturing method, for the step of forming the separation groove,
Forming a shallow groove having a width wider than the opening in the silicon substrate located under the opening by isotropic wet etching using an acid solution to the base film in the vicinity of the opening of the silicon substrate;
Implanting boron ions into the silicon substrate in the opening;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution to the shallow groove portion;
There is a preferable aspect that includes a step of performing a trench deepening process by dry etching of the opening to the exposed portion of the silicon substrate.

  This aspect is characterized in the order of boron ion implantation, alkaline solution anisotropic wet etching, and dry etching groove deepening treatment. According to this aspect, before performing anisotropic wet etching using an alkaline solution, boron ions are implanted to give time control to the wet etching, and further improve the groove shape processing accuracy. Differential shape variation can be suppressed. As a result, the problem of electric field concentration and stress concentration can be solved, and the gate oxide film breakdown voltage can be further improved.

In the above manufacturing method, for the step of forming the separation groove,
Implanting boron ions into the silicon substrate in the opening;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution;
Depositing an insulating film such that both ends of the (111) plane of the inverted trapezoidal groove are partially masked;
A step of performing a groove deepening process by dry etching the silicon substrate exposed portion of the opening;
There is a preferable aspect of comprising a step of removing the deposited insulating film. Here, as the insulating film, a TEOS (tetraethoxysilane) film or the like is preferable.

  This aspect is characterized in that there is no isotropic wet etching using an acid solution to the base film before boron ion implantation, and a partial mask with an insulating film on both ends of the (111) plane. According to this aspect, as described above, the groove shape processing accuracy can be improved by controlling the time of wet etching by boron ion implantation, and the grooves for deepening the groove can be formed by the partial masks on both ends of the (111) plane. It can be made narrower.

In the above manufacturing method, for the step of forming the separation groove,
Implanting boron ions into the silicon substrate in the opening;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution;
Depositing an insulating film so that the entire (111) surface of the inverted trapezoidal groove is masked;
A step of performing a groove deepening process by dry etching the silicon substrate exposed portion of the opening;
Removing the deposited insulating film;
There is a preferable aspect that includes a step of forming an inverted trapezoidal shape at the bottom of the separation groove by anisotropic wet etching using an alkaline solution.

  In this embodiment, there is no isotropic wet etching using an acid solution to the base film before boron ion implantation, and the whole surface mask of the insulating film with respect to the (111) plane and anisotropic wet etching using an alkaline solution. This is characterized by the two processes. According to this aspect, as described above, the groove shape processing accuracy can be improved by controlling the time of wet etching by boron ion implantation, and at the same time, a different mask surface mask and two different alkaline solutions are used. By the anisotropic wet etching, the groove for the groove deepening treatment can be further narrowed.

  Further, in the above manufacturing method, the wet etching is performed by performing an anisotropic etching process of (111) on the exposed portion using an alkaline solution, and performing the process before all the etched exposed surfaces become the (111) plane. There is a mode in which the dry etching of the groove deepening process is performed while maintaining the (111) plane.

  According to this aspect, the groove shape processing accuracy is improved by performing time control in the anisotropic etching with the alkaline solution for forming the shallow groove portion.

  Further, the above manufacturing method may further include a step of performing rounding oxidation of the separation groove using an oxygen radical oxidation method after the step of forming the separation groove. Here, as the oxygen radical oxidation method, an oxidation treatment using ISSG (In-Situ Stream Generation) annealing is preferable.

  According to this aspect, the breakdown voltage of the gate oxide film is improved by performing the rounding oxidation using the oxygen radical oxidation method when forming the shallow groove portion.

  Further, in the above manufacturing method, after the step of forming the separation groove, a step of filling the separation groove, a step of flattening the surface, and a step of performing etch back after flattening the surface There is a mode of having. This functions as an STI by embedding an insulating film in the isolation trench.

  A semiconductor device according to the present invention includes a (100) silicon substrate, a separation groove, and an insulator embedded in the separation groove. The separation groove has a (100) surface on a bottom surface and an end portion on the bottom surface. The (111) plane and the side surface have the (011) plane, and the upper end of the side surface has the (111) plane.

  According to this, it is possible to prevent the oxide film at the groove edge portion from being thinned by providing facets in the shallow groove portion, so that the breakdown voltage of the gate oxide film can be improved.

  In the above semiconductor device, the (111) plane at the upper end of the side surface of the separation groove may be wider than the (111) plane at the bottom end. According to this, by providing a facet in the shallow groove portion, it is possible to prevent the oxide film at the groove edge portion from being thinned, and the breakdown voltage of the gate oxide film is improved.

  In the above semiconductor device, the length of the side surface of the separation groove may be 300 to 400 nm. According to this, it becomes possible to apply as STI by setting the groove to 300 to 400 nm.

  In the semiconductor device, the width of the upper end of the separation groove may be larger than the width of the bottom surface of the separation groove. In this case, the breakdown voltage of the gate oxide film is improved by making the shallow groove portion larger than the groove bottom portion.

  According to the present invention, the inverted trapezoidal groove is formed by wet etching in the first stage, and the groove deepening process is performed by dry etching in the second stage, so that there is no problem of plasma damage to the silicon substrate and the mask opening diameter is reduced. It is possible to suppress the generation of a density pattern difference due to, and improve the groove shape processing accuracy. As a result, it is possible to suppress the breakdown voltage degradation of the gate oxide film near the edge of the shallow groove portion.

  Embodiments of a semiconductor device manufacturing method according to the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
Embodiment 1 of the present invention will be described below with reference to the drawings.

1 to 4 show a method of manufacturing a semiconductor device according to the first embodiment of the present invention. In FIGS. 1 to 4, 10 is a (100) silicon substrate, 11 is a SiO ₂ film as a base film, 12 is a polysilicon film as a base film, 13 is a silicon nitride film as an antioxidant film, 14 is an antireflection film (ARC), 15 is a resist, 16 is an HDP-NSG film, and 17 is an RO resist.

First, as shown in FIG. 1A, a SiO ₂ film 11, a polysilicon film 12, a silicon nitride film 13, an antireflection film 14 and a resist 15 subjected to exposure opening treatment are formed on a silicon substrate 10 on a (100) main surface. Pattern is formed. FIG. 1A shows the state after the active region mask exposure step, and the groove shape formed by the etching process to be performed later varies depending on the diameter of the resist opening. Depending on the device to be applied, it is necessary to adjust the shape of the opening.

Next, as shown in FIG. 1B, the antireflection film 14, the silicon nitride film 13, the polysilicon film 12, and the SiO ₂ film 11 are removed by dry etching and oxygen ashing, and the silicon substrate 10 is opened. Exposed to.

Next, as shown in FIG. 1C, the SiO ₂ film 11 is etched using BHF (buffered hydrofluoric acid) as wet etching using an acid solution. At that time, an isotropic etching process is performed so that the etching region is approximately 10 to 20 nm wider at one end than the opening region.

Next, as shown in FIG. 2A, boron ions are implanted into the silicon exposed portion of the opening (corresponding to a boron concentration of 1 × 10 ²⁰ cm ⁻³ ).

  Next, as shown in FIG. 2B, the silicon substrate 10 is etched using sulfuric acid and ammonium hydroxide as wet etching using an alkaline solution. At that time, the anisotropic etching process is performed such that the process is stopped before all the exposed portions of the silicon substrate 10 become the (111) plane.

  Next, as shown in FIG. 2C, a trench deepening process of about 250 to 400 nm is performed along the (100) plane at the exposed portion of the silicon substrate 10 using a dry etching process.

  Next, as shown in FIG. 3 (a), after removing the resist 15 and the antireflection film 14 by a hydrogen peroxide cleaning process, after the wet etching process of one bath, an oxygen radical oxidation method is performed as protective oxidation of the separation groove. As an example, an oxidation treatment is performed at 1000 to 1150 ° C. using ISSG (In-Situ Stream Generation) annealing, and the separation groove is rounded and oxidized.

  Next, as shown in FIG. 3B, an HDP-NSG film 16 is deposited at about 550 to 700 nm.

  Next, as shown in FIG. 3C, an RO resist 17 is deposited.

  Next, as shown in FIG. 4A, an RO dry etching process is performed by an oxide film dry etching process.

  Next, as shown in FIG. 4B, the protruding RO resist 17 and HDP-NSG film 16 are planarized by cleaning with sulfuric acid and chemical mechanical polishing.

Next, as shown in FIG. 4C, the silicon nitride film 13 is removed by dry etching, and the polysilicon film 12 and the SiO ₂ film 11 are removed by wet etching. An STI in which an insulator 16a is embedded in a separation groove 18 in the silicon substrate 10 is formed.

(Embodiment 2)
Embodiment 2 of the present invention will be described below with reference to the drawings.

5 to 8 show a method of manufacturing a semiconductor device according to the second embodiment of the present invention. In FIGS. 5 to 8, 20 is a (100) silicon substrate, 21 is a SiO ₂ film, and 22 is polysilicon. A film, 23 is a silicon nitride film, 24 is an antireflection film, 25 is a resist, 26 is a TEOS film, 27 is an HDP-NSG film, and 28 is an RO resist.

First, as shown in FIG. 5A, an SiO ₂ film 21, a polysilicon film 22, a silicon nitride film 23, an antireflection film 24, and a resist 25 subjected to exposure opening treatment are formed on a silicon substrate 20 on the (100) main surface. Pattern is formed. FIG. 5A shows the state after the active region mask exposure step, and the groove shape formed by the subsequent etching process varies depending on the diameter of the resist opening. Depending on the device to be applied, it is necessary to adjust the shape of the opening.

Next, as shown in FIG. 5B, the antireflection film 24, the silicon nitride film 23, the polysilicon film 22 and the SiO ₂ film 21 are removed by dry etching and oxygen ashing, so that the silicon substrate 20 is opened. Exposed to.

Next, as shown in FIG. 5C, boron ions are implanted into the silicon exposed portion of the opening (corresponding to a boron concentration of 1 × 10 ²⁰ cm ⁻³ ).

  Next, as shown in FIG. 6A, the silicon substrate 20 is etched using sulfuric acid and ammonium hydroxide as wet etching using an alkaline solution. At that time, the anisotropic etching process is performed such that the process is stopped before all the exposed portions of the silicon substrate 20 become the (111) plane.

  Next, as shown in FIG. 6 (b), the resist 25 and the antireflection film 24 are removed by a hydrogen peroxide cleaning process.

  Next, as shown in FIG. 6C, a TEOS (tetraethoxysilane) film 26 is deposited so that both ends of the (111) plane at the bottom of the inverted trapezoidal groove are partially masked.

  Next, as shown in FIG. 7A, a groove deepening process of about 250 to 400 nm is performed along the (100) plane at the exposed portion of the silicon substrate 20 using a dry etching process.

  In FIG. 6C, the TEOS film 26 partially masks both ends of the (111) surface of the inverted trapezoidal groove bottom in order to leave the (111) surface at the groove bottom in FIG. It is. This is different from the masking of the entire surface in the case of Embodiment 3 (see FIGS. 10C and 11A).

  Next, as shown in FIG. 7B, the TEOS film 26 deposited in FIG. 6C is removed by cleaning, and after one-bus wet etching treatment, oxygen radical oxidation is performed as protective oxidation of the separation groove. As a method, using ISSG (In-Situ Stream Generation) annealing, oxidation treatment is performed at 1000 to 1150 ° C., and the separation groove is rounded and oxidized.

  Next, as shown in FIG. 7C, about 550 to 700 nm of HDP-NSG film 27 and RO resist 28 are deposited.

  Next, as shown in FIG. 8A, an RO dry etching process is performed by an oxide film dry etching process.

  Next, as shown in FIG. 8B, the protruding RO resist 28 and HDP-NSG film 27 are planarized by cleaning with sulfuric acid and chemical mechanical polishing.

Next, as shown in FIG. 8C, the silicon nitride film 23 is removed by dry etching, and the polysilicon film 22 and the SiO ₂ film 21 are removed by wet etching. An STI in which an insulator 27a is embedded in a separation groove 29 in the silicon substrate 20 is formed.

(Embodiment 3)
Embodiment 3 of the present invention will be described below with reference to the drawings.

9 to 12 show a method of manufacturing a semiconductor device according to the third embodiment of the present invention. In FIGS. 9 to 12, 30 is a (100) silicon substrate, 31 is a SiO ₂ film, and 32 is polysilicon. A film, 33 is a silicon nitride film, 34 is an antireflection film, 35 is a resist, 36 is a TEOS film, 37 is an HDP-NSG film, and 38 is an RO resist.

First, as shown in FIG. 9A, an SiO ₂ film 31, a polysilicon film 32, a silicon nitride film 33, an antireflection film 34, and a resist 35 subjected to exposure opening treatment are formed on a (100) main surface silicon substrate 30. Pattern is formed. FIG. 9A shows the state after the active region mask exposure step, and the groove shape formed by the subsequent etching process differs depending on the diameter of the resist opening. Depending on the device to be applied, it is necessary to adjust the shape of the opening.

Next, as shown in FIG. 9B, the antireflection film 34, the silicon nitride film 33, the polysilicon film 32, and the SiO ₂ film 31 are removed by dry etching and oxygen ashing, and the silicon substrate 30 is opened. Exposed to.

Next, as shown in FIG. 9C, boron ions are implanted into the silicon exposed portion of the opening (corresponding to a boron concentration of 1 × 10 ²⁰ cm ⁻³ ).

  Next, as shown in FIG. 10A, the silicon substrate 30 is etched using sulfuric acid and ammonium hydroxide as wet etching using an alkaline solution. At that time, the anisotropic etching process is performed such that the process is stopped before all the exposed portions of the silicon substrate 30 become the (111) plane.

  Next, as shown in FIG. 10B, the resist 35 and the antireflection film 34 are removed by a sulfuric acid water washing treatment.

  Next, as shown in FIG. 10C, the TEOS film 36 is deposited so that the entire (111) plane of the bottom of the inverted trapezoidal groove is masked.

  Next, as shown in FIG. 11A, a trench deepening process of about 250 to 400 nm is performed along the (100) plane at the exposed portion of the silicon substrate 30 using a dry etching process.

  In FIG. 10C, the TEOS film 36 masks the entire (111) surface at the bottom of the inverted trapezoidal groove so that the (111) surface is not left at the groove bottom in FIG. 11A. It is. This is different from the partial masking in the second embodiment (see FIGS. 6C and 7A).

  Next, as shown in FIG. 11B, the silicon substrate 30 is etched using sulfuric acid and ammonium hydroxide as wet etching using an alkaline solution. At that time, the anisotropic etching process is performed such that the process is stopped before all the exposed portions of the silicon substrate 30 become the (111) plane.

  Next, as shown in FIG. 11C, the TEOS film 36 deposited in FIG. 10C is removed by cleaning, and after one-bus wet etching treatment, oxygen radical oxidation is performed as protective oxidation of the separation groove. As a method, an oxidation treatment is performed at 1000 to 1150 ° C. using ISSG (In-Situ Stream Generation) annealing, and the separation groove is rounded and oxidized.

  Next, as shown in FIG. 12A, an HDP-NSG film 37 is deposited at about 550 to 700 nm and an RO resist 38 is deposited.

  Next, as shown in FIG. 12B, an RO dry etching process is performed by an oxide film dry etching process.

  Next, as shown in FIG. 12C, the protruding RO resist 38 and HDP-NSG film 37 are planarized by cleaning with sulfuric acid water and chemical mechanical polishing.

Next, as shown in FIG. 12D, the silicon nitride film 33 is removed by dry etching, and the polysilicon film 32 and the SiO ₂ film 31 are removed by wet etching. An STI in which an insulator 37a is embedded in a separation groove 39 in the silicon substrate 30 is formed.

(Embodiment 4)
The semiconductor device according to the fourth embodiment of the present invention has a (100) silicon substrate and a buried insulator. The groove bottom has a (100) plane and a (111) plane. The shallow groove portion above the side surface made of the (110) surface has a (111) surface extending in a flare shape from the groove bottom surface. The length of the (110) side surface, that is, the groove depth is set to 300 to 400 nm. The shallow groove portion has a diameter larger than that of the deep groove portion. Both the shallow groove portion and the deep groove portion have facets of approximately 52 ° with respect to the (110) plane along the (111) plane.

  The present invention is a technique for suppressing the deterioration of the breakdown voltage of a gate oxide film near the edge of a shallow groove portion in a semiconductor device such as an LSI, in which there is no difference in density pattern due to the mask opening diameter, the groove shape processing accuracy is high. Useful.

Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention (the 1) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention (the 2) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention (the 3) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 1 of this invention (the 4) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention (the 1) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention (the 2) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention (the 3) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 2 of this invention (the 4) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention (the 1) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention (the 2) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention (the 3) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in Embodiment 3 of this invention (the 4) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in a prior art (the 1) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in a prior art (the 2) Sectional drawing which shows each process of the manufacturing method of the semiconductor device in a prior art (the 3)

Explanation of symbols

10 (100) Silicon substrate 11 SiO ₂ film 12 Polysilicon film 13 Silicon nitride film 14 Antireflection film (ARC)
15 resist (pattern)
16 HDP-NSG film 16a Insulator 17 RO resist 18 Separation groove 20 (100) Silicon substrate 21 SiO ₂ film 22 Polysilicon film 23 Silicon nitride film 24 Antireflection film (ARC)
25 resist (pattern)
26 TEOS film 27 HDP-NSG film 27a Insulator 28 RO resist 29 Separation groove 30 (100) Silicon substrate 31 SiO ₂ film 32 Polysilicon film 33 Silicon nitride film 34 Antireflection film (ARC)
35 resist (pattern)
36 TEOS film 37 HDP-NSG film 37a Insulator 38 RO resist 39 Separation groove

Claims (12)

(100) forming a laminated film of a base film and an antioxidant film on a silicon substrate;
Selectively etching the laminated film to form an opening to expose the surface of the silicon substrate;
Etching the exposed portion of the silicon substrate to form a separation groove;
A step of embedding an insulating film in the isolation trench to form an element isolation layer,
The step of forming the separation groove includes:
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by wet etching;
A method of manufacturing a semiconductor device comprising a step of performing a groove deepening process by dry etching. The step of forming the separation groove includes:
Forming a shallow groove having a width wider than the opening in the silicon substrate located under the opening by isotropic wet etching using an acid solution to the base film in the vicinity of the opening of the silicon substrate;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution to the shallow groove portion;
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a groove deepening process by dry etching of the opening to the exposed portion of the silicon substrate. The step of forming the separation groove includes:
Forming a shallow groove having a width wider than the opening in the silicon substrate located under the opening by isotropic wet etching using an acid solution for the base film in the vicinity of the opening of the silicon substrate;
Implanting boron ions into the silicon substrate in the opening;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution to the shallow groove portion;
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing a groove deepening process by dry etching of the opening to the exposed portion of the silicon substrate. The step of forming the separation groove includes:
Implanting boron ions into the silicon substrate in the opening;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution;
Depositing an insulating film such that both ends of the (111) plane of the inverted trapezoidal groove are partially masked;
A step of performing a groove deepening process by dry etching the silicon substrate exposed portion of the opening;
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of removing the deposited insulating film. The step of forming the separation groove includes:
Implanting boron ions into the silicon substrate in the opening;
Forming an inverted trapezoidal groove in the exposed portion of the silicon substrate by anisotropic wet etching using an alkaline solution;
Depositing an insulating film so that the entire (111) surface of the inverted trapezoidal groove is masked;
A step of performing a groove deepening process by dry etching the silicon substrate exposed portion of the opening;
Removing the deposited insulating film;
The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming an inverted trapezoidal shape at the bottom of the separation groove by anisotropic wet etching using an alkaline solution. In the wet etching, an anisotropic etching process of (111) is performed on the exposed portion using an alkaline solution, and the processing is stopped before all the exposed etching surfaces become the (111) plane,
6. The method of manufacturing a semiconductor device according to claim 1, wherein the dry etching for the groove deepening process is performed while maintaining the (111) plane.   The semiconductor device manufacturing method according to claim 1, further comprising a step of performing rounding oxidation of the separation groove using an oxygen radical oxidation method after the step of forming the separation groove. Method.   The method further comprises a step of filling the separation groove, a step of flattening the surface, and a step of performing etch back after the surface is flattened after the step of forming the separation groove. A method for manufacturing a semiconductor device according to claim 6. (100) having a silicon substrate, a separation groove, and an insulator embedded in the separation groove,
The semiconductor has a (100) plane on the bottom, a (111) plane on the bottom end, a (011) plane on the side, and a (111) plane on the side upper end. apparatus.   The semiconductor device according to claim 9, wherein a (111) plane at the upper end portion of the side surface of the separation groove is wider than a (111) plane at the bottom end portion.   The semiconductor device according to claim 9, wherein a length of the side surface of the separation groove is 300 to 400 nm.   The semiconductor device according to claim 9, wherein a width of an upper end of the separation groove is larger than a width of a bottom surface of the separation groove.

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