CN105826263A - Transistor forming method - Google Patents
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- CN105826263A CN105826263A CN201510010128.0A CN201510010128A CN105826263A CN 105826263 A CN105826263 A CN 105826263A CN 201510010128 A CN201510010128 A CN 201510010128A CN 105826263 A CN105826263 A CN 105826263A
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Abstract
The invention discloses a transistor forming method. The method comprises steps: a semiconductor substrate is provided, wherein the semiconductor substrate comprises an NMOS area and a PMOS area; a first gate dielectric layer, a first capping layer and a first pseudo gate covering part of the PMOS area are formed, and a second gate dielectric layer, a second capping layer and a second pseudo gate covering part of the NMOS area are formed; a dielectric layer is formed on the surface of the semiconductor substrate, and the surface of the dielectric layer is flush with the surface of the first pseudo gate and the surface of the second pseudo gate; the first pseudo gate is removed to form a first groove; a first work function layer and a first gate are formed in the first groove; first annealing treatment is carried out in an oxygen atmosphere to enable the surface of the first gate and the surface of the second pseudo gate to be oxidized; second annealing treatment is carried out on the second pseudo gate in a hydrogen atmosphere; the second pseudo gate is removed to form a second groove; and a second work function layer and a second gate are formed in the second groove. Thus, the method of the invention can improve the performance of the formed transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly to the forming method of a kind of transistor.
Background technology
Along with improving constantly of semiconductor device integrated level, the reduction of technology node, traditional gate dielectric layer is the most thinning, and transistor leakage amount increases therewith, causes the problems such as semiconductor device power wastage.For solving the problems referred to above, prior art provides a kind of solution that metal gates substitutes polysilicon gate.Wherein, " rear grid (gatelast) " technique is the main technique forming high-K metal gate gated transistors.
The method of existing formation high-K metal gate gated transistors includes: provide Semiconductor substrate, it is formed with gate dielectric layer in described Semiconductor substrate and covers the dummy grid of gate dielectric layer, and it being positioned in described Semiconductor substrate and covers the dielectric layer of described gate dielectric layer and dummy grid, the surface of described dielectric layer flushes with dummy grid surface；Groove is formed after removing dummy gate structure；Sequentially forming work-function layer and metal level in described groove, described metal level fills full groove, as the metal gates of transistor.
When after using on a semiconductor substrate, grid technique concurrently forms nmos pass transistor and PMOS transistor, need the dummy grid first removing in PMOS area, form the metal gates of PMOS transistor, then remove the dummy grid in NMOS area, form the metal gates of nmos pass transistor.During the metal gates forming nmos pass transistor, the metal gates that easy pair pmos transistor has been formed causes damage, thus affects the performance of PMOS transistor.
The performance using the transistor that above-mentioned rear grid technique formed needs further to be improved.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of transistor, improves the performance of the transistor formed.
For solving the problems referred to above, the present invention provides the forming method of a kind of transistor, including: providing Semiconductor substrate, described Semiconductor substrate includes NMOS area and PMOS area；Formed covering part PMOS area first grid dielectric layer, be positioned at first grid dielectric layer surface the first cap and be positioned at the first cap surface the first dummy grid and formed covering part NMOS area second gate dielectric layer, be positioned at the second cap of second gate dielectric layer surface and be positioned at second dummy grid on the second cap surface；Forming dielectric layer at described semiconductor substrate surface, the surface of described dielectric layer flushes with the surface of the first dummy grid, the second dummy grid；Remove the first dummy grid, PMOS area is formed the first groove；In described first groove, form the first work-function layer and be positioned at the first grid of described first full described first groove of work-function layer surface filling；Carry out the first annealing under an oxygen-containing atmosphere, make first grid and the second dummy grid surface oxidized；Under an atmosphere of hydrogen the second dummy grid is carried out the second annealing；Remove described second dummy grid, form the second groove on an nmos area；In described second groove, form the second work-function layer and be positioned at the second grid of described second full described second groove of work-function layer surface filling.
Optionally, described first dummy grid includes the first polysilicon layer, the first doped polysilicon layer doped with non-proliferation ion being positioned at the first polysilicon layer surface and the first amorphous silicon layer；Described second dummy grid includes the second polysilicon layer, the second doped polysilicon layer doped with non-proliferation ion being positioned at many second crystal silicon layer surfaces and the second amorphous silicon layer.
Optionally, the non-proliferation ion in described doped polysilicon layer includes C, Ge, As, P or B.
Optionally, the doping content scope of described non-proliferation ion is 0.5E13atom/cm3～5E14atom/cm3。
Optionally, the atmosphere of described first annealing also includes nitrogenous gas.
Optionally, described first annealing is including N2O and NH3Atmosphere under carry out.
Optionally, the temperature of described first annealing is 600 DEG C～1200 DEG C, and the time is 10ms～10s.
Optionally, the temperature of described second annealing is 600 DEG C～1200 DEG C, and the time is 10ms～10s.
Optionally, before carrying out the second annealing, forming the mask layer exposing the second dummy grid, the material of described mask layer is TiN, SiN or SiON.
Optionally, before forming described dielectric layer, also include: in the PMOS area of described first dummy grid both sides, form the first source-drain electrode, in the NMOS area of described second dummy grid both sides, form the second source-drain electrode.
Optionally, dry etch process is used to remove described first dummy grid and the second dummy grid.
Optionally, the gas that described dry etch process uses includes that the flow velocity of HBr and Ar, HBr is 10sccm～1000sccm, and the flow velocity of Ar is 10sccm～1000sccm.
Optionally, after removing described first dummy grid, described first groove is carried out wet-cleaning.
Optionally, the cleaning solution that described wet-cleaning uses includes HCl and H2O2Mixed solution or NH4OH and H2O2Mixed solution.
Optionally, after removing described second dummy grid, dry etch process is used to perform etching post-processing step.
Optionally, the etching gas that described etching post-processing step uses includes: CF4And Cl2, wherein CF4With Cl2Gas flow be than for 80:20～65:35.
Optionally, the method forming described first grid dielectric layer, the first cap, the first dummy grid, second gate dielectric layer, the second cap and the second dummy grid includes: sequentially form gate dielectric material layer, cap material layer, dummy grid material layer at described semiconductor substrate surface；Etching dummy gate pole material layer, cap material layer and gate dielectric material layer, form first grid dielectric layer, the first cap and the first dummy grid being positioned in PMOS area, the second gate dielectric layer being positioned in NMOS area, the second cap and the second dummy grid.
Optionally, the material of described first grid dielectric layer and second gate dielectric layer is hafnium oxide, zirconium oxide, aluminium oxide or silicon hafnium oxide, and the material of described first cap and the second cap is TiN.
Optionally, the material of described first work-function layer is TiN, and the material of the second work-function layer is TiAl or TiC.
Optionally, the material of described first grid and second grid includes aluminum, copper, silver, platinum, tungsten or tungsten nitride.
Compared with prior art, technical scheme has the advantage that
In the forming method of the transistor of technical scheme, the PMOS area of Semiconductor substrate forms first grid dielectric layer, the first cap and the first dummy grid, on an nmos area formation second gate dielectric layer, the second cap and the second dummy grid；Then forming dielectric layer at described semiconductor substrate surface, the surface of described dielectric layer flushes with the surface of the first dummy grid, the second dummy grid；After removing the first dummy grid, PMOS area forms the first groove；Then in the first groove, form the first work-function layer and first grid；Carry out the first annealing the most under an oxygen-containing atmosphere, make first grid and the second dummy grid surface oxidized；Then before removing the second dummy grid, under an atmosphere of hydrogen the second dummy grid is carried out the second annealing, the oxide that second grid surface is oxidized to form reduces, so during removing the second dummy grid, the damage to dielectric layer can be reduced, thus improve the performance of the transistor of formation, the second work-function layer and second grid is formed the most again in removing the second groove that the second dummy grid is formed, the oxide that described first annealing is formed on first grid surface can protect described first grid during forming the second work function and second grid.
Further, described second dummy grid includes the second polysilicon layer, the second doped polysilicon layer doped with non-proliferation ion being positioned at many second crystal silicon layer surfaces and the second amorphous silicon layer.In carrying out the first annealing process, the oxygen atom in described atmosphere can penetrate in the second dummy grid, forms silicon oxide with the pasc reaction in the second dummy grid, is unfavorable for follow-up removal the second dummy grid.The association that non-proliferation ion in described second doped polysilicon layer is formed with silicon atom can effectively reduce the gap in silicon, thus stop oxygen atom to diffuse to downwards the bottom of the second dummy grid, avoid the second bottom portion of groove residual oxidization silicon formed after removing described second dummy grid, affect the quality of the second work-function layer and the second grid being subsequently formed.
Further, the atmosphere of described first annealing also includes nitrogenous gas, forms nitride on described first grid surface, it is possible to play a protective role first grid further.
Accompanying drawing explanation
Fig. 1 to Fig. 9 is the structural representation of the forming process of the transistor of the present invention.
Detailed description of the invention
As described in the background art, the performance of the transistor that prior art is formed needs further to be improved.
Prior art, during the metal gates forming nmos pass transistor, is easily damaged work-function layer and metal gates that PMOS transistor has been formed, thus is affected the performance of PMOS transistor when metal gates is carried out cmp.
In order to avoid the problems referred to above; can be after forming the metal gates of PMOS transistor; carry out the annealing under oxygen-containing atmosphere; oxide layer is formed, to protect the metal gates of described PMOS transistor while the metal gates of NMOS is carried out chemical machinery mask on the metal gates surface of PMOS transistor.But, during carrying out above-mentioned annealing, oxygen atom can penetrate in the dummy grid of NMOS area, oxide layer is formed on surface, dummy gate pole, follow-up when the dummy grid removed in described NMOS area, need first to remove described oxide layer, easily cause the damage of substrate surface dielectric layer, thus affect the performance of the transistor of formation.
In embodiments of the invention, after first work-function layer and first grid of the PMOS transistor formed in PMOS area, carry out the first annealing under oxygen-containing atmosphere, make first grid and the first dummy grid surface oxidized, then before the second dummy grid removed in NMOS area, under an atmosphere of hydrogen described second dummy grid is carried out the second annealing, the oxide layer making described second dummy grid surface long-living in the first annealing process is reduced, remove the oxygen atom in described oxide layer, make when removing described second dummy grid, the damage to dielectric layer can be reduced.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with the accompanying drawings the specific embodiment of the present invention is described in detail.
Refer to Fig. 1, it is provided that Semiconductor substrate 100, described Semiconductor substrate 100 includes PMOS area and NMOS area.
Described Semiconductor substrate 100 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 100 can also be germanium, germanium silicon, GaAs or germanium on insulator, and the material of Semiconductor substrate 100 described in this enforcement is body silicon.Follow-up formation nmos pass transistor and PMOS transistor respectively in described NMOS area and PMOS area.
It is also formed with fleet plough groove isolation structure 101 in described Semiconductor substrate 100.Described fleet plough groove isolation structure includes the pad oxide being positioned at flute surfaces and is positioned at described pad oxide surface, fills the sealing coat of full groove.
In the present embodiment, isolated by fleet plough groove isolation structure 101 between described NMOS area and PMOS area.
Refer to Fig. 2, the first grid dielectric layer 211 forming covering part PMOS area, the first cap 212 being positioned at first grid dielectric layer 211 surface and be positioned at first dummy grid 213 on the first cap 212 surface and form the second gate dielectric layer 221 of covering part NMOS area, be positioned at second cap 222 on second gate dielectric layer 221 surface and be positioned at second dummy grid 223 on the second cap 222 surface.
The material of described first grid dielectric layer 211 and second gate dielectric layer 221 is high K dielectric material, such as hafnium oxide, zirconium oxide, aluminium oxide or silicon hafnium oxide etc..
The material of described first cap 212 and the second cap 222 is TiN, and described first cap 212 and the second cap 222 are for protecting first grid dielectric layer 211 and the second gate dielectric layer 221 of lower section.
The material of described first dummy grid 213 and the second dummy grid 223 can be non-crystalline silicon.In the present embodiment, described first dummy grid 213 includes the first polysilicon layer 213a, is positioned at the first doped polysilicon layer 213b and the first amorphous silicon layer 213c doped with non-proliferation ion on the first polysilicon layer 213a surface；Described second dummy grid 223 includes the second polysilicon layer 223a, is positioned at the second doped polysilicon layer 223b and the second amorphous silicon layer 223c doped with non-proliferation ion on many second crystal silicon layer 223a surfaces.
In described first doped polysilicon layer 213b and the second doped polysilicon layer 223b, the non-proliferation ion of doping includes C, Ge, As, P or B etc..Above-mentioned non-proliferation ion can form association with silicon atom, it is possible to effectively reduces the gap in silicon, it is to avoid follow-up when annealing the first metal gates in PMOS area, oxygen atom penetrates into bottom the second dummy grid in NMOS area.
In described first doped polysilicon layer 213b and the second doped polysilicon layer 223b, the concentration of the non-proliferation ion of doping is 0.5E13atom/cm3～5E14atom/cm3。
The method forming described first grid dielectric layer 211 and second gate dielectric layer the 221, first cap 212 and second cap the 222, first dummy grid 213 and the second dummy grid 223 includes: sequentially form gate dielectric material layer, cap material layer, dummy grid material layer on described Semiconductor substrate 100 surface；Etching dummy gate pole material layer, cap material layer and gate dielectric material layer, form first grid dielectric layer the 211, first cap 212 and the first dummy grid 213, second gate dielectric layer the 221, second cap 222 being positioned in NMOS area and the second dummy grid 223 being positioned in PMOS area.
Refer to Fig. 3, form side wall 300 in described first grid dielectric layer the 211, first cap 212 and the first dummy grid 213 sidewall surfaces, form side wall 300 in described second gate dielectric layer the 221, second cap 222 and the second dummy grid 223 sidewall surfaces；Then in the PMOS area of described first dummy grid 213 both sides, form the first source-drain electrode 301, in the NMOS area of the second dummy grid 223 both sides, form the second source-drain electrode 302.
The material of described side wall 300 can be the laminated construction of silicon nitride, silicon oxide or silicon nitride and silicon oxide.
After forming described side wall 300, with the side wall 300 of described first dummy grid 213 and both sides thereof as mask, carry out p-type ion implanting in PMOS area to the Semiconductor substrate 100 of described first dummy grid 213 both sides, and make annealing treatment, form the first source-drain electrode 301；With the side wall 300 of described second dummy grid 223 and both sides thereof as mask, the NMOS area of the Semiconductor substrate 100 of described second dummy grid 223 both sides is carried out N-type ion implanting, and makes annealing treatment, form the second source-drain electrode 302.Follow-up formation P-type transistor in described PMOS area, forms N-type transistor in described NMOS area.
Refer to Fig. 4, form dielectric layer 400 in described Semiconductor substrate 100, the surface of described dielectric layer 400 flushes with the top surface of first dummy grid the 213, second dummy grid 223.
The material of described dielectric layer 400 is the dielectric materials such as silicon oxide, p-doped silicon oxide, boron-doping silicon oxide, it is also possible to for low-K dielectric material or ultralow K dielectric material, such as amorphous carbon, silicon containing gas gel etc..Chemical vapor deposition method can be used to form described dielectric layer 400.In the present embodiment, after described Semiconductor substrate 100 forms dielectric material, described dielectric material is planarized, form dielectric layer 400, make the surface of described dielectric layer 400 flush with the top surface of the first dummy grid 213 and the second dummy grid 223.
Refer to Fig. 5, remove the first dummy grid 213 (refer to Fig. 4), PMOS area is formed the first groove 401.
In the present embodiment, dry etch process is used to remove described first dummy grid 213, concrete, in one embodiment of the invention, the etching gas that described dry etch process uses includes HBr and Ar, wherein, the flow velocity of HBr is 10sccm～1000sccm, and the flow velocity of Ar is 10sccm～1000sccm.
In other embodiments of the invention, it would however also be possible to employ wet-etching technology removes described first dummy grid 213, the etching solution that described wet-etching technology uses can be tetramethyl aqua ammonia (TMAH) solution or KOH solution.
Before removing described first dummy grid 213, mask layer, second dummy grid 223 on protection NMOS area surface can be formed in described NMOS area, after removing described first dummy grid 213, remove described mask layer.
During using dry etch process to remove described first dummy grid 213, etching gas can react with material to be etched, produce nonvolatile polymer residue in the groove 401 formed, so, in the present embodiment, after forming described groove 401, use wet clean process, described groove 401 is carried out, to remove described residual impurity.Described cleaning solution can be HCl and H2O2Mixed solution or NH4OH and H2O2Mixed solution etc..
Refer to Fig. 6, in described first groove 401 (refer to Fig. 5), form the first work-function layer 411 and be positioned at the first grid 412 of described first full described first groove 401 of work-function layer 411 surface filling.
The forming method of described first work-function layer 411 and first grid 412 includes: after described first groove 401 inner wall surface and dielectric layer the 400, second dummy grid 223 surface form the first workfunction material, first grid material layer is formed on described first workfunction material surface, described first grid material layer fills full first groove 401, then with described dielectric layer 400 as stop-layer, described first grid material layer and the first workfunction material are planarized, forms described first work-function layer 411 and the first grid 412.
Chemical vapor deposition method, atom layer deposition process or RF physical gas-phase deposition can be used to form described first workfunction material and first grid material layer.
In the present embodiment, the material of described first work-function layer 411 is titanium nitride, for adjusting the work function of PMOS transistor.
In other embodiments of the invention, described first workfunction material 411 can also use the material for regulating PMOS work function that other are commonly used in the art, described first workfunction material 411 can be single layer structure, it is also possible to be the stacked structure of various material layers composition.
The material of described first grid 412 is one or more in aluminum, copper, silver, platinum, tungsten, tungsten nitride, silicide.In the present embodiment, the material of described first grid 412 is Al.
Refer to Fig. 7, carry out the first annealing under an oxygen-containing atmosphere, make first grid 412 and the second dummy grid 223 surface oxidized.
In described first annealing process, oxygen atom reacts with first grid 412 surface, forms the first protective layer 413 on described first grid 412 surface, and the most described oxygen atom also reacts formation the second protective layer 224 with the second dummy grid 223 surface.Described first protective layer 413 can carry out in chemical mechanical planarization process when follow-up removal the second dummy grid 223, the second work-function layer formed in NMOS area, second grid, protects described first grid 412.
In other embodiments of the invention, described second annealing atmosphere also includes nitrogenous gas, and first grid 412 and the second dummy grid 223 surface can be made to be nitrogenized simultaneously.
In the present embodiment, described first annealing is including N2O and NH3Atmosphere under carry out, annealing temperature is 600 DEG C～1200 DEG C, and the time is 10ms～10s.
Described first annealing can use the annealing process such as furnace anneal, spike annealing, rapid thermal annealing, and the time of described annealing can be adjusted according to different annealing.
Including oxide and nitride in the first protective layer 413 that described first annealing is formed, in the present embodiment, the material of described first grid 412 is Al, comprises aluminium oxide and aluminium nitride in described first protective layer 413.
In carrying out the first annealing process, the oxygen atom in described atmosphere can penetrate in the second dummy grid 223, forms silicon oxide with the pasc reaction in the second dummy grid 223, is unfavorable for follow-up removal the second dummy grid 223.
In the present embodiment, described second dummy grid 223 includes the second polysilicon layer 223a, is positioned at the second doped polysilicon layer 223b and the second amorphous silicon layer 223c doped with non-proliferation ion on the second polysilicon layer 223a surface.The association that non-proliferation ion in described second doped polysilicon layer 223b is formed with silicon atom can effectively reduce the gap in silicon, thus stop oxygen atom to diffuse to downwards the bottom of the second dummy grid 223, avoid the second bottom portion of groove residual oxidization silicon formed after removing described second dummy grid 223, affect the quality of the second work-function layer and the second grid being subsequently formed.
Refer to Fig. 8, after under an atmosphere of hydrogen the second dummy grid 223 being carried out the second annealing, remove described second dummy grid 223 (refer to Fig. 7).
Second dummy grid 223 is carried out by described second annealing, so, before carrying out described annealing, described dielectric layer 400 forming mask layer, described mask layer exposes the surface of the second dummy grid 223 to be etched.The material of described mask layer can be TiN, SiN, SiON etc..After carrying out described second annealing, remove described mask layer.
Described second annealing is carried out under an atmosphere of hydrogen, and described hydrogen is reducibility gas, it is possible to remove the oxygen atom in second protective layer 224 (refer to Fig. 7) on described second dummy grid 223 surface.The temperature of described second annealing is 600 DEG C～1200 DEG C, and the time is 10ms～10s.
Described second annealing can use the annealing process such as furnace anneal, spike annealing, rapid thermal annealing, and the time of described annealing can be adjusted according to different annealing.
During removing the second dummy grid 223; first have to remove the second protective layer 224 of described second dummy grid 223 top surface; it is mainly composed of silicon oxide due to described second protective layer 224; identical with the material of dielectric layer 400; during removing described second protective layer 224, dielectric layer 400 can be caused also to sustain damage.
Described second annealing can reduce the silica content in second protective layer 224 on the second dummy grid 223 surface, follow-up during removing described second protective layer 224, reduces the damage to dielectric layer 400.
After carrying out described second annealing, remove described second protective layer 224 and the second dummy grid 223.
Wet method or dry etch process can be used to remove described second protective layer 224, and described wet etching can use hydrofluoric acid solution, described dry etch process can use CF4、C2F6Deng fluoro-gas.
Then use dry etch process to remove described second dummy grid 223, in the present embodiment, use dry etch process to remove described second dummy grid 223.
Concrete, in one embodiment of the invention, the etching gas that described dry etch process uses includes HBr and Ar, and wherein, the flow velocity of HBr is 10sccm～1000sccm, and the flow velocity of Ar is 10sccm～1000sccm.
In other embodiments of the invention, it would however also be possible to employ other etching gas carry out above-mentioned etching, to remove described second dummy grid 223.
In the present embodiment, after removing described second dummy grid 223, form the second groove 402 on an nmos area, then using dry etch process to perform etching post-processing step, before described etching post-processing step is mainly used in removing, dry etching removes the polymer produced during the second dummy grid 223 and oxide residual.Dry etch process is compared with wet-etching technology, it is possible to reduce the damage to the first protective layer 413 in dielectric layer 400 and PMOS area.
In prior art, typically use CF4Carry out above-mentioned etching post-processing step, but CF4First protective layer 413 is had higher etching rate, easily make described first protective layer 413 be removed or thickness decline, follow-up carry out cmp during be not enough to protect first grid 412.
In the present embodiment, use CF4And Cl2Mixed gas carries out dry etching, to complete described etching post-processing step, described CF4And Cl2Mixed gas for the etch rate of polymer and silicon oxide more than the etch rate of the first protective layer 413 such that it is able to reduce the damage to described first protective layer 413.Described CF4With Cl2Gas flow be than for 80:20～65:35.In one embodiment of the invention, described CF4Gas flow be 75sccm, Cl2Flow be 25sccm.
Refer to Fig. 9, in described second groove 402 (refer to Fig. 8), form the second work-function layer 421 and be positioned at the second grid 422 of described second full described second groove 402 of work-function layer 421 surface filling.
The material of described second work-function layer 421 is TiAl, and in other described examples of the present invention, the material of described second work-function layer 421 can also is that TiC.In other embodiments of the invention, described second work-function layer 421 can also use the material for regulating nmos pass transistor work function that other are commonly used in the art.
The material of described second grid 422 is one or more in aluminum, copper, silver, platinum, tungsten, tungsten nitride, silicide.In the present embodiment, the material of described second grid 422 is Al.
The forming method of described second work-function layer 421 and second grid 422 includes: after described second groove 402 inner wall surface and dielectric layer the 400, first protective layer 413 surface form the second workfunction material; second grid material layer is formed on described second workfunction material surface; described second grid material layer fills full second groove 402; then with described dielectric layer 400 as stop-layer; described second grid material layer and the second workfunction material are planarized, forms described second work-function layer 421 and second gate 422.
Chemical vapor deposition method, atom layer deposition process or RF physical gas-phase deposition can be used to form described first workfunction material and first grid material layer.
Use chemical mechanical milling tech that described second grid material layer and the second workfunction material are planarized; described first grid 412 protected during carrying out cmp by described first protective layer 413; avoid being formed on described first grid 412 surface the defects such as depression, thus improve the performance of the transistor of formation.
In the present embodiment, after forming described second work-function layer 421 and second grid 422, the first protective layer 413 of described first grid 412 surface also member-retaining portion thickness.
In other embodiments of the invention, during forming described second work-function layer 421 and second grid 422, described first protective layer 413 is removed completely.
In embodiments of the invention, the PMOS area of Semiconductor substrate forms first grid dielectric layer, the first cap and the first dummy grid, on an nmos area formation second gate dielectric layer, the second cap and the second dummy grid；Then forming dielectric layer at described semiconductor substrate surface, the surface of described dielectric layer flushes with the surface of the first dummy grid, the second dummy grid；After removing the first dummy grid, PMOS area forms the first groove；Then in the first groove, form the first work-function layer and first grid；Carry out the first annealing the most under an oxygen-containing atmosphere, make first grid and the second dummy grid surface oxidized；Then before removing the second dummy grid, under an atmosphere of hydrogen the second dummy grid is carried out the second annealing, the oxide that second grid surface is oxidized to form reduces, so during removing the second dummy grid, the damage to dielectric layer can be reduced, thus improve the performance of the transistor of formation, the second work-function layer and second grid is formed the most again in removing the second groove that the second dummy grid is formed, the oxide that described first annealing is formed on first grid surface can protect described first grid during forming the second work function and second grid.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. the forming method of a transistor, it is characterised in that including:
Thering is provided Semiconductor substrate, described Semiconductor substrate includes NMOS area and PMOS area；
Form the first grid dielectric layer of covering part PMOS area, be positioned at the first cap of first grid dielectric layer surface and be positioned at first dummy grid on the first cap surface, form the second gate dielectric layer of covering part NMOS area, be positioned at the second cap of second gate dielectric layer surface and be positioned at second dummy grid on the second cap surface；
Forming dielectric layer at described semiconductor substrate surface, the surface of described dielectric layer flushes with the surface of the first dummy grid, the second dummy grid；
Remove the first dummy grid, PMOS area is formed the first groove；
In described first groove, form the first work-function layer and be positioned at the first grid of described first full described first groove of work-function layer surface filling；
Carry out the first annealing under an oxygen-containing atmosphere, make first grid and the second dummy grid surface oxidized；
Under an atmosphere of hydrogen the second dummy grid is carried out the second annealing；
Remove described second dummy grid, form the second groove on an nmos area；
In described second groove, form the second work-function layer and be positioned at the second grid of described second full described second groove of work-function layer surface filling.
The forming method of transistor the most according to claim 1, it is characterised in that described first dummy grid includes the first polysilicon layer, the first doped polysilicon layer doped with non-proliferation ion being positioned at the first polysilicon layer surface and the first amorphous silicon layer；Described second dummy grid includes the second polysilicon layer, the second doped polysilicon layer doped with non-proliferation ion being positioned at many second crystal silicon layer surfaces and the second amorphous silicon layer.
The forming method of transistor the most according to claim 2, it is characterised in that the non-proliferation ion in described doped polysilicon layer includes C, Ge, As, P or B.
The forming method of transistor the most according to claim 2, it is characterised in that the doping content scope of described non-proliferation ion is 0.5E13atom/cm3～5E14atom/cm3。
The forming method of transistor the most according to claim 1, it is characterised in that the atmosphere of described first annealing also includes nitrogenous gas.
The forming method of transistor the most according to claim 5, it is characterised in that described first annealing is including N2O and NH3Atmosphere under carry out.
The forming method of transistor the most according to claim 6, it is characterised in that the temperature of described first annealing is 600 DEG C～1200 DEG C, and the time is 10ms～10s.
The forming method of transistor the most according to claim 1, it is characterised in that the temperature of described second annealing is 600 DEG C～1200 DEG C, and the time is 10ms～10s.
The forming method of transistor the most according to claim 1, it is characterised in that before carrying out the second annealing, forms the mask layer exposing the second dummy grid, and the material of described mask layer is TiN, SiN or SiON.
The forming method of transistor the most according to claim 1, it is characterized in that, before forming described dielectric layer, also include: in the PMOS area of described first dummy grid both sides, form the first source-drain electrode, in the NMOS area of described second dummy grid both sides, form the second source-drain electrode.
The forming method of 11. transistors according to claim 1, it is characterised in that use dry etch process to remove described first dummy grid and the second dummy grid.
The forming method of 12. transistors according to claim 11, it is characterised in that the gas that described dry etch process uses includes that the flow velocity of HBr and Ar, HBr is 10sccm～1000sccm, and the flow velocity of Ar is 10sccm～1000sccm.
The forming method of 13. transistors according to claim 1, it is characterised in that after removing described first dummy grid, described first groove is carried out wet-cleaning.
The forming method of 14. transistors according to claim 13, it is characterised in that the cleaning solution that described wet-cleaning uses includes HCl and H2O2Mixed solution or NH4OH and H2O2Mixed solution.
The forming method of 15. transistors according to claim 1, it is characterised in that after removing described second dummy grid, uses dry etch process to perform etching post-processing step.
The forming method of 16. transistors according to claim 15, it is characterised in that the etching gas that described etching post-processing step uses includes: CF4And Cl2, wherein CF4With Cl2Gas flow be than for 80:20～65:35.
The forming method of 17. transistors according to claim 1, it is characterized in that, the method forming described first grid dielectric layer, the first cap, the first dummy grid, second gate dielectric layer, the second cap and the second dummy grid includes: sequentially form gate dielectric material layer, cap material layer, dummy grid material layer at described semiconductor substrate surface；Etching dummy gate pole material layer, cap material layer and gate dielectric material layer, form first grid dielectric layer, the first cap and the first dummy grid being positioned in PMOS area, the second gate dielectric layer being positioned in NMOS area, the second cap and the second dummy grid.
The forming method of 18. transistors according to claim 1, it is characterised in that the material of described first grid dielectric layer and second gate dielectric layer is hafnium oxide, zirconium oxide, aluminium oxide or silicon hafnium oxide, the material of described first cap and the second cap is TiN.
The forming method of 19. transistors according to claim 1, it is characterised in that the material of described first work-function layer is TiN, the material of the second work-function layer is TiAl or TiC.
The forming method of 20. transistors according to claim 1, it is characterised in that the material of described first grid and second grid includes aluminum, copper, silver, platinum, tungsten or tungsten nitride.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6406956B1 (en) * | 2001-04-30 | 2002-06-18 | Taiwan Semiconductor Manufacturing Company | Poly resistor structure for damascene metal gate |
| US20060017098A1 (en) * | 2004-07-20 | 2006-01-26 | Doczy Mark L | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
| CN103730418A (en) * | 2012-10-10 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104253047A (en) * | 2013-06-26 | 2014-12-31 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistor |
| CN104253029A (en) * | 2013-06-26 | 2014-12-31 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistors |
-
2015
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6406956B1 (en) * | 2001-04-30 | 2002-06-18 | Taiwan Semiconductor Manufacturing Company | Poly resistor structure for damascene metal gate |
| US20060017098A1 (en) * | 2004-07-20 | 2006-01-26 | Doczy Mark L | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
| CN103730418A (en) * | 2012-10-10 | 2014-04-16 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN104253047A (en) * | 2013-06-26 | 2014-12-31 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistor |
| CN104253029A (en) * | 2013-06-26 | 2014-12-31 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistors |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108648996A (en) * | 2018-05-03 | 2018-10-12 | 武汉新芯集成电路制造有限公司 | A method of reducing floating boom square resistance |
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