CN107039273B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN107039273B CN107039273B CN201610079609.1A CN201610079609A CN107039273B CN 107039273 B CN107039273 B CN 107039273B CN 201610079609 A CN201610079609 A CN 201610079609A CN 107039273 B CN107039273 B CN 107039273B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
Abstract
A kind of forming method of transistor, comprising: provide semiconductor substrate, the semiconductor substrate includes first area, and the semiconductor substrate surface has dielectric layer and penetrates the first groove of the dielectric layer, and first groove is located on first area；Gate dielectric layer, the cap positioned at gate dielectric layer surface are sequentially formed in the inner wall surface of first groove；The first mask layer is formed in the nut cap layer surface, the first mask layer covering is located at the part cap of the first bottom portion of groove；Using first mask layer as exposure mask, removal is located at the cap in the first recess sidewall, exposes the gate dielectric layer surface on the first recess sidewall surface；First mask layer is removed, the etching barrier layer for covering the gate dielectric layer and cap is formed；Work-function layer is formed on the etching barrier layer；The grid layer for filling full first groove is formed in work-function layer.The performance for the transistor to be formed can be improved in the above method.
Description
Technical field
The present invention relates to technical field of semiconductors, the in particular to forming method of transistor.
Background technique
With the continuous improvement of semiconductor devices integrated level, the reduction of technology node, traditional gate dielectric layer is constantly thinning,
The problems such as transistor leakage amount increases therewith, causes semiconductor devices power wastage.To solve the above problems, the prior art provides
A kind of solution by metal gates substitution polysilicon gate.Wherein, " rear grid (gate last) " technique is to form high karat gold
Belong to a main technique of gridistor.
The existing method that high-K metal gate gated transistors are formed using post tensioned unbonded prestressed concrete technique, comprising: semiconductor substrate, institute are provided
State pseudo- grid structure is formed in semiconductor substrate and in the semiconductor substrate and cover dummy gate structure interlayer be situated between
Matter layer, dummy gate structure include the pseudo- gate dielectric layer and the pseudo- gate dielectric layer surface positioned at the semiconductor substrate surface
Dummy grid, the surface of the interlayer dielectric layer are flushed with pseudo- grid structure surface；Groove is formed after removal dummy gate structure；Institute
It states and sequentially forms high-K gate dielectric layer, metal layer in groove, the metal layer fills full groove, the metal gates as transistor.
The performance for the transistor that the prior art is formed need further to improve.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of transistor, improves the performance of the transistor of formation.
To solve the above problems, the present invention provides a kind of forming method of transistor, comprising: provide semiconductor substrate, institute
Stating semiconductor substrate includes first area, and the semiconductor substrate surface has dielectric layer and penetrates the first recessed of the dielectric layer
Slot, first groove are located on first area；Gate dielectric layer is sequentially formed, positioned at grid in the inner wall surface of first groove
The cap of dielectric layer surface；The first mask layer is formed in the nut cap layer surface, the first mask layer covering is located at first
The part cap of bottom portion of groove；Using first mask layer as exposure mask, removal is located at the cap in the first recess sidewall, cruelly
Expose the gate dielectric layer surface on the first recess sidewall surface；Remove first mask layer, formed cover the gate dielectric layer and
The etching barrier layer of cap；Work-function layer is formed on the etching barrier layer；Filling full first is formed in work-function layer
The grid layer of groove.
Optionally, the semiconductor substrate further includes second area, also has to penetrate in the semiconductor substrate and be given an account of
Second groove of matter layer, second groove are located on second area；Simultaneously in the inner wall of first groove and the second groove
Surface forms gate dielectric layer, the cap positioned at gate dielectric layer surface；First mask layer, which also covers, is located at the second groove-bottom
The part cap in portion；The grid layer also fills up full second groove.
Optionally, first mask layer with a thickness of
Optionally, the material of first mask layer includes amorphous silicon, silicon oxide or silicon nitride.
Optionally, the forming method of first mask layer includes: using physical gas-phase deposition in nut cap layer surface
The first mask layer is formed, the thickness of the first mask layer in the first recess sidewall, the second recess sidewall is less than
Positioned at the thickness of the first groove and the first mask layer of the second bottom portion of groove；Removal is recessed positioned at the first recess sidewall and second
The first mask layer in groove sidewall forms the first mask layer for being located at the first bottom portion of groove and the second bottom portion of groove.
Optionally, using wet-etching technology removal first in the first recess sidewall and the second recess sidewall
Mask layer.
Optionally, the first mask layer is formed using sputtering technology.
Optionally, the thickness of the first mask layer in the first recess sidewall, the second recess sidewall be located at the
The ratio between one bottom portion of groove, thickness of the first mask layer of the second bottom portion of groove are less than 2:3.
Optionally, the work-function layer in the first groove includes the second work-function layer；Work content in the second groove
Several layers include the first work-function layer and the second work-function layer positioned at first work-function layer surface, first work-function layer
Only covering is located at the etching barrier layer of the second bottom portion of groove, and second work-function layer covers first work-function layer and second
Etching barrier layer in recess sidewall.
Optionally, the forming method of first work-function layer includes: to form the first work function of covering etching barrier layer
Material layer；Form the second mask layer that covering is located at the first workfunction material of part of the first groove and the second bottom portion of groove；
Using second mask layer as exposure mask, removal is located at the first work function material of part on the first groove and the second recess sidewall
Layer forms the first work-function layer for being located at the first groove and the second bottom portion of groove；Remove second mask layer；It is recessed to remove first
The first work-function layer in slot.
Optionally, the material of the work-function layer is TiAl or TiAlC.
Optionally, the work-function layer includes the first work-function layer and the second function positioned at first work-function layer surface
Function layer, first work-function layer only cover the etching barrier layer positioned at the first bottom portion of groove, and second work-function layer is covered
Cover the etching barrier layer in first work-function layer and the first recess sidewall.
Optionally, the forming method of first work-function layer includes: to form the first function for covering entire etching barrier layer
Function material layer；Form the second mask layer that covering is located at the first work-function layer of part of the first bottom portion of groove；With described second
Mask layer is exposure mask, and removal is located at the first workfunction material of part in the first recess sidewall, is formed and is located at the first groove-bottom
First work-function layer in portion；Remove second mask layer.
Optionally, the forming method of second mask layer includes: using physical gas-phase deposition in the first work function
Material surface forms the second mask layer, and the thickness of the second mask layer in the first recess sidewall, which is less than, to be located at
The thickness of first mask layer of the second bottom portion of groove；Removal is located at the second mask layer in the first recess sidewall, shape
At the second mask layer of part the first work function material layer surface for being located at the first bottom portion of groove.
Optionally, second mask layer with a thickness of
Optionally, using wet-etching technology removal second mask layer in the first recess sidewall.
Optionally, the thickness of the second mask layer in the first recess sidewall be located at the of the first bottom portion of groove
The ratio between thickness of two mask layers is less than 2:3.
Optionally, the material of second mask layer includes amorphous silicon, silicon oxide or silicon nitride.
Optionally, the material of first work-function layer is TiN, the material of second work-function layer be TiAl or
TiAlC。
Optionally, further includes: form grid after work-function layer surface forms soakage layer, then in the infiltration layer surface
Layer.
Compared with prior art, technical solution of the present invention has the advantage that
In technical solution of the present invention, after forming cap, the first mask layer, institute are formed in the nut cap layer surface
State the part cap that the covering of the first mask layer is located at the first bottom portion of groove；Then using first mask layer as exposure mask, removal
Cap in the first recess sidewall；Then remove the first mask layer, then in first groove formed work-function layer,
Grid layer.The removal cap in the first recess sidewall, can be improved first groove and is not filled part
Width improves the filling quality of the grid layer formed in the first groove, also, improves the width of grid layer, improves the grid
Pole layer is to the control ability of barrier potential difference between the drain electrode and channel of transistor, to improve the performance of transistor.
Further, the work-function layer includes the first work-function layer and the second function positioned at first work-function layer surface
Function layer, first work-function layer only cover the etching barrier layer positioned at the first bottom portion of groove, and second work-function layer is covered
Cover the etching barrier layer in first work-function layer and the first recess sidewall.It is located at since first work-function layer only covers
The etching barrier layer of first bottom portion of groove improves recessed first so improving the width that first groove is not filled part
The filling quality of the grid layer formed in slot, also, the width of grid layer is improved, improve drain electrode of the grid layer to transistor
The control ability of barrier potential difference between channel, to improve the performance of transistor.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the transistor of the prior art of the invention；
Fig. 2 to Figure 13 is the structural schematic diagram of the transistor of the embodiment of the present invention.
Specific embodiment
As described in the background art, the performance for the transistor that the prior art is formed needs to be further improved.
Referring to FIG. 1, a kind of structural schematic diagram of the transistor formed for the prior art.
The transistor includes semiconductor substrate 10, the gate structure positioned at 10 surface of semiconductor substrate, is located at grid knot
Source-drain electrode 11 in the semiconductor substrate 10 of structure two sides, the gate structure include first material layer 21 and second material layer 22,
The first material layer 21 is metal gates, including work-function layer and grid layer, part second material layer 22 are located at the first material
Between layer and semiconductor substrate 10, part second material layer 22 covers the side wall of first material layer 21, the second material layer 22
Including gate dielectric layer, positioned at the cap on gate dielectric layer surface etc..
The transistor further includes the metal plug 23 positioned at 11 surface of source-drain electrode.
The size of transistor various pieces influences the performance of transistor very big: the gate structure width of the transistor is
A, the grid width a is smaller, and the distance between gate structure and metal plug 23 are bigger, and the two is less susceptible to be electrically connected
Problem；Effective channel width of the transistor is d, and effective channel width d is bigger, more can control short-channel effect；The crystalline substance
Overlapping widths between the grid and source-drain electrode of body pipe are e, and the overlapping widths are bigger, and the switch performance of transistor is better.When
Mono- timing of the gate structure width a of transistor and effective channel width d, the first material layer 21 as metal gates
Width b is bigger, and the overlapping widths e between grid and source-drain electrode is bigger, control of the metal gates to barrier potential difference between drain electrode and channel
Ability processed is bigger.So reducing the thickness of the second material layer 22 of 21 sidewall surfaces of first material layer, it can be improved metal gates
To the control ability of barrier potential difference between drain electrode and channel, the performance of transistor is improved.
In the embodiment of the present invention, removal is located at the cap of recess sidewall, improves the width of finally formed grid layer,
To improve grid to the control ability of barrier potential difference between drain electrode and channel, the performance of transistor is improved.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Referring to FIG. 2, providing semiconductor substrate 100, the semiconductor substrate 100 includes first area I, the semiconductor
100 surface of substrate has dielectric layer 200 and penetrates the first groove 210 of the dielectric layer 200, and first groove 210 is located at
On the I of first area.
The semiconductor substrate 100 can be silicon or silicon-on-insulator (SOI), and the semiconductor substrate 100 can also be with
It is germanium, germanium silicon, GaAs or germanium on insulator, the material of semiconductor substrate 100 described in this implementation is silicon.
In the present embodiment, the semiconductor substrate 100 further includes second area II, is also had on the semiconductor substrate II
The second groove 220 of the dielectric layer 200 is penetrated, second groove 220 is located on second area II.
In the present embodiment, NMOS transistor is formed on the I of first area, forms PMOS transistor on second area II.
In other embodiments of the invention, PMOS transistor can also be formed on the I of first area, is formed on second area II
NMOS transistor.It is also formed with fleet plough groove isolation structure 101 in the semiconductor substrate 10, as between transistor to be formed
Isolation structure.In other embodiments of the invention, NMOS transistor can also be only formed, or only forms PMOS transistor.
In the semiconductor substrate 100 further include: the 100 first area I of semiconductor substrate positioned at 210 two sides of the first groove
Interior the first source-drain electrode 102, the second source-drain electrode in the 100 second area II of semiconductor substrate of 220 two sides of the second groove
103。
Specifically, the method for forming above structure includes: to provide semiconductor substrate 100, the semiconductor substrate includes the
One region I and second area II；The first pseudo- grid structure is formed on the surface the first area I, is formed on the surface second area II
Second pseudo- grid structure；Side wall 230 is formed in the described first pseudo- grid structure, the second pseudo- grid structure sidewall surfaces；It is pseudo- described first
The first source-drain electrode 102 is formed in the first area I of the semiconductor substrate 100 of grid structure two sides, in the described second pseudo- grid structure two
The second source-drain electrode 103 is formed in the second area II of the semiconductor substrate 100 of side；It is formed on 100 surface of semiconductor substrate
Dielectric layer 200, the surface of the dielectric layer 200 are flushed with the surface of the first pseudo- grid structure, the second pseudo- grid structure；Remove described
One pseudo- grid structure and the second pseudo- grid structure, are respectively formed the first groove 210 and the second groove 220.
Referring to FIG. 3, the inner wall surface in first groove 210 sequentially forms gate dielectric layer 202, is located at gate dielectric layer
The cap 203 on 202 surfaces.
The gate dielectric layer 202 and cap can be formed using chemical vapor deposition process, atom layer deposition process
203.The material of the gate dielectric layer 202 can be the high K dielectric material such as hafnium oxide, zirconium oxide, silicon hafnium oxide or aluminium oxide.Institute
It states cap 203 to be used to that the atom in the subsequent material layer formed in cap to be stopped to diffuse in gate dielectric layer 202, this reality
It applies in example, the material of the cap 203 is TiN.
In the present embodiment, while gate dielectric layer is formed in the inner wall surface of first groove 210 and the second groove 220
202, positioned at the cap 203 on 202 surface of gate dielectric layer.
It is described also to deposit gate dielectric layer 202 and cap 203 on 200 surface of dielectric layer in the process that is actually formed, it is subsequent
The material layers such as the work-function layer formed in step can also be formed on dielectric layer 200, may finally be removed by flatening process
Each material layer on dielectric layer 200 is to draw to form dielectric layer in the attached drawing of the present embodiment for the sake of simply understanding
Each material layer on 200.
It further include in the first groove 210, the second groove 220 before forming the gate dielectric layer 202 in the present embodiment
100 surface of semiconductor substrate of bottom forms boundary layer 201, and the material of the boundary layer 201 is silica, can pass through hot oxygen
Chemical industry skill forms the boundary layer 201.The boundary layer 201 can be improved between semiconductor substrate 100 and gate dielectric layer 202
Interface quality.
Then, the first mask layer is formed on 203 surface of cap, the first mask layer covering is located at the first groove
The forming method of the part cap of bottom, first mask layer please refers to Fig. 4 to Fig. 5.
Referring to FIG. 4, forming the first exposure mask on 203 surface of cap using physical gas-phase deposition in the present embodiment
The thickness of material layer 204, the first mask layer 204 on 210 side wall of the first groove, 220 side wall of the second groove is less than
Positioned at the thickness of the first mask layer 204 of 220 bottom of the first groove 210 and the second groove.
The physical gas-phase deposition can be sputtering technology, since sputtering technology has stronger directionality, in water
Deposition rate in plane is greater than the deposition rate of vertical plane, so the first mask layer 204 formed is in recess sidewall
Thickness be less than bottom portion of groove thickness.In the present embodiment, on 210 side wall of the first groove, 210 side wall of the second groove
The thickness of one mask layer 204 and the first mask layer 204 for being located at 210 bottom of the first groove, 220 bottom of the second groove
The ratio between thickness be less than 2:3.
The material of first mask layer 204 includes that amorphous silicon, silicon oxide or silicon nitride etc. have with cap 203
The material of higher etching selection ratio.In the present embodiment, the material of first mask layer 204 is amorphous silicon, specifically, adopting
Use monocrystalline silicon as sputtering target material, for argon gas as sputter gas, sputtering power is 50W~500W, and temperature is 150 DEG C~500 DEG C.
In the present embodiment, the first mask layer 204 on 210 side wall of the first groove, 210 side wall of the second groove
With a thickness ofPositioned at the thickness of the first mask layer 204 of 210 bottom of the first groove, 220 bottom of the second groove
Degree is
Referring to FIG. 5, removal is located at the first mask layer on 220 side wall of 210 side wall of the first groove and the second groove
204 (please referring to Fig. 4) form the first mask layer 205 for being located at 220 bottom of 210 bottom of the first groove and the second groove.
Using wet-etching technology removal first on 220 side wall of 210 side wall of the first groove and the second groove
Mask layer 204.Specifically, the etching solution that the wet-etching technology uses can be HF and HNO3Mixed solution.
Thickness due to being located at the first mask layer 204 of bottom portion of groove is greater than the first exposure mask being located in recess sidewall
The thickness of material layer 204, so, it is removed when by the first mask layer 203 on the first groove 210,220 side wall of the second groove
Later, there are also the first mask layers of segment thickness for the first groove 210,220 bottom of the second groove, as the first mask layer
205.In the present embodiment, first mask layer 205 with a thickness ofSo that first mask layer 205 has
Mask layer of the enough thickness as subsequent etching cap 203.
Referring to FIG. 6, being exposure mask with first mask layer 205, removal is located at the cap on 210 side wall of the first groove
203 (please referring to Fig. 5) expose 202 surface of gate dielectric layer of 210 sidewall surfaces of the first groove.
The cap 203 is etched using wet-etching technology, to remove the position not covered by the first mask layer 205
Cap 203 on 210 side wall of the first groove forms the cap 203a being located at after the etching of 210 bottom of the first groove.
In the present embodiment, while the cap 203 being located on 220 side wall of the second groove is removed, is formed and be located at the second groove
The cap 203a of 220 bottoms.
The etching solution that the wet-etching technology uses can be NH4OH and H2O2Mixed aqueous solution, to the nut cap
203 Etch selectivity with higher of layer, and other materials layer will not be caused to corrode.It can be made by the time of control etching
The cap 203 obtained on the first groove 210,220 side wall of the second groove is removed, and does not damage the first groove 210, second
The cap 203a of 220 bottom of groove.
In other embodiments of the invention, the cap 203 can also be etched using dry etch process.It is described dry
Method etching technics can use Cl2、CHCl3Or CF4Have highly selective gas as etching Deng the material to cap 203
Gas.
Removal is located at after the cap 203 on 220 side wall of the first groove 210 and the second groove, so that the first groove
210, the width that the second groove 220 is not filled by part increases, to be conducive to improve subsequent in the first groove 210 and the second groove
Work-function layer, the filling quality of grid layer and the width of grid layer formed in 220 improves grid layer to drain electrode and channel
Between barrier potential difference control ability, to improve the performance of the transistor of formation.
Referring to FIG. 7, removal first mask layer 205 (please referring to Fig. 6), forms and covers 202 He of gate dielectric layer
The etching barrier layer 206 of cap 203a after etching.
Can remove first mask layer 205 using wet-etching technology, the wet-etching technology using HF and
The mixed solution of HNO3 is as etching solution.In other embodiments of the invention, it can also be removed using dry etch process
First mask layer 205, the dry etch process can be using fluoro-gas such as CF4, CHF3 as etching gas.
After removing first mask layer 205, the nut cap of first groove 210,220 bottom of the second groove is exposed
Layer 203a and the gate dielectric layer 202 on the first groove 210,220 side wall of the second groove.
Then, using chemical vapor deposition process or atom layer deposition process in the cap 203a and gate dielectric layer
202 surfaces form etching barrier layer 206.The material of the etching barrier layer 206 is TaN.
Then, then on the etching barrier layer 206 form work-function layer, in the present embodiment, the shape of the work-function layer
Fig. 8 is please referred to Figure 12 at method.
Referring to FIG. 8, forming the first workfunction material 207 for covering entire etching barrier layer 206.
First workfunction material 207 is formed using chemical vapor deposition process or atom layer deposition process.It is described
First workfunction material 207 forms P-type workfunction layer, and in the present embodiment, the material of first workfunction material 207 is
TiN。
Referring to FIG. 9, forming covering is located at the first workfunction material of part 207 of 210 bottom of the first groove second
Mask layer 208.
The forming method of second mask layer 208 is identical as the forming method of the first mask layer 205, specifically includes: adopting
The second mask layer is formed on 207 surface of the first workfunction material with physical gas-phase deposition, is located at the first groove
210, the thickness of the second mask layer on 220 side wall of the second groove, which is less than, is located at the first groove 210,220 bottom of the second groove
The thickness of second mask layer in portion；Second mask material of the removal on the first groove 210,220 side wall of the second groove
Layer forms second exposure mask on 207 surface of the first workfunction material of part positioned at the first groove 210,220 bottom of the second groove
Layer 208.
The physical gas-phase deposition can be sputtering technology, on the first groove 210,220 side wall of the second groove
The second mask layer thickness be located at the first groove 210,220 bottom of the second groove the second mask layer thickness
The ratio between be less than 2:3.
The material of second mask layer 208 includes amorphous silicon, silicon oxide or silicon nitride etc..In the present embodiment, described
The material of two mask layers 208 be amorphous silicon, second mask layer 208 with a thickness of
It can be covered using wet-etching technology removal second on the first groove 210,220 side wall of the second groove
Membrane layers, to form second mask layer 208, the etching solution of use can be HF and HNO3Mixed solution.
Referring to FIG. 10, being exposure mask with second mask layer 208, removal is located at the first groove 210 and the second groove 220
The first workfunction material of part 207 (please referring to Fig. 9) on side wall forms and is located at 220 bottom of the first groove 210 and the second groove
The first work-function layer 207a in portion.
The first work content of part being located on 220 side wall of the first groove 210 and the second groove using wet-etching technology removal
Number material layers 207, in the present embodiment, the wet etching solution used is NH4OH and H2O2Mixed aqueous solution.Control can be passed through
The time of system etching is removed the first workfunction material 207 on the first groove 210,220 side wall of the second groove,
The first work-function layer 207a of the first groove 210,220 bottom of the second groove is not damaged again.
In other embodiments of the invention, first work-function layer 207 can also be etched using dry etch process.
The dry etch process can use Cl2、CHCl3Or CF4Deng the material to the first work-function layer 207 with highly selective
Gas is as etching gas.
Figure 11 is please referred to, second mask layer 208 (please referring to Figure 10) is removed, removes first in the first groove 220
Work-function layer 207a.
Second mask layer 208 is removed using wet-etching technology, the wet-etching technology uses HF and HNO3's
Mixed solution is as etching solution.It in other embodiments of the invention, can also be using dry etch process removal described the
Two mask layers 208.
Since the first work-function layer 207a is P-type workfunction layer, it is suitable for P-type transistor.In the present embodiment, first
NMOS transistor is formed on the I of region, forms PMOS transistor on second area II, it is therefore desirable to remove on the I of first area
First work-function layer 207a.It is formed after coating on second area II, using wet-etching technology or dry etch process
The first work-function layer 207a on the first area I is removed, the etching barrier layer 206 is as the first work-function layer of removal
The etching barrier layer of 207a avoids causing to damage to gate dielectric layer 202.
Figure 12 is please referred to, the first work function in 206 surface of etching barrier layer of the first groove 210, the second groove 220
Layer 207a and 206 surface of etching barrier layer form the second work-function layer 209.
Second work-function layer 209 is N-type workfunction layer, for adjusting the work function of NMOS transistor.The present embodiment
In, the material of second work-function layer 209 is TiAl or TiAlC, can use chemical vapor deposition process or atomic layer deposition
Product technique forms second work-function layer 209.
So far, in the present embodiment, the work-function layer formation in the first groove 210 and the second groove 220 is finished.Positioned at first
Work-function layer in groove 210 includes the second work-function layer 209；Work-function layer in the second groove 220 includes the first function
Function layer 207a and the second work-function layer 209 positioned at the surface the first work-function layer 207a, first work-function layer
207a covering is located at the etching barrier layer 206 of 220 bottom of the second groove, and second work-function layer 209 covers first function
Etching barrier layer 206 on 220 side wall of function layer 207a and the second groove.In other embodiments of the invention, may be used not
First workfunction material of removal covering 220 side wall of the second groove, so that the first work-function layer in the second groove 220 covers
Second groove, 220 side wall and the etching barrier layer 206 of bottom.
In other embodiments of the invention, NMOS transistor can also be only formed, then the work-function layer only includes institute
The second work-function layer is stated, the material of the work function is TiAl or TiAlC；If only forming PMOS transistor, the work function
Layer includes the first work-function layer and the second work-function layer positioned at first work-function layer surface, and first work-function layer is only
Covering is located at the etching barrier layer of the first bottom portion of groove, and second work-function layer covers first work-function layer and first recessed
Etching barrier layer in groove sidewall, the material of first work-function layer are TiN, the material of the second work-function layer be TiAl or
TiAlC。
Figure 13 is please referred to, forms the grid layer 302 for filling full first groove 210 (please referring to Figure 12) in work-function layer.
In the present embodiment, the grid layer 302 fills full first groove 210 and the second groove 220 (please referring to Figure 12), makees
For the grid of NMOS transistor and PMOS transistor.The material of the grid layer 302 is W or Al.
In the present embodiment, before forming the grid layer 302, soakage layer 301 is formed on work-function layer surface, to improve
Adhesiveness between the grid layer 302 and work-function layer.In the present embodiment, the soakage layer 301 includes TiN layer and is located at
The Ti layer on TiN layer surface.
Cap 203a on the I of first area is only located at 210 bottom of the first groove, to form grid layer so as to improve
Before 302, the first groove 210 is not filled the width of part, thus the grid layer of full first groove 210 of the filling for improving formation
302 filling quality, and the width of the grid layer 302 of formation is improved, and then improve the grid layer 302 to first area I
The control ability of barrier potential difference, improves the performance of transistor between the drain electrode and channel of the transistor of upper formation.
Cap 203a and the first work-function layer 207a on second area II are only located at the bottom of the second groove 220, from
And can be improved before forming grid layer 302, the second groove 220 is not filled the width of part, to improve the filling of formation
The filling quality of the grid layer 302 of full second groove 220, and the width of the grid layer 302 of formation is improved, and then described in raising
Grid layer 302 improves crystal to the control ability of barrier potential difference between the drain electrode and channel of the transistor formed on second area II
The performance of pipe.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (19)
1. a kind of forming method of transistor characterized by comprising
There is provided semiconductor substrate, the semiconductor substrate includes first area, the semiconductor substrate surface have dielectric layer and
The first groove of the dielectric layer is penetrated, first groove is located on first area；
Gate dielectric layer, the cap positioned at gate dielectric layer surface are sequentially formed in the inner wall surface of first groove；
The first mask layer is formed in the nut cap layer surface, the first mask layer covering is located at the part lid of the first bottom portion of groove
Cap layers；
Using first mask layer as exposure mask, removal is located at the cap in the first recess sidewall, exposes the first recess sidewall
The gate dielectric layer surface on surface；
First mask layer is removed, the etching barrier layer for covering the gate dielectric layer and cap is formed；
Work-function layer is formed on the etching barrier layer；
The grid layer for filling full first groove is formed in work-function layer；
The work-function layer includes the first work-function layer and the second work-function layer positioned at first work-function layer surface, described
First work-function layer only covers the etching barrier layer positioned at the first bottom portion of groove, and second work-function layer covers first function
Etching barrier layer on function layer and the first recess sidewall.
2. the forming method of transistor according to claim 1, which is characterized in that the semiconductor substrate further includes second
Region, also has the second groove for penetrating the dielectric layer in the semiconductor substrate, and second groove is located at second area
On；Gate dielectric layer, the nut cap positioned at gate dielectric layer surface are formed in the inner wall surface of first groove and the second groove simultaneously
Layer；First mask layer also covers the part cap positioned at the second bottom portion of groove；It is recessed that the grid layer also fills up full second
Slot.
3. the forming method of transistor according to claim 1 or 2, which is characterized in that the thickness of first mask layer
For
4. the forming method of transistor according to claim 1 or 2, which is characterized in that the material of first mask layer
Including amorphous silicon, silicon oxide or silicon nitride.
5. the forming method of transistor according to claim 2, which is characterized in that the forming method of first mask layer
Include: that the first mask layer is formed in nut cap layer surface using physical gas-phase deposition, is located at the first recess sidewall, second
The thickness of the first mask layer in recess sidewall is less than the first mask material positioned at the first groove and the second bottom portion of groove
The thickness of layer；Removal is located at the first mask layer in the first recess sidewall and the second recess sidewall, is formed recessed positioned at first
First mask layer of trench bottom and the second bottom portion of groove.
6. the forming method of transistor according to claim 5, which is characterized in that using described in wet-etching technology removal
The first mask layer in the first recess sidewall and the second recess sidewall.
7. the forming method of transistor according to claim 5, which is characterized in that form the first exposure mask using sputtering technology
Material layer.
8. the forming method of transistor according to claim 5, which is characterized in that be located at the first recess sidewall, second recessed
The thickness of the first mask layer in groove sidewall and the first mask layer for being located at the first bottom portion of groove, the second bottom portion of groove
The ratio between thickness be less than 2:3.
9. the forming method of transistor according to claim 2, which is characterized in that the work-function layer in the first groove
Including the second work-function layer；Work-function layer in the second groove including the first work-function layer and is located at first work function
Second work-function layer of layer surface, first work-function layer only covers the etching barrier layer positioned at the second bottom portion of groove, described
Second work-function layer covers the etching barrier layer in first work-function layer and the second recess sidewall.
10. the forming method of transistor according to claim 9, which is characterized in that the formation of first work-function layer
Method includes: to form the first workfunction material of covering etching barrier layer；It forms covering and is located at the first groove and the second groove
Second mask layer of the first workfunction material of part of bottom；Using second mask layer as exposure mask, it is recessed that removal is located at first
The first workfunction material of part on slot and the second recess sidewall forms and is located at the first of the first groove and the second bottom portion of groove
Work-function layer；Remove second mask layer；Remove the first work-function layer in the first groove.
11. the forming method of transistor according to claim 1, which is characterized in that the material of the work-function layer is
TiAl or TiAlC.
12. the forming method of transistor according to claim 1, which is characterized in that the formation of first work-function layer
Method includes: to form the first workfunction material for covering entire etching barrier layer；It forms covering and is located at the first bottom portion of groove
Second mask layer of the first work-function layer of part；Using second mask layer as exposure mask, removal is located in the first recess sidewall
The first workfunction material of part forms the first work-function layer for being located at the first bottom portion of groove；Remove second mask layer.
13. the forming method of transistor according to claim 12, which is characterized in that the formation side of second mask layer
Method includes: to form the second mask layer in the first work function material layer surface using physical gas-phase deposition, is located at first
The thickness of the second mask layer in recess sidewall is less than the thickness of the first mask layer positioned at the second bottom portion of groove；It goes
Except the second mask layer being located in the first recess sidewall, the first work function material of part for being located at the first bottom portion of groove is formed
Second mask layer of layer surface.
14. the forming method of transistor according to claim 12, which is characterized in that second mask layer with a thickness of
15. the forming method of transistor according to claim 13, which is characterized in that remove institute using wet-etching technology
Rheme is in the second mask layer in the first recess sidewall.
16. the forming method of transistor according to claim 13, which is characterized in that in the first recess sidewall
The thickness of two mask layers is less than 2:3 with the ratio between the thickness of the second mask layer for being located at the first bottom portion of groove.
17. the forming method of transistor according to claim 12, which is characterized in that the material packet of second mask layer
Include amorphous silicon, silicon oxide or silicon nitride.
18. the forming method of transistor according to claim 1, which is characterized in that the material of first work-function layer
For TiN, the material of second work-function layer is TiAl or TiAlC.
19. the forming method of transistor according to claim 1, which is characterized in that further include: in work-function layer surface shape
Grid layer is formed after soakage layer, then in the infiltration layer surface.
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| CN104253029A (en) * | 2013-06-26 | 2014-12-31 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistors |
| CN104425575A (en) * | 2013-09-03 | 2015-03-18 | 联华电子股份有限公司 | Metal gate structure and manufacturing method thereof |
| CN104617046A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | CMOS transistor forming method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104253029A (en) * | 2013-06-26 | 2014-12-31 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistors |
| CN104425575A (en) * | 2013-09-03 | 2015-03-18 | 联华电子股份有限公司 | Metal gate structure and manufacturing method thereof |
| CN104617046A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | CMOS transistor forming method |
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