CN105244276A - FinFET (field effect transistor), manufacturing method of FinFET and electronic device - Google Patents
FinFET (field effect transistor), manufacturing method of FinFET and electronic device Download PDFInfo
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- CN105244276A CN105244276A CN201410260429.4A CN201410260429A CN105244276A CN 105244276 A CN105244276 A CN 105244276A CN 201410260429 A CN201410260429 A CN 201410260429A CN 105244276 A CN105244276 A CN 105244276A
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Abstract
The invention provides a FinFET (field effect transistor), a manufacturing method of the FinFET and an electronic device. The method comprises the steps of providing a semiconductor substrate, and forming a fin on the semiconductor substrate; forming a pseudo-gate structure comprising a sacrificial gate dielectric layer and a sacrificial gate material layer which are sequentially stacked at two sides and the top of the fin; depositing an interlayer dielectric layer so as to cover the pseudo-gate structure, the fin and the semiconductor substrate; grinding the interlayer dielectric layer until the top of the pseudo-gate structure is exposed; removing the sacrificial gate material layer in the pseudo-gate structure; and implementing dry etching, surface treatment and wet etching in a joint mode to remove the sacrificial gate dielectric layer in the pseudo-gate structure. According to the invention, the control precision for removing of the sacrificial gate dielectric layer can be effectively enhanced, and surface loss of the fin is avoided.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of FinFET and manufacture method, electronic installation.
Background technology
Along with the development of semiconductor technology, the raising of performance of integrated circuits is mainly realized with the speed improving it by the size constantly reducing integrated circuit (IC)-components.At present, because in pursuit high device density, high-performance and low cost, semi-conductor industry has advanced to nanometer technology process node, the preparation of semiconductor device is subject to the restriction of various physics limit.
Along with constantly reducing of cmos device size, the challenge from manufacture and design aspect has impelled three dimensional design as the development of FinFET (FinFET).Relative to existing planar transistor, FinFET is the advanced semiconductor device for 22nm and following process node, it can effective scaled the caused short-channel effect being difficult to overcome of control device, effectively can also improve the density of the transistor array formed on substrate, simultaneously, gate loop in FinFET is arranged around fin, and therefore can control electrostatic effect from three faces, the performance in electrostatic control is also more outstanding.
Prior art adopts following processing step to form the fin of FinFET usually: first, silicon substrate forms buried oxide layer to make silicon-on-insulator (SOI) structure; Then, on insulator silicon structure forms silicon layer, its constituent material can be monocrystalline silicon or polysilicon; Then, graphical silicon layer, and etch described through patterned silicon layer, to form fin.Next, formed in the both sides of fin and top and comprise stacked gate dielectric and the grid structure of gate material layers from bottom to top, and form germanium silicon stressor layers at the two ends of fin.
If subsequent implementation high k dielectric layer-metal gate process, then need first to remove grid structure, prior art adopts an etch process to implement described removal.For there is the FinFET of 22nm and following process node, the very thin thickness of the gate dielectric in grid structure, implement an etch process (comprising the dry etching and wet etching implemented successively) very poor for the control precision of the removal of gate dielectric, cause the removal homogeneity being positioned at the both sides of different fin and the gate dielectric at top poor, and then cause the loss on fin surface.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides the manufacture method of a kind of FinFET, comprising: Semiconductor substrate is provided, be formed with fin on the semiconductor substrate; The dummy gate structure comprising sacrificial gate dielectric layer and the sacrificial gate material layer stacked gradually is formed in the both sides of described fin and top; Interlevel dielectric deposition, to cover described dummy gate structure, described fin and described Semiconductor substrate; Grinding interlayer dielectric layer, until expose the top of described dummy gate structure; Remove the sacrificial gate material layer in described dummy gate structure; Joint Implementation dry etching, surface treatment and wet etching remove the sacrificial gate dielectric layer in described dummy gate structure.
In one example, the Joint Implementation order of described dry etching, surface treatment and wet etching is: described dry etching → described surface treatment → described dry etching → described surface treatment → described wet etching, described dry etching is SiCoNi etching, described surface-treated cleaning fluid is the deionized water being dissolved with ozone, and the corrosive liquid of described wet etching is hydrofluoric acid.
In one example, a small amount of fluorine is contained in the etching gas that described SiCoNi etches.
In one example, another dry etching is adopted to remove described sacrificial gate material layer.
In one example, before depositing described interlayer dielectric layer after forming described dummy gate structure, be also included in the step described fin that exposes described dummy gate structure both sides being formed germanium silicon stressor layers.
In one example, selective epitaxial growth process is adopted to form described germanium silicon stressor layers.
In one example, after removing described sacrificial gate dielectric layer, also comprise the steps: to form high k dielectric layer, to cover described fin; Form metal gates, cover described high k dielectric layer and described interlayer dielectric layer; Perform cmp until expose the top of described interlayer dielectric layer.
In one example, described metal gates comprise stack gradually workfunction setting metal layer, barrier layer and metal gate material layer.
In one embodiment, the present invention also provides a kind of FinFET adopting said method to manufacture.
In one embodiment, the present invention also provides a kind of electronic installation, and described electronic installation comprises described FinFET.
According to the present invention, effectively can strengthen the control precision of the removal to described sacrificial gate dielectric layer, avoid the loss on described fin surface.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 F for according to an exemplary embodiment of the present one the vertical view of device that obtains respectively of the step implemented successively of method;
Fig. 2 A-Fig. 2 F is the schematic cross sectional view of the device obtained along the trend of grid corresponding respectively to Figure 1A-Fig. 1 F;
Fig. 3 is the flow chart of step implemented successively of method of according to an exemplary embodiment of the present.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain FinFET and manufacture method, the electronic installation of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment one]
With reference to Figure 1A-Fig. 1 F and Fig. 2 A-Fig. 2 F, the schematic cross sectional view of the device obtained along the trend of grid of the vertical view of the device that the step that the method that illustrated therein is according to an exemplary embodiment of the present is implemented successively obtains respectively and correspondence.
First, as shown in Figure 1A and Fig. 2 A, provide Semiconductor substrate 100, the constituent material of Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon etc. doped with impurity.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate 100 selects monocrystalline silicon.
Next, fin 102 is formed on a semiconductor substrate 100.In order to simplify, a fin is only shown in legend, and those skilled in the art can know, and need on a semiconductor substrate 100 to form multiple fin, and the width of described fin is all identical, or described fin is divided into multiple fins group with different in width.Exemplarily, in the present embodiment, the step forming fin 102 is as follows: first deposit buried oxide layer 101 and silicon layer successively on a semiconductor substrate 100, described deposition can be low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), physical vapour deposition (PVD) (PVD), one in ald (ALD) and molecular beam epitaxy (MBE), the material of buried oxide layer 101 can be Si oxide, the material of silicon layer can be monocrystalline silicon, its surface orientation is <110>, <100> or other crystal orientation, in order to form the matrix of fin 102, graphical described silicon layer is to form fin 102 again, its step comprises: on described silicon layer, form the photoresist layer with the pattern of fin 102, with described photoresist layer for mask, etch described silicon layer, to form fin 102, remove described photoresist layer by cineration technics.
It should be noted that, following step also can be adopted to form fin 102: form the photoresist layer with the pattern of fin 102 on a semiconductor substrate 100; With described photoresist layer for mask, etching semiconductor substrate 100, to form fin 102, removes described photoresist layer by cineration technics.If a kind of mode forms fin 102 after adopting, then before the following dummy gate structure of formation, the gap be increased between fin 102 is needed to form the step of isolation structure.The processing step forming described isolation structure is had the knack of by those skilled in the art, is no longer repeated at this.
Then, as shown in fig. ib and fig. 2b, form in the both sides of fin 102 and top the dummy gate structure comprising sacrificial gate dielectric layer 104a and the sacrificial gate material layer 104b stacked gradually.Exemplarily, in the present embodiment, the material of sacrificial gate dielectric layer 104a is silica, and the material of sacrificial gate material layer 104b is polysilicon.The method forming described dummy gate structure is well known in the art, is no longer repeated at this.
Next, alternatively, the fin 102 exposed in described dummy gate structure both sides forms germanium silicon stressor layers 105.Exemplarily, in the present embodiment, adopt selective epitaxial growth process to form germanium silicon stressor layers 105, described selective epitaxial growth process can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).
Then, as shown in figures 1 c and 2 c, interlevel dielectric deposition 106, covers described dummy gate structure, germanium silicon stressor layers 105, fin 102 and buried oxide layer 101.Exemplarily, in the present embodiment, the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), physical vapour deposition (PVD) (PVD), ald (ALD) and molecular beam epitaxy (MBE) is deposited as described in.Then, cmp is implemented until expose the top of described dummy gate structure.
Then, remove described dummy gate structure, leave gate groove.Exemplarily, in the present embodiment, remove described dummy gate structure to comprise the following steps: first adopt the first dry etching to remove sacrificial gate material layer 104b, its technological parameter comprises: the flow of etching gas HBr is 30-300sccm, pressure is 5-30mTorr, power is 200-1800W, wherein mTorr represents milli millimetres of mercury, sccm represents cc/min, due to the narrower in width of fin 102, highly very high, therefore, as shown in Fig. 1 D and Fig. 2 D, after implementing the first dry etching, the coating substances 104b ' jointly formed by remaining sacrificial gate material layer 104b and etch byproducts can be remained in the both sides of fin 102 and top, it should be noted that, dotted line in Fig. 1 D is two boundary lines that fin 102 projects in buried oxide layer 101, and, the thickness of described coating substances 104b ' is inhomogenous, the part being positioned at the both sides of fin 102 is usually thicker, for another example shown in Fig. 1 E and Fig. 2 E, Joint Implementation second dry etching, surface treatment and wet etching remove described coating substances 104b ' and sacrificial gate dielectric layer 104a, second dry etching, the enforcement order of surface treatment and wet etching is: the second dry etching → surface treatment → the second dry etching → surface treatment → wet etching, enforcement first time the second dry etching is to remove described coating substances 104b ', implement first time surface treatment with the Substance Transformation do not removed by first time the second dry etching for oxide, implement second time the second dry etching to remove described oxide and sacrificial gate dielectric layer 104a, implement second time surface treatment to remove residue and the impurity of aforementioned etching, implement the residual fraction of the sacrificial gate dielectric layer 104a that wet etching is not removed with second time second dry etching removing the both sides and top that are positioned at the larger fin of characteristic size 102, wherein, twice second dry etchings implemented all can adopt SiCoNi to etch, and containing a small amount of fluorine in the etching gas of described SiCoNi etching, the percentage of usual fluoro-gas in etching gas is no more than 10%, the cleaning fluid of twice surface clean implemented all can adopt the deionized water being dissolved with ozone, the corrosive liquid of the wet etching implemented can adopt hydrofluoric acid.
Then, as shown in Fig. 1 F and Fig. 2 F, in gate groove, high k dielectric layer 107 is formed, to cover buried oxide layer 101 and fin 102.
Next, metal gates 108 is formed, to cover high k dielectric layer 107 and interlayer dielectric layer 106.Then, cmp is performed until expose the top of interlayer dielectric layer 106.
In one example, the k value (dielectric constant) of high k dielectric layer 107 is generally more than 3.9, its constituent material comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc., particularly preferably is hafnium oxide, zirconia or aluminium oxide.In one example, metal gates 108 comprise stack gradually workfunction setting metal layer, barrier layer and metal gate material layer, wherein, workfunction setting metal layer comprises one or more layers metal or metallic compound, comprise titanium, tantalum, aluminium, zirconium, hafnium, ruthenium, palladium, platinum, tungsten and alloy thereof, also comprise the carbide of above-mentioned metallic element, nitride etc.; The material on barrier layer comprises tantalum nitride or titanium nitride, and the material of metal gate material layer comprises tungsten or aluminium.It should be noted that, cover layer can also be formed between high k dielectric layer 107 and workfunction setting metal layer, its constituent material comprises titanium nitride or tantalum nitride, and forming tectal effect is stop the metal material in workfunction setting metal layer to the diffusion of high k dielectric layer; Can also form soakage layer between barrier layer and metal gate material layer, its constituent material comprises titanium or titanium-aluminium alloy, and the effect forming soakage layer improves the interfacial characteristics between barrier layer and metal gate material layer, in order to simplify, omitted in diagram.In one example, adopt chemical vapor deposition method to form high k dielectric layer 107, adopt atom layer deposition process or physical gas-phase deposition to form metal gates 108.
So far, the processing step that the method completing according to an exemplary embodiment of the present is implemented.According to the present invention, effectively can strengthen the control precision of the removal to sacrificial gate dielectric layer 104a, avoid the loss on fin 102 surface.
With reference to Fig. 3, the flow chart of the step that the method that illustrated therein is according to an exemplary embodiment of the present is implemented successively, for schematically illustrating the flow process of manufacturing process.
In step 301, provide Semiconductor substrate, be formed with fin on a semiconductor substrate;
In step 302, form in the both sides of fin and top the dummy gate structure comprising sacrificial gate dielectric layer and the sacrificial gate material layer stacked gradually;
In step 303, interlevel dielectric deposition, to cover dummy gate structure, fin and Semiconductor substrate;
In step 304, grinding interlayer dielectric layer, until expose the top of dummy gate structure;
In step 305, the sacrificial gate material layer in dummy gate structure is removed;
Within step 306, Joint Implementation dry etching, surface treatment and wet etching remove the sacrificial gate dielectric layer in dummy gate structure.
[exemplary embodiment two]
Next, the making of whole FinFET can be completed by subsequent technique, conventional FinFET front end fabrication process can be implemented:
In an exemplary embodiment, first, form another interlayer dielectric layer, cover interlayer dielectric layer 106 and metal gates 108; Then, the contact hole being communicated with the top of metal gates 108 and the top of germanium silicon stressor layers 105 is formed in above-mentioned interlayer dielectric layer, by described contact hole, form self-aligned silicide at the top of the top of the metal gates 108 exposed and germanium silicon stressor layers 105; The contact plug of the interconnecting metal layer that filling metal (being generally tungsten) forms connection enforcement back end fabrication and formed in described contact hole and described self-aligned silicide.
Next, conventional FinFET back end fabrication can be implemented, comprising: the formation of multiple interconnecting metal layer, usually adopt dual damascene process; The formation of metal pad, for implementing wire bonding during device package.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, the FinFET that it method comprising according to an exemplary embodiment of the present two manufactures.Described electronic installation can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.Described electronic installation, owing to employing described semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method of FinFET, comprising:
Semiconductor substrate is provided, is formed with fin on the semiconductor substrate;
The dummy gate structure comprising sacrificial gate dielectric layer and the sacrificial gate material layer stacked gradually is formed in the both sides of described fin and top;
Interlevel dielectric deposition, to cover described dummy gate structure, described fin and described Semiconductor substrate;
Grinding interlayer dielectric layer, until expose the top of described dummy gate structure;
Remove the sacrificial gate material layer in described dummy gate structure;
Joint Implementation dry etching, surface treatment and wet etching remove the sacrificial gate dielectric layer in described dummy gate structure.
2. method according to claim 1, it is characterized in that, the Joint Implementation order of described dry etching, surface treatment and wet etching is: described dry etching → described surface treatment → described dry etching → described surface treatment → described wet etching, described dry etching is SiCoNi etching, described surface-treated cleaning fluid is the deionized water being dissolved with ozone, and the corrosive liquid of described wet etching is hydrofluoric acid.
3. method according to claim 2, is characterized in that, containing a small amount of fluorine in the etching gas of described SiCoNi etching.
4. method according to claim 1, is characterized in that, adopts another dry etching to remove described sacrificial gate material layer.
5. method according to claim 1, is characterized in that, before depositing described interlayer dielectric layer, is also included in the step described fin that exposes described dummy gate structure both sides being formed germanium silicon stressor layers after forming described dummy gate structure.
6. method according to claim 5, is characterized in that, adopts selective epitaxial growth process to form described germanium silicon stressor layers.
7. method according to claim 1, is characterized in that, after removing described sacrificial gate dielectric layer, also comprises the steps: to form high k dielectric layer, to cover described fin; Form metal gates, cover described high k dielectric layer and described interlayer dielectric layer; Perform cmp until expose the top of described interlayer dielectric layer.
8. method according to claim 7, is characterized in that, described metal gates comprise stack gradually workfunction setting metal layer, barrier layer and metal gate material layer.
9. the FinFET of the method manufacture adopting one of claim 1-8 described.
10. an electronic installation, described electronic installation comprises FinFET according to claim 9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107644809A (en) * | 2017-08-17 | 2018-01-30 | 北京工业职业技术学院 | The grid preparation method and grid of fin formula field effect transistor |
| CN113539827A (en) * | 2020-04-20 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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| JP2002533931A (en) * | 1998-12-18 | 2002-10-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for manufacturing semiconductor device |
| CN1726582A (en) * | 2002-12-20 | 2006-01-25 | 皇家飞利浦电子股份有限公司 | Method of manufacturing a semiconductor device and semiconductor device obtained with such a method |
| US20140145242A1 (en) * | 2012-11-29 | 2014-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-Last FinFET and Methods of Forming Same |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| EP1043348A1 (en) * | 1997-12-26 | 2000-10-11 | Daikin Industries, Ltd. | Flexible heat-resistant material for office automation equipment and coating material |
| JP2002533931A (en) * | 1998-12-18 | 2002-10-08 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Method for manufacturing semiconductor device |
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| US20140145242A1 (en) * | 2012-11-29 | 2014-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fin-Last FinFET and Methods of Forming Same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107644809A (en) * | 2017-08-17 | 2018-01-30 | 北京工业职业技术学院 | The grid preparation method and grid of fin formula field effect transistor |
| CN113539827A (en) * | 2020-04-20 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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