CN103871886B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN103871886B CN103871886B CN201210552997.2A CN201210552997A CN103871886B CN 103871886 B CN103871886 B CN 103871886B CN 201210552997 A CN201210552997 A CN 201210552997A CN 103871886 B CN103871886 B CN 103871886B
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- 238000000034 method Methods 0.000 title claims abstract description 61
- 239000010410 layer Substances 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000011229 interlayer Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229920000642 polymer Polymers 0.000 claims abstract description 34
- 239000003518 caustics Substances 0.000 claims abstract description 22
- 238000001312 dry etching Methods 0.000 claims abstract description 20
- 238000001039 wet etching Methods 0.000 claims abstract description 16
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 8
- 239000000463 material Substances 0.000 claims description 40
- 239000004020 conductor Substances 0.000 claims description 24
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 238000006116 polymerization reaction Methods 0.000 claims 1
- 239000002904 solvent Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000003628 erosive effect Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical group CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 4
- 238000005260 corrosion Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000002253 acid Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920005573 silicon-containing polymer Polymers 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000003682 fluorination reaction Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000004480 active ingredient Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 150000005846 sugar alcohols Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of transistor, including：Semiconductor substrate is provided, on a semiconductor substrate the source region formed with dummy grid, in the Semiconductor substrate of dummy grid both sides and drain region；Interlayer dielectric layer is formed on a semiconductor substrate, covers the source region and drain region；After forming interlayer dielectric layer, the dummy grid is removed using dry etching, forms pseudo- gate groove；After dry etching removes the dummy grid, the caused polymer during the dry etching is removed using wet etching, wherein, the pH value of the corrosive agent used is more than 6 and is less than 7 or is less than 8 more than 7, and fluoride is included in the corrosive agent；After wet etching removes the polymer, grid is formed in the pseudo- gate groove.Using the corrosive agent of the present invention, the polymer of pseudo- gate trench sidewall and bottom removes substantially, and grid also can form accessible contact with gate dielectric layer with the grid of pseudo- gate trench sidewall.The forming method of transistor of the present invention improves the performance of transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of forming method of transistor.
Background technology
In the prior art, " rear grid（Gate last) " technique is to form a main technique of metal gates.This skill
The characteristics of art, is re-formed after the operation of drain source ion implanting and the completion of subsequent high-temperature annealing step are carried out to silicon chip
Metal gates.
In the rear grid technique of prior art, the method that forms transistor generally includes：First, on a semiconductor substrate
Form dummy grid；Afterwards, source region and drain region are formed in the Semiconductor substrate of dummy grid both sides；Then, on a semiconductor substrate
Interlayer dielectric layer is formed, source region is covered and drain region, upper surface and the dummy grid upper surface of interlayer dielectric layer maintains an equal level；And then, carve
Etching off removes dummy grid, and pseudo- gate groove is formed in interlayer dielectric layer；Finally, metal is filled in the pseudo- gate groove, forms gold
Belong to grid.
But the performance of the semiconductor devices made using the rear grid technique of prior art is bad.
The more knowledge on rear grid technique, it refer to disclosed in 4 days Mays in 2011, Publication No. CN102044421A
Chinese patent literature.
The content of the invention
The present invention solves the problems, such as be prior art rear grid technique formation transistor performance it is bad.
To solve the above problems, the present invention provides a kind of forming method of new transistor, including：
Semiconductor substrate is provided, on a semiconductor substrate the Semiconductor substrate formed with dummy grid, positioned at dummy grid both sides
In source region and drain region；
Interlayer dielectric layer is formed on a semiconductor substrate, covers the source region and drain region；
After forming interlayer dielectric layer, the dummy grid is removed using dry etching, forms pseudo- gate groove；
After dry etching removes the dummy grid, removed using wet etching caused during the dry etching
Polymer, wherein, the pH value of the corrosive agent used is more than 6 and is less than 7 or is less than 8 more than 7, and fluorination is included in the corrosive agent
Thing；
After wet etching removes the polymer, grid is formed in the pseudo- gate groove.
Optionally, the fluoride includes：Hydrofluoric acid or hydrogen PVF.
Optionally, the corrosive agent also includes hydrogen peroxide, the concentration of hydrogen peroxide（Quality）Less than 1%.
Optionally, the dummy grid is removed using dry etching, the etching gas used are O2。
Optionally, the dummy grid is removed using dry etching, the etching gas used also include NF3, HBr or CF4In
It is one or more.
Optionally, dummy grid, source region, the method in drain region are formed, including：
Dummy grid material is deposited, covers Semiconductor substrate；
The graphical dummy grid material, forms the dummy grid；
Ion implanting is carried out in the Semiconductor substrate of the dummy grid both sides, forms source region and drain region.
Optionally, the material of the dummy grid includes polysilicon, silicon nitride or amorphous carbon.
Optionally, the method for forming grid, including：
Deposit conductive material, covering interlayer dielectric layer, the pseudo- gate groove of filling；
Remove and be higher by the conductive material of the interlayer dielectric layer, the conductive material in the remaining pseudo- gate groove, as grid
Pole.
Optionally, in addition to the high-K dielectric layer being located under the grid is formed, as gate dielectric layer；
The method for forming the high-K dielectric layer, including：
After wet etching removes the polymer, before depositing the conductive material, high-K dielectric layer material, covering are deposited
Interlayer dielectric layer, the pseudo- gate groove of filling；
When removal is higher by the conductive material of the interlayer dielectric layer, the high-K dielectric layer material for being higher by interlayer dielectric layer is also removed
Expect, the high-K dielectric layer in the remaining pseudo- gate groove, as gate dielectric layer.
Optionally, the method for the conductive material for being higher by the interlayer dielectric layer is removed, including chemically-mechanicapolish polishes or returns and carve.
Optionally, the material of the grid includes：Al、Cu、Ag、Au、Pt、Ni、Ti、TiN、TaN、Ta、TaC、TaSiN、
W, WN, WSi one or more.
Optionally, in addition to：Formed before source region and drain region, formed around the dummy grid on a semiconductor substrate
Side wall.
Optionally, the method for the side wall formed around dummy grid, including：Deposit spacer material, covering semiconductor lining
Bottom, dummy grid；
The spacer material is etched using carving technology is returned, side wall is formed around dummy grid.
Optionally, the material of the interlayer dielectric layer is silica.
Optionally, the transistor is N-type transistor or P-type transistor.
Compared with prior art, the present invention has advantages below：
The present invention is directed to rear grid technique, removes the process of dummy grid, there is provided a kind of new wet etching method, to remove
Dry etching dummy grid process forms and is attached to the side wall of pseudo- gate groove and the polymer of bottom.In the present invention, wet method is rotten
The pH value of the corrosive agent of erosion process is more than 6 and is less than 7 or is less than 8 more than 7, and fluoride is included in the corrosive agent.The corrosive agent
With weak acid or alkalescent, during polymer is removed, the side wall of pseudo- gate groove or bottom will not be caused to damage, also not
Adjacent semiconductor bodies can be caused to damage.Fluoride in corrosive agent is to remove the oxide and silicon-containing polymer in polymer
Active ingredient.Using the corrosive agent of the present invention, the polymer in pseudo- gate groove removes substantially, and pseudo- gate groove has flatter
Side wall.So, grid is formed in pseudo- gate groove, the grid has more neat surface at pseudo- gate trench sidewall, stable
And the performance of transistor is improved, lift the reliability of transistor.In addition, the polymer of pseudo- gate groove bottom also removes substantially,
Conductive material also can form accessible contact with the gate dielectric layer of pseudo- gate groove bottom with the grid of pseudo- gate trench sidewall.
The influence of transistor performance may further be improved that is the forming method of transistor of the invention avoids polymer
The performance of transistor.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the forming method of the transistor of the specific embodiment of the invention；
Fig. 2~Fig. 5 is the cross-sectional view of the forming method of the transistor of the specific embodiment of the invention.
Embodiment
The problem of inventor exists for the rear grid technique of prior art, is studied, and is found：Using dry etching
Remove in dummy grid, polymer can be generated, be attached to bottom and the side wall of pseudo- gate groove.Such as in dry etch process, generally
Oxygen is passed through to etching reaction intracavitary, partial oxidation can react with other materials of polysilicon or etching reaction intracavitary, raw
Into oxide, oxide can be considered a kind of composition of polymer.It is existing although subsequently removing polymer using wet etching
It is 1-METHYLPYRROLIDONE to have corrosive agent usually used in technology（NMP, N-methyl-2-pyrrolidone）Solvent or EKC
Solvent (a kind of alkaline solution provided by EKC Technology Inc of Du Pont).Nmp solvent is respectively provided with strong basicity with EKC solvents, is removing
While polymer, also adjacent semiconductor bodies are caused with damage and the erosion removal polymer of nmp solvent or EKC solvents
Ability it is bad, most of polymer can not remove.This can produce following problem：Contain residual in the side wall of pseudo- gate groove
Polymer so that the side wall of pseudo- gate groove is uneven, and the side wall of pseudo- gate groove has surface projections point.So, in puppet
The metal gates formed in gate groove have rough surface at pseudo- gate trench sidewall, and then have influence on the property of transistor
Energy.Directly contacted with grid moreover, not removing clean polymer, also influence whether the performance of transistor.
Inventor obtains a kind of forming method of new semiconductor devices in view of the above-mentioned problems, by creative work.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.Many details are elaborated in the following description in order to fully understand this hair
It is bright.But the present invention can be to be much different from other modes described here to implement, those skilled in the art can be not
Similar popularization is done in the case of running counter to intension of the present invention, therefore the present invention is not limited by following public specific embodiment.
Reference picture 2, and reference picture 1 is combined, perform step S11, there is provided Semiconductor substrate 100, on a semiconductor substrate 100
Source region 102 and drain region 103 formed with dummy grid 101, in the Semiconductor substrate 100 of the both sides of dummy grid 101.
In a particular embodiment, the material of the Semiconductor substrate 100 can be monocrystalline silicon, monocrystalline germanium or single-crystal silicon Germanium；
It can also be silicon-on-insulator（SOI）；Or other materials can also be included, such as the compounds of group of GaAs etc. III-V.
It is used for phase formed with device architecture (not shown), such as the isolation structure such as isolation trench structure in the Semiconductor substrate 100
Isolation between adjacent transistor.
In a particular embodiment, it is also formed with titanium nitride layer in the Semiconductor substrate 100 under dummy grid 101（Do not show
Go out）, when titanium nitride layer can form grid in follow-up pseudo- gate groove, the conductive material of barrier grid spreads into channel region.
In a particular embodiment, the method for forming dummy grid 101, including：Dummy grid material is deposited on a semiconductor substrate 100
Material, select chemical vapor deposition method, dummy grid material covering Semiconductor substrate 100；Graphical dummy grid material, forms pseudo- grid
Pole 101.The graphical dummy grid material is：Patterned photoresist layer is formed in dummy grid material layer, is defined to be formed
Dummy grid position；Using the patterned photoresist layer as mask, dummy grid material is etched, is stopped to Semiconductor substrate 100
Only, if formed with titanium nitride layer under dummy grid 101, stop to titanium nitride layer；Remove patterned photoresist layer.
In a particular embodiment, material selection polysilicon, silicon nitride or the amorphous carbon of the dummy grid 101.In this reality
Apply in example, select polysilicon, and the elaboration of subsequent schedule is carried out by taking polysilicon as an example.
In a particular embodiment, it is also formed with side wall around dummy grid 101（It is not shown）.Forming dummy grid 101
Afterwards, before the source region being located in Semiconductor substrate 100 and drain region is formed, side wall is formed around dummy grid 101.Form side
The method of wall, including：Deposit spacer material, covering Semiconductor substrate, dummy grid；The side wall material is etched using carving technology is returned
Material, forms side wall around dummy grid.Generally, the material selective oxidation silicon of side wall.
In a particular embodiment, source region 102, the method in drain region 103 are formed, including：Mask is formed on dummy grid 101
Layer；Using the mask layer as mask, ion implanting is carried out, source region 102 and drain region 103 are formed in Semiconductor substrate 100.Its
In, the ionic type of injection, determined according to the type of transistor to be formed.If transistor to be formed is nmos pass transistor,
Then the type of ion implanting is p-type ion, such as boron；If transistor to be formed is PMOS transistor, the type of ion implanting
For N-type ion.Concrete technology condition is well known to those skilled in the art, and will not be repeated here.
Reference picture 3, and Fig. 1 is combined, step S12 is performed, forms interlayer dielectric layer 104, covering on a semiconductor substrate 100
Source region 102 and drain region 103.
In a particular embodiment, the material of interlayer dielectric layer 104 generally selects silica, also has other can selection certainly
Material, can be selected according to being actually needed.The step of forming interlayer dielectric layer 104, usually first deposits, then planarized
Processing, such as chemically mechanical polishing or time quarter, so that the upper surface of interlayer dielectric layer 104 and the upper surface of dummy grid 101 maintain an equal level.
Reference picture 4, and Fig. 1 is combined, step S13 is performed, after forming interlayer dielectric layer 104, institute is removed using dry etching
Dummy grid 101 is stated, forms pseudo- gate groove 105.
In a particular embodiment, using dry etch process, the pseudo- gate groove with compared with vertical sidewall can be obtained.Dry
In method etching process, etching product can be produced, the etching product can be deposited on side wall and the bottom of pseudo- gate groove 105.
In dry etching, generally O is passed through to etching reaction intracavitary2, can play a part of removing dummy grid 101, and interlayer can be supplemented
The oxygen that dielectric layer 104 is lost in etching process.But while above-mentioned positive effect is produced, the oxygen that is passed through also with
Some reactant reactions generate oxide, and the oxide is with foregoing etching product together as being formed during dry etching
Polymer.Except being passed through O to etching reaction intracavitary2Outside, also include being passed through NF into reaction chamber during dry etching4、
HBr or CF4Deng the one or more of gas, generally mixed gas a variety of in them.These polymer must be carved in dry method
Removed after erosion, otherwise can influence the performance of transistor.
Therefore, after dry etching removes dummy grid 101, with continued reference to Fig. 4, and Fig. 1 is combined, performs step S14, used
Wet etching removes the caused polymer during dry etching, wherein, the pH value of the corrosive agent used be more than 6 be less than 7 or
It is less than 8 more than 7, and fluoride is included in corrosive agent.
In a particular embodiment, the pH value of the corrosive agent is more than 6 and is less than 7 or more than 7 less than 8, has weak acid or weak base
Property, side wall and the bottom of pseudo- gate groove will not be damaged, and will not also damage adjacent semiconductor devices.Moreover, fluorination therein
Thing can remove most silicon-containing polymer and oxide, and silicon-containing polymer is also the main component in polymer.Therefore,
The corrosive agent that the present invention uses can not only remove the polymer for remaining in pseudo- gate trench sidewall and bottom, can also avoid to phase
Adjacent semiconductor devices causes to damage.In specific implementation, the fluoride includes the composition such as hydrofluoric acid or hydrogen PVF.
In a particular embodiment, the corrosive agent may also include hydrogen peroxide（H2O2）, wherein H2O2Concentration（Quality）Scope
For less than 1%, hydrogen peroxide can effectively strengthen the effect for removing oxide.1% is less than to the selection of hydrogen peroxide concentration scope, can be subtracted
Small hydrogen peroxide produces the possibility of damage to adjacent semiconductor bodies.
In the present embodiment, the ATMI TK12-6 solvents of the corrosive agent selection ATMI.Inc productions.Wherein, ATMI
The pH value of TK12-6 solvents is more than 6 and is less than 7, has faintly acid, contains concentration in the solvent（Quality）For 0.6% hydrogen peroxide, fluorine
The compositions such as compound.In specific production, the duration about 2min of wet etching is carried out, corrosion rate is aboutAnd corrosive agent of the prior art, such as EKC solvents, pH value is about 9, has strong basicity and higher concentration
Hydrogen peroxide, other semiconductor devices can be damaged, and EKC corrosion rate is larger, can be in erosion removal polymer process, volume
Outer other semiconductor devices of corrosion.The corrosion rate of ATMI TK12-6 solvents is smaller, avoids in adjacent semiconductor bodies
Metal or other materials cause extra erosion.
In the present embodiment, wet etching eliminates the polymer for remaining in the pseudo- side wall of gate groove 105 and bottom so that pseudo-
The side wall and bottom flat of gate groove 105, it also avoid negative influence of the polymer to transistor performance.
Reference picture 4 and Fig. 5, and Fig. 1 is combined, step S15 is performed, after wet etching removes polymer, in pseudo- gate groove
Grid 106 is formed in 105.Grid 106 can be metal gates, or the grid of other conductive materials.
In a particular embodiment, the method for forming grid 106, including：Conductive material is deposited, covers interlayer dielectric layer 104
With the pseudo- gate groove 105 of filling；Remove and be higher by the conductive material of interlayer dielectric layer 104, the conduction material in remaining pseudo- gate groove 105
Material.In the present embodiment, chemically mechanical polishing can be used or be etched back to technique, remove the conduction for being higher by interlayer dielectric layer 104
Material, including remove the conductive material of the upper surface of interlayer dielectric layer 104 and remove the conductive material more than pseudo- gate groove 105.
In specific production, high-K dielectric layer is also formed between grid 106 and Semiconductor substrate 100, as gate medium
Layer（It is not shown）.Forming the method for high-K dielectric layer includes：After wet etching removes polymer, before depositing the conductive material,
High-K dielectric layer material is deposited, interlayer dielectric layer is covered and fills pseudo- gate groove；Then, remove and be higher by the interlayer dielectric layer
During conductive material, the high-K dielectric layer for being higher by interlayer dielectric layer is also got rid of, it is so, remaining in the side wall of pseudo- gate groove and bottom
High-K dielectric layer, as gate dielectric layer.Certainly, in a particular embodiment, high K can also be first formed in pseudo- gate groove bottom to be situated between
Matter layer, after high-K dielectric layer is formed, then form grid in the high-K dielectric layer in pseudo- gate groove.The grid of high-K dielectric layer
Dielectric layer coordinates grid 106, such as metal gates, can obtain the transistor of better performance.The type of transistor can be that N-type is brilliant
Body pipe or P-type transistor.
In a particular embodiment, conductive material include Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN,
W, WN, WSi one or more.In specific production, the specific of conductive material is determined according to the type of transistor to be formed
Scope.
Because after step S14 is performed, wet etching eliminates the residual polyalcohol in pseudo- gate groove 105, the grid of formation
Pole 106 has flatter surface at pseudo- gate groove 105, improves the performance of transistor.In addition, the pseudo- side wall of gate groove 105
Removed substantially with the polymer of bottom, conductive material can with the gate dielectric layer of the pseudo- bottom of gate groove 105 is accessible contacts.Also
To say, avoiding polymer to the influence of transistor performance, may improve the performance of transistor, lifting can transistor it is reliable
Property.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, any this area
Technical staff without departing from the spirit and scope of the present invention, may be by the methods and technical content of the disclosure above to this hair
Bright technical scheme makes possible variation and modification, therefore, every content without departing from technical solution of the present invention, according to the present invention
Any simple modifications, equivalents, and modifications made to above example of technical spirit, belong to technical solution of the present invention
Protection domain.
Claims (12)
- A kind of 1. forming method of transistor, it is characterised in that including：Semiconductor substrate is provided, on a semiconductor substrate formed with dummy grid, in the Semiconductor substrate of dummy grid both sides Source region and drain region, the material of the dummy grid is polysilicon, silicon nitride or amorphous carbon；Interlayer dielectric layer is formed on a semiconductor substrate, covers the source region and drain region；After forming interlayer dielectric layer, the dummy grid is removed using dry etching, forms pseudo- gate groove, the etching gas used are O2；After dry etching removes the dummy grid, the caused polymerization during the dry etching is removed using wet etching Thing, wherein, the pH value of the corrosive agent used is more than 6 and is less than 7 or is less than 8 more than 7, and fluoride, institute are included in the corrosive agent Stating fluoride includes containing PVF；After wet etching removes the polymer, grid is formed in the pseudo- gate groove.
- 2. forming method as claimed in claim 1, it is characterised in that the corrosive agent also includes hydrogen peroxide, the matter of hydrogen peroxide Measure concentration and be less than 1%.
- 3. forming method as claimed in claim 2, it is characterised in that remove the dummy grid using dry etching, use Etching gas also include NF3, HBr or CF4In one or more.
- 4. forming method as claimed in claim 1, it is characterised in that dummy grid, source region, the method in drain region are formed, including：Dummy grid material is deposited, covers Semiconductor substrate；The graphical dummy grid material, forms the dummy grid；Ion implanting is carried out in the Semiconductor substrate of the dummy grid both sides, forms source region and drain region.
- 5. forming method as claimed in claim 1, it is characterised in that the method for forming grid, including：Deposit conductive material, covering interlayer dielectric layer, the pseudo- gate groove of filling；Remove and be higher by the conductive material of the interlayer dielectric layer, the conductive material in the remaining pseudo- gate groove, as grid.
- 6. forming method as claimed in claim 5, it is characterised in that also include forming the high K dielectric being located under the grid Layer, as gate dielectric layer；The method for forming the high-K dielectric layer, including：After wet etching removes the polymer, before depositing the conductive material, high-K dielectric layer material is deposited, covers interlayer Dielectric layer, the pseudo- gate groove of filling；When removal is higher by the conductive material of the interlayer dielectric layer, the high-K dielectric layer material for being higher by interlayer dielectric layer is also removed, is remained High-K dielectric layer in the remaining pseudo- gate groove, as gate dielectric layer.
- 7. forming method as claimed in claim 5, it is characterised in that removal is higher by the conductive material of the interlayer dielectric layer Method, including chemically-mechanicapolish polish or return and carve.
- 8. forming method as claimed in claim 1, it is characterised in that the material of the grid includes：Al、Cu、Ag、Au、Pt、 Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi one or more.
- 9. forming method as claimed in claim 1, it is characterised in that also include：Source region and leakage are formed on a semiconductor substrate Before area, the side wall being located at around the dummy grid is formed.
- 10. forming method as claimed in claim 9, it is characterised in that the method for the side wall formed around dummy grid, bag Include：Deposit spacer material, covering Semiconductor substrate, dummy grid；The spacer material is etched using carving technology is returned, side wall is formed around dummy grid.
- 11. forming method as claimed in claim 1, it is characterised in that the material of the interlayer dielectric layer is silica.
- 12. forming method as claimed in claim 1, it is characterised in that the transistor is N-type transistor or P-type transistor.
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| US5556833A (en) * | 1993-12-10 | 1996-09-17 | Armor All Products Corporation | Wheel cleaning composition containing acid fluoride salts |
| US5939336A (en) * | 1998-08-21 | 1999-08-17 | Micron Technology, Inc. | Aqueous solutions of ammonium fluoride in propylene glycol and their use in the removal of etch residues from silicon substrates |
| CN1918698A (en) * | 2004-02-09 | 2007-02-21 | 三菱化学株式会社 | Cleaning liquid for substrate for semiconductor device and cleaning method |
| CN102214576A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102479692A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Gate forming method |
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| JP4945900B2 (en) * | 2005-01-06 | 2012-06-06 | ソニー株式会社 | Insulated gate field effect transistor and manufacturing method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5556833A (en) * | 1993-12-10 | 1996-09-17 | Armor All Products Corporation | Wheel cleaning composition containing acid fluoride salts |
| US5939336A (en) * | 1998-08-21 | 1999-08-17 | Micron Technology, Inc. | Aqueous solutions of ammonium fluoride in propylene glycol and their use in the removal of etch residues from silicon substrates |
| CN1918698A (en) * | 2004-02-09 | 2007-02-21 | 三菱化学株式会社 | Cleaning liquid for substrate for semiconductor device and cleaning method |
| CN102214576A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102479692A (en) * | 2010-11-30 | 2012-05-30 | 中芯国际集成电路制造(北京)有限公司 | Gate forming method |
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