CN105826245B - The forming method of semiconductor structure - Google Patents
The forming method of semiconductor structure Download PDFInfo
- Publication number
- CN105826245B CN105826245B CN201510011973.XA CN201510011973A CN105826245B CN 105826245 B CN105826245 B CN 105826245B CN 201510011973 A CN201510011973 A CN 201510011973A CN 105826245 B CN105826245 B CN 105826245B
- Authority
- CN
- China
- Prior art keywords
- etching
- layer
- contact hole
- dielectric layer
- semiconductor structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
A kind of forming method of semiconductor structure, comprising: the substrate with bottom metal layer is provided；Form the dielectric layer for being covered in the substrate surface and underlying metal layer surface；Graph layer is formed in the dielectric layer surface, there is opening in the graph layer；Using the graph layer as exposure mask, the dielectric layer is etched along the opening, until exposing underlying metal layer surface, contact hole is formed in the dielectric layer, there is fluoropolymer impurity in the contact hole；Remove the graph layer；The first etching is carried out to the contact hole using hydrogen plasma to post-process, and removes the fluorine ion in the fluoropolymer impurity；After carrying out the first etching post-processing, wet clean process is carried out to the contact hole；Form the conductive layer for filling the full contact hole.The present invention avoids the fluorine ion in Q-time from causing to damage to dielectric layer and bottom metal layer, improves the production yield of semiconductor structure, improves chip quantum of output.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, in particular to a kind of forming method of semiconductor structure.
Background technique
As integrated circuit develops to super large-scale integration, the current densities of IC interior are increasing, institute
The number of elements for including is also more and more.In semiconductor integrated circuit, metal-oxide semiconductor (MOS) (MOS, Metal Oxide
Semiconductor) one of element wherein mostly important when transistor.
Existing MOS transistor technique is to form gate structure on a semiconductor substrate, in gate structure opposite sides
Source region and drain region are formed in semiconductor substrate；Then contact hole (Contact is formed on gate structure, source region and drain region again
Via), metal is filled in contact hole form metal plug.However, between metal plug and gate structure, source region and drain region
Conduction property is to be improved and contact resistance is bigger, in order to improve metal plug and gate structure, source region and the contact in drain region
Resistance, it will usually metal silicide (Silicide) is formed on source region, drain region and gate structure surface, for example, nickle silicide, with
Reduce the contact resistance between metal plug and gate structure, source region and drain region.
However, the yield and chip quantum of output of prior art semiconductor structure are still to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of forming method of semiconductor structure, carry out wet clean process it
Before, content of fluoride ion in contact hole interpolymer impurity is effectively reduced, so that etching be made to be formed at contact hole to wet-cleaning
Waiting time (the Q time from Contact Etch Step to Wet Clean Step) between reason is elongated, keeps away
Exempt to cause unnecessary damage in waiting time interpolymer impurity and bottom metal layer or dielectric layer, improve chip quantum of output with
And semiconductor.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: providing has bottom gold
Belong to the substrate of layer；Form the dielectric layer for being covered in the substrate surface and underlying metal layer surface；In the dielectric layer surface
Graph layer is formed, there is opening in the graph layer；Using the graph layer as exposure mask, the dielectric layer is etched along the opening,
Until exposing underlying metal layer surface, contact hole is formed in the dielectric layer, there is fluoropolymer in the contact hole
Impurity；Remove the graph layer；The first etching is carried out to the contact hole using hydrogen plasma to post-process, and is removed described fluorine-containing
Fluorine ion in polymeric impurities；After carrying out the first etching post-processing, the contact hole is carried out at wet-cleaning
Reason；Form the conductive layer for filling the full contact hole.
Optionally, the treatment temperature of the first etching post-processing is 85 degrees Celsius to 110 degrees Celsius.
Optionally, the technological parameter of the first etching post-processing are as follows: H is passed through into reaction chamber2, H2Flow is
10sccm to 500sccm, the bias power provided are 100 watts to 1000 watts, and reaction chamber pressure is 50 millitorrs to 200 millitorrs.
Optionally, first etching is carried out using hydrogen plasma and nitrogen plasma to post-process；Described first
In over etching last handling process, H is passed through into reaction chamber2And N2, wherein N2Flow is 100sccm to 1000sccm, H2Flow
For 10sccm to 500sccm.
Optionally, the etching technics carries out in same reaction chamber with the first etching post-processing.
Optionally, also contain carbon ion in the fluoropolymer impurity；After carrying out the first over etching processing, carry out
Before wet clean process, further comprises the steps of: and the second etching post-processing, removal are carried out to the contact hole using nitrogen plasma
Carbon ion in fluoropolymer impurity.
Optionally, the treatment temperature of the second etching post-processing is 85 degrees Celsius to 110 degrees Celsius；At second quarter
It loses in last handling process, N is passed through into reaction chamber2。
Optionally, etching stop layer is formed between the bottom metal layer and dielectric layer；Form the work of the contact hole
Skill step includes: to etch the dielectric layer along opening using main etching technique, until etching stopping layer surface is exposed, described
Initial contact hole is formed in dielectric layer；Remove the graph layer；Then the first over etching technique is used, etching is located at initial contact
Segment thickness etching stop layer below hole；Then the second over etching technique is used, the quarter below etching initial contact hole is continued
Stop-layer is lost, until exposing underlying metal layer surface, forms the contact hole.
Optionally, it after removing the graph layer, before carrying out the second over etching technique, further comprises the steps of: using nitrogen
Plasma carries out third etching post-processing to the initial contact hole sidewall surfaces and etching stopping layer surface.
Optionally, the treatment temperature of the third etching post-processing is 85 degrees Celsius to 110 degrees Celsius；After third etching
In treatment process, N is passed through into reaction chamber2。
Optionally, the main etching technique includes: the dielectric layer for first using first step main etching technique etched portions thickness,
Then proceed to the dielectric layer using second step main etching technique etching remainder thickness；Wherein, first step main etching technique is carved
The angle lost between the dielectric layer side wall and substrate surface formed is 88 ° to 95 °, and second step main etching technique etches Jie to be formed
Angle between matter layer side wall and substrate surface is 65 ° to 85 °.
Optionally, the technological parameter of the first step main etching technique are as follows: source power is 1500 watts to 3000 watts, biases function
Rate is 2000 watts to 4000 watts, and the ratio of source power and bias power is 1 to 2, and reaction chamber pressure is 5 millitorrs to 40 millitorrs,
Etching gas includes CF4, Ar is also passed through into etching cavity, Ar flow is 500sccm to 1500sccm；The second step main quarter
The technological parameter of etching technique are as follows: source power is 500 watts to 2000 watts, and bias power is 500 watts to 2000 watts, source power and biasing
The ratio of power is 0.5 to 2, and reaction chamber pressure is 5 millitorrs to 40 millitorrs, and etching gas includes CF4、CHF3Or CH2F2, also
He is passed through into etching cavity, He flow is 100sccm to 1000sccm.
Optionally, the material of the etching stop layer is silicon nitride, carbon dope silicon nitride, silicon carbide or silicon oxynitride.
Optionally, it before the wet clean process, further comprises the steps of: and contact hole progress Ar plasma is banged
It hits, reduces the dielectric layer surface contact angle of contact hole side-walls.
Optionally, before the Ar plasma bombardment, the dielectric layer surface contact angles of contact hole side-walls be 90 ° extremely
110°；After the Ar plasma bombardment, the dielectric layer surface contact angle of contact hole side-walls is 65 ° to 75 °.
Optionally, the technological parameter of the Ar plasma bombardment are as follows: treatment temperature is 85 degrees Celsius to 110 degrees Celsius,
Ar flow is 100sccm to 1000sccm, and reaction chamber pressure is 100 millitorrs to 500 millitorrs, and providing bias power is 100 watts
To 1000 watts.
Optionally, the cleaning liquid of the wet clean process is hydrofluoric acid or hydrogen peroxide solution.
Optionally, the material of the conductive layer is TiN, Ti, Ta, TaN, WN, Cu, Al or W；The graph layer includes photoetching
Glue-line；The material of the bottom metal layer is copper, tungsten, aluminium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or metal silicide.
Optionally, the top surface of the bottom metal layer is higher than substrate surface；Alternatively, table at the top of the bottom metal layer
Face is lower than substrate surface；Alternatively, being flushed at the top of the bottom metal layer with substrate surface.
Compared with prior art, technical solution of the present invention has the advantage that
In the technical solution of the forming method of semiconductor structure provided by the invention, the contact hole that is formed after etch media layer
It is interior that there is fluoropolymer impurity, the first etching is carried out to contact hole using hydrogen plasma and is post-processed, fluoropolymer is removed
Fluorine ion in impurity avoids etching to reduce the probability that fluorine ion and dielectric layer and bottom metal layer react
It is formed in contact hole to the waiting time between wet clean process, dielectric layer and bottom metal layer are by the fluorine in fluoropolymer
Ion etching improves the production yield of semiconductor structure so that dielectric layer and bottom metal layer be made to keep good performance, improves
Chip quantum of output.Simultaneously as the fluorine ion in fluoropolymer impurity is removed, so as to form contact hole clear to wet process for etching
The waiting time washed between processing can be long, to increase the cycle window in semiconductor structure production technology.
Further, if the treatment temperature of the first etching post-processing is too low, the ability of hydrogen plasma is weaker, and fluorine ion is difficult
To shake off from fluoropolymer impurity；If the treatment temperature of the first etching post-processing is excessively high, it is easy to make intrabasement device
At damage.The treatment temperature of the first etching post-processing is 85 degrees Celsius to 110 degrees Celsius in the present invention, both to remove fluorine-containing poly-
The fluorine ion ability closed in object impurity is stronger, and is avoided that and causes adverse effect to intrabasement device.
Further, in the first etching last handling process, H is passed through into reaction chamber2And N2, the N2It is used to form nitrogen
Plasma, while removing the fluorine ion in fluoropolymer impurity, additionally it is possible to remove the carbon in fluoropolymer impurity
Ion.
Further, main etching technique includes first step main etching technique and second step main etching technique in the present invention,
In, it is 88 ° to 95 °, i.e. top that first step main etching technique, which etches the angle between the dielectric layer side wall to be formed and substrate surface,
Divide the side wall in initial contact hole close to right angle, so that the characteristic size of contact hole is easy to control, improves the contact electricity of conductive layer
The uniformity of resistance；The angle between dielectric layer side wall and substrate surface that second step main etching technique is formed is 65 ° to 85 °, i.e.,
Inverted trapezoidal is presented in lower part initial contact hole section shape, so that filling the technology difficulty of conductive layer in the tap contact hole of lower part
It is low, it avoids contact with and forms gap between hole bottom and conductive layer.
Further, the present invention carries out Ar plasma bombardment to contact hole, makes to connect before carrying out wet clean process
The dielectric layer surface contact angle of contact hole side-walls reduces, and the dielectric layer surface hydrophily of contact hole side-walls becomes strong, so that
The ability that wet clean process cleans contact hole is stronger, provides good interface basis to form conductive layer.
Detailed description of the invention
Fig. 1 to Figure 13 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process.
Specific embodiment
It can be seen from background technology that the yield for the semiconductor structure that the prior art is formed is to be improved, and chip quantum of output is low.
In one embodiment, the formation process of semiconductor structure is the following steps are included: step S1, offer substrate, described
There is bottom metal layer in substrate, form dielectric layer in the substrate surface；Step S2, figure is formed in the dielectric layer surface
Layer, the graph layer is interior to have the opening for exposing dielectric layer surface；Step S3, it using the graph layer as exposure mask, is carved along opening
Erosion dielectric layer forms contact hole in the dielectric layer up to exposing underlying metal layer surface；Step S4, to the contact hole
Carry out wet clean process；Step S5, the conductive layer for filling the full contact hole is formed.
In the above method, generally use dry etch process etch media layer to form contact hole；In dry etch process
In the process, the material generation chemical reaction of the material of etching gas and dielectric layer, graph layer forms byproduct of reaction.It is a part of anti-
Answer by-product that can be carried over etching cavity with the flowing of etching gas, effect of some byproduct of reaction in gravity
Under, it is attached to side wall and the bottom of contact hole.Due to usually containing the materials such as photoresist, antireflection material, photoetching in graph layer
Glue material, antireflection material and etching gas, which react, can generate polymer, therefore the bottom and side wall surface of contact hole is attached
Have polymeric impurities.
When being attached with polymeric impurities in contact hole, the technique hardly possible for forming the conductive layer for filling full contact hole will be increased
Degree, and be easy to cause between conductive layer and bottom metal layer and lead to the problem of open circuit.For this purpose, being needed before forming conductive layer
Wet clean process is carried out to contact hole.
However, the production yield of semiconductor structure is still lower although having carried out wet clean process to contact hole, partly lead
Body reliability of structure and electric property are still poor.
Further study show that forming contact hole to wet clean process from etching during production process of semiconductor
Waiting time (Q-Time, the time from Contact Etch Step to Wet Clean Step) usually relatively
It is long；Within the waiting time, polymeric impurities can react with dielectric layer, and dielectric layer performance is caused to change；Also,
The polymeric impurities can also react with bottom metal layer, and bottom metal layer surfacing is caused to be converted into insulating materials,
Such as bottom metal layer surfacing be nickle silicide when, polymeric impurities are chemically reacted with nickle silicide, lead to underlying metal
Layer surface material becomes insulating materials.Correspondingly, will occur after forming conductive layer, between conductive layer and bottom metal layer disconnected
Road problem seriously affects the production yield of semiconductor structure, and the quantum of output (WPH, Wafer Per Hour) of chip will be by tight
Ghost image is rung.When Q-time is longer, the damage that dielectric layer and bottom metal layer are subject to is bigger, and the yield of semiconductor structure is poorer,
The reliability and electric property of semiconductor structure are poorer.
Also, after polymeric impurities and bottom metal layer chemically react, wet clean process removes contact hole
The ability of interior impurity will be weaker.
Further study show that containing fluorine ion in polymeric impurities, the fluorine ion is to lead to dielectric layer and bottom gold
Belong to the main reason for layer is damaged.If the content of fluoride ion in polymeric impurities can be reduced before wet clean process, that
The probability that corresponding dielectric layer and bottom metal layer chemically react will be lower, accordingly Q-time inner medium layer with
Bottom metal layer material property be able to maintain it is constant, to improve the production yield of semiconductor structure.
If the fluorine ion in the polymeric impurities can be removed before carrying out wet clean process, then in Q-
The probability that time inner medium layer and bottom metal layer and fluorine ion chemically react will greatly reduce even zero, to make
Dielectric layer and bottom metal layer keep good performance, and improve the ability of wet clean process removal polymeric impurities.
For this purpose, the present invention provides a kind of forming method of offer semiconductor structure, etch media layer is formed in dielectric layer
Contact hole, the contact hole is interior to have fluoropolymer impurity；First etching is carried out to the contact hole using hydrogen plasma
Post-processing, removes the fluorine ion in the fluoropolymer impurity；After carrying out the first etching post-processing, connect to described
Contact hole carries out wet clean process；Form the conductive layer for filling the full contact hole.The present invention is before wet clean process, removal
Fluorine ion in fluoropolymer impurity avoids to prevent fluorine ion from chemically reacting with dielectric layer and bottom metal layer
Dielectric layer and bottom metal layer are damaged, to improve the production yield of semiconductor structure, increase chip quantum of output.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 1 to Figure 13 is the schematic diagram of the section structure that the semiconductor structure that one embodiment of the invention provides forms process.
Referring to FIG. 1, providing the substrate 100 with bottom metal layer 101.
In the present embodiment, bottom metal layer 101 is located in substrate 100, and 101 top surface of bottom metal layer is higher than substrate
100 surfaces.
In a specific embodiment, gate medium can also be formed between the substrate 100 and bottom metal layer 101
Layer, corresponding bottom metal layer 101 are a part of gate structure, and the side wall of bottom metal layer 101 can also be formed with side wall,
The material of the side wall is silica, silicon nitride or silicon oxynitride.
The bottom metal layer 101 includes first part's metal layer and positioned at second of first part's layer on surface of metal
Point metal layer, wherein the material of first part's metal layer is copper, tungsten, aluminium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride, second
The material of partial metal layers is metal silicide, for example, NiSi or CoSi.In other embodiments, the bottom metal layer 101
It may be single layer structure.
The material of the substrate 100 is silicon, germanium, SiGe, silicon carbide, GaAs or gallium indium；The substrate 100 may be used also
Think the germanium substrate on the silicon substrate or insulator on insulator；Semiconductor devices, example can also be formed in the substrate 100
Such as, PMOS transistor, NMOS transistor, CMOS transistor, resistor, inductor or capacitor etc..
The material of substrate 100 described in the present embodiment is silicon.
In the present embodiment, bottom metal layer 101 is located at 100 surface of substrate, and 101 top surface of bottom metal layer is higher than
100 surface of substrate.In other embodiments, bottom metal layer can also be located in substrate, the top surface of bottom metal layer
It can be flushed lower than the top table of substrate surface or bottom metal layer with substrate surface.The material packet of the bottom metal layer
Copper, tungsten, aluminium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or metal silicide are included, for example, NiSi.
Referring to FIG. 2, forming the dielectric layer 102 for being covered in 100 surface of substrate and 101 surface of bottom metal layer.
The material of the dielectric layer 102 is silica, silicon nitride, silicon oxynitride, low k dielectric materials or ultra-low k dielectric material
Material.The dielectric layer 102 is formed using chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition or spin coating proceeding.
Wherein, low k dielectric materials refer to that the dielectric material that relative dielectric constant is lower than 3.9, ultra-low k dielectric material refer to opposite Jie
Electric constant is lower than 2.5 dielectric material.
When the material of the dielectric layer 102 is low k dielectric materials or ultra-low k dielectric material, the material of dielectric layer 102 is
SiOH, SiCOH, FSG (silica of fluorine doped), BSG (silica of boron-doping), PSG (silica of p-doped), BPSG
(silica of boron-doping phosphorus), hydrogenation silsesquioxane (HSQ, (HSiO1.5)n) or methyl silsesquioxane (MSQ,
(CH3SiO1.5)n)。
The material of dielectric layer 102 described in the present embodiment is silica, is given an account of using chemical vapor deposition process formation
Matter layer 102.Also, after metallization medium layer 102, can also carry out grinding technics makes 102 top surface height one of dielectric layer
It causes.
The present embodiment is formed with etching stop layer 103 between bottom metal layer 101 and dielectric layer 102, that is, is forming institute
Before stating dielectric layer 102, etching stop layer 103, the etching are formed on 101 surface of bottom metal layer and 100 surface of substrate
The material of stop-layer 103 is different from the material of dielectric layer 102.
During subsequent etching processes, etching technics is much smaller than to dielectric layer 102 rate of etching stop layer 103
Etch rate avoids etching technics from causing over etching to bottom metal layer 101 to play the role of etching stopping.The etching
The material of stop-layer 103 is silicon nitride, carbon dope silicon nitride, silicon carbide or silicon oxynitride.
The material of etching stop layer 103 is silicon nitride in the present embodiment.
Referring to FIG. 3, forming graph layer on 102 surface of dielectric layer, there is opening 107 in the graph layer.
The positions and dimensions of the opening 107 correspond to the positions and dimensions for the contact hole being subsequently formed, subsequent along opening
107 etch media layers 102, form contact hole in dielectric layer 102.
In the present embodiment, the graph layer includes: amorphous carbon layer (A-C, the Amorphous positioned at 102 surface of dielectric layer
Carbon) 104, inorganic bottom antireflective coatings (DARC, the Dielectric Anti- positioned at 104 surface of amorphous carbon layer
Reflective Coating) 105 and the photoresist layer 106 positioned at 105 surface of inorganic bottom antireflective coatings, wherein it opens
Mouth 107 is through the photoresist layer 106 and exposes 105 surface of reflection coating provided.
In other embodiments, graph layer also may include: positioned at organic distribution layer of dielectric layer surface, positioned at organic point
The bottom antireflective coating (BARC, Bottom Anti-reflective Coating) of cloth layer surface and anti-positioned at bottom
The photoresist layer of reflective coated surface, wherein opening is through the photoresist layer and exposes bottom antireflective coating surface.Or
Person, graph layer include: the photoetching positioned at the bottom antireflective coating of dielectric layer surface and positioned at bottom antireflective coating surface
Glue-line, wherein opening is through the photoresist layer and exposes anti-reflective coating layer surface.
The graph layer can also only include photoresist layer, and opening is through photoresist layer and exposes dielectric layer surface.
Referring to FIG. 4, using the graph layer as exposure mask, using main etching technique along the 107 etching medium of opening
Layer 102 forms initial contact hole 108 until exposing 103 surface of etching stop layer in the dielectric layer 102, described initial
There is fluoropolymer impurity in contact hole 108.
Main etching technique is divided into the progress of two steps in the present embodiment, first using first step main etching technique etched portions thickness
Dielectric layer 102, the first step main etching technique use higher source power and bias power, and to the etching of dielectric layer 102
Rate is larger, the content of reaction byproduct of 102 sidewall surfaces of dielectric layer aggregation after etching is reduced, so that first step main etching work
It is 88 ° to 95 ° that skill, which etches between 100 surface of 102 side wall of dielectric layer to be formed and substrate, for example, 90 °, 92 °.
Then using the dielectric layer 102 of second step main etching technique etching remainder thickness, the second step main etching
The source power and bias power of technique are less than the source power and bias power of first step main etching technique, and second step main quarter
Etching technique is less than first step main etching technique to the etch rate of dielectric layer 102 to the etch rate of dielectric layer 102, and second step
Main etching technique is to dielectric layer 102 and to the etching selection ratio with higher of etching stop layer 103, the second step main etching work
The angle that skill etches between 100 surface of 102 side wall of dielectric layer to be formed and substrate is 65 ° to 85 °, for example, 70 °, 75 °, 80 °.
As a specific embodiment, the dielectric layer 102 of first step main etching technique etching with a thickness of second step main quarter
The 1/3 to 2/3 of the thickness of the dielectric layer 102 of etching technique etching.
In the present embodiment, initial contact hole 108 is formd after etch media layer 102, subsequent etch again is located at initial contact
After the etching stop layer 103 of 108 lower section of hole, that is, form the contact hole for exposing 101 surface of bottom metal layer.Using above-mentioned main quarter
Etching technique enables to lower part initial contact 108 side wall of hole to have the biggish angle being inclined outwardly, so that subsequent to contact
The filling capacity of hole bottom is stronger.Also, since upper part initial contact 108 side wall of hole is almost vertical with plane, so that contact
The available good control of the critical size in hole has preferable contact resistance (Rc) uniformity.
As in a specific embodiment, the technological parameter of the first main etching technique are as follows: source power be 1500 watts extremely
3000 watts, bias power is 2000 watts to 4000 watts, and the ratio of source power and bias power is 1 to 2, and reaction chamber pressure is 5
For millitorr to 40 millitorrs, etching gas includes CF4, Ar is also passed through into etching cavity, Ar flow is 500sccm to 1500sccm.
The technological parameter of the second main etching technique are as follows: source power is 500 watts to 2000 watts, and bias power is 500 watts
To 2000 watts, the ratio of source power and bias power is 0.5 to 2, and reaction chamber pressure is 5 millitorrs to 40 millitorrs, etching gas
Including CF4、CHF3Or CH2F2, He is also passed through into etching cavity, He flow is 100sccm to 1000sccm.
In the main etching technical process, etching gas occurs chemical reaction formation with 102 material of dielectric layer and reacts secondary
Product, etching gas can also occur chemical reaction with figure layer material and form byproduct of reaction, have in the byproduct of reaction
Fluoropolymer impurity, since the quality of fluoropolymer impurity is relatively large, the gravity being subject to is larger, therefore fluorine-containing
Polymeric impurities are difficult to flow and be discharged out of etching cavity；The fluoropolymer impurity under the effect of gravity, is attached to initial
The bottom and side wall surface of contact hole 108.
Simultaneously as containing C element in the present embodiment dielectric layer 102, graph layer and etching gas, therefore described
Also it will contain carbon ion in fluoropolymer impurity.
In other embodiments, a step main etching technique can also be used, etch media layer is until expose etching stopping
Layer surface.
Also, to expose the etching stopping position that 103 surface of etching stop layer is main etching technics, In in the present embodiment
Etching stop layer 103 is not caused to etch in main etching technical process.In other embodiments, main etching technique can also be to portion
The etching stop layer of thickness is divided to perform etching.
Referring to FIG. 5, removing the graph layer.
In the present embodiment, using cineration technics removal photoresist layer 106, inorganic bottom antireflective coatings 105 and amorphous
Carbon-coating 104.
In ash process, it is also possible to will increase the fluorine-containing polymeric impurities being attached in initial contact hole 108
Amount.
Referring to FIG. 6, etching is located at the quarter of the segment thickness of 108 lower section of initial contact hole using the first over etching technique
Lose stop-layer 103.
In the present embodiment, over etching technique is divided into the progress of two steps, first using the first over etching technique etched portions thickness
Then etching stop layer 103 uses the second over etching technique more smaller than the first over etching technique etch rate, avoids to bottom
Metal layer 101 causes over etching.
The etching gas of the first over etching technique includes CO, and He can also be passed through into etching cavity.Described
In one over etching technical process, initially contacting the carbon ion content in hole 108 in fluoropolymer impurity will also increase.
Referring to FIG. 7, using nitrogen plasma, to 208 sidewall surfaces of initial contact hole and etching stop layer 103
Surface carries out third etching post-processing.
It is etched and is post-processed using third, the part carbon ion in fluoropolymer impurity can be removed, formed after reduction
Carbon ion content in fluoropolymer in contact hole, so that C ion in C-F key in fluoropolymer is from fluoropolymer
Middle disengaging, to increase the content of fluoride ion to dissociate in fluoropolymer, so that removing in subsequent first etching post-processing
The ability of fluorine ion is stronger in fluoropolymer.
If the treatment temperature of third etching post-processing is too low, the energy of nitrogen plasma is excessively weak, removes the energy of carbon ion
Power is poor；If the treatment temperature of third etching post-processing is excessively high, it is easy to cause adverse effect to the device in substrate 100.
For this purpose, the treatment temperature of the etching post-processing of third described in the present embodiment is 85 degrees Celsius to 110 degrees Celsius；
In three etching last handling processes, N is passed through into reaction chamber2。
The third etching post-processing and first step main etching technique, second step main etching technique and first step over etching
Technique carries out in same reaction chamber.
Referring to FIG. 8, continuing the etching below etching initial contact hole 108 (with reference to Fig. 7) using the second over etching technique
Stop-layer 103 forms the contact hole 109 until exposing 101 surface of bottom metal layer.
Contact hole 109 described in the present embodiment runs through dielectric layer 102 and etching stop layer 103, and 109 bottom of contact hole
Expose 101 surface of bottom metal layer.
The second over etching technique is to the etch rate of etching stop layer 103 less than the first over etching technique to etch-stop
The only etch rate of layer 103, to avoid causing over etching to bottom metal layer 101.
Due to containing fluoropolymer impurity in initial contact hole 108, accordingly after etching the etching stop layer 103
To also have fluoropolymer impurity in the contact hole 109 of formation.
Referring to FIG. 9, the first etching post-processing 200 is carried out to the contact hole 109 using hydrogen plasma, described in removal
Fluorine ion in fluoropolymer impurity.
The processing of hydrogen plasma can reduce the content of fluoride ion in fluorine-containing polymeric impurities, or even can go completely
Except the fluorine ion in fluorine-containing polymeric impurities.This is because:
The bond energy of H-F key is about 569kJ/mol, and the bond energy of C-F key is about 552kJ/mol, and the bond energy of H-F key is greater than C-F
The bond energy of key illustrates that compared with C-F key, F ion and the H-F key that H ions binding is formed are more stable, therefore hydrogen plasma
The fluorine ion in fluorine-containing polymeric impurities can be made to shake off the constraint of C-F key, the combination for re-starting chemical bond forms H-F key
And it is detached from from fluorine-containing polymeric impurities.
Also, the content of fluoride ion of free state increases in fluoropolymer impurity when aforementioned third etching post-processing, makes
The ability for obtaining fluorine ion in 200 removal fluoropolymer impurity of the first etching post-processing is stronger.
If the treatment temperature of the first etching post-processing 200 is too low, the energy of hydrogen plasma is lower, hydrogen plasma pair
The bombardment of fluoropolymer impurity is weaker, so that fluorine ion is difficult to shaking off from fluoropolymer impurity；If after the first etching
The treatment temperature of processing 200 is excessively high, then is easy to cause to damage to the device in substrate 100.
For this purpose, the treatment temperature of the first etching post-processing 200 is 85 degrees Celsius to 110 degrees Celsius in the present embodiment, such as
It is 90 degrees Celsius, 95 degrees Celsius or 100 degrees Celsius.
The first etching post-processing 200 of the present embodiment uses higher reaction chamber pressure and lower bias power,
So that hydrogen plasma adequately bombards fluoropolymer impurity, the energy of fluorine ion in removal fluoropolymer impurity is improved
Power.As one embodiment, reaction chamber pressure is 100 millitorrs, 150 millitorrs to 180 millitorrs, and bias power is 200 watts, 300
Watt, 500 watts or 700 watts.
In a specific embodiment, the technological parameter of the first etching post-processing 200 are as follows: be passed through into reaction chamber
H2, H2Flow is 10sccm to 500sccm, and the bias power provided is 100 watts to 1000 watts, and source power is 100 watts to 2000
Watt, reaction chamber pressure is 50 millitorrs to 200 millitorrs.
And the bond energy of c h bond is about 444kJ/mol, and the bond energy of H-F key is significantly greater than the bond energy of c h bond, therefore H ion
It is more easier to form stable H-F key in conjunction with F ion, therefore compared with carrying out the first over etching processing 200 before, is carrying out
After first over etching post-processing 200, the content of fluoride ion in fluoropolymer impurity tails off even zero, and fluoropolymer
Carbon ion content in impurity is kept approximately constant.
In order to make the first etching post-processing 200 that can also remove the part carbon ion in fluoropolymer impurity, reduce subsequent
The difficulty of second etching post-processing removal carbon ion, in the present embodiment, carries out institute using hydrogen plasma and nitrogen plasma
State the first etching post-processing 200, wherein hydrogen plasma can remove the fluorine ion in fluoropolymer impurity, nitrogen plasma
Body can remove the carbon ion in fluoropolymer impurity.As a specific embodiment, in the first etching post-processing 200
In the process, H is passed through into reaction chamber2And N2, wherein N2Flow is 100sccm to 1000sccm, H2Flow be 10sccm extremely
500sccm。
Also, since aforementioned etch can have the gas containing oxygen element in the technical process for forming contact hole, so that bottom
Metal layer 101 is oxidized to a certain extent, and the degree of oxidation of bottom metal layer 101 can also be reduced using hydrogen plasma,
So that reduction reaction occurs for the bottom metal layer 101 being oxidized, to further increase the performance of bottom metal layer 101.
Since the present embodiment uses the first over etching processing 200, the fluorine ion in fluoropolymer impurity is eliminated, is made
The content of fluoride ion obtained in the fluoropolymer impurity in contact hole 109 greatly reduces even zero, is subsequently formed accordingly
Contact hole in fluoropolymer impurity in content of fluoride ion also will be seldom, avoid formed contact hole to wet-cleaning at
In Q-time between reason, fluorine ion is chemically reacted with dielectric layer 102, bottom metal layer 101, to make dielectric layer 102
And bottom metal layer 101 keeps good performance.
Impurity in subsequent touch hole 109 is still referred to as fluorine-containing polymeric impurities, with phase before the first over etching processing 200
Even zero is tailed off than, the content of fluoride ion in fluorine-containing polymeric impurities in subsequent touch hole 109.
Referring to FIG. 10, after the etching of carry out first post-processing 200 (referring to Fig. 9), using nitrogen plasma to described
Contact hole 109 carries out the second etching post-processing 300.
Since the first etching post-processing mainly eliminates the fluorine ion in fluoropolymer impurity, and remove fluoropolymer
The ability of carbon ion in impurity is weaker.And if carbon ion content in fluoropolymer is more, subsequent wet cleaning treatment
Difficulty will become larger.
For this purpose, the present embodiment carries out the to contact hole 109 after the etching post-processing of carry out first, using nitrogen plasma
Two etching post-processings 300；Carbon ion quilt during the second etching post-processing 300, in the fluoropolymer impurity
Removal.
In a specific embodiment, by N2It is plasmarized with the nitrogen plasma.If the second etching post-processing 300
Treatment temperature it is too low, then the ability of nitrogen plasma bombardment fluoropolymer impurity is weaker, and nitrogen plasma removal is fluorine-containing poly-
The ability for closing the carbon ion in object impurity is weak；If the treatment temperature that the second etching can handle 300 is excessively high, can be in substrate 100
Device cause adverse effect.
For this purpose, the treatment temperature of the second etching post-processing 300 is 85 degrees Celsius to 110 degrees Celsius in the present embodiment, such as
It is 90 degrees Celsius, 95 degrees Celsius or 100 degrees Celsius.
Figure 11 is please referred to, the first etching post-processing 200 (referring to Fig. 9) and the second etching post-processing 300 are being carried out
After (referring to Figure 10), further comprises the steps of: and Ar plasma bombardment 400 is carried out to the contact hole 109, make 109 side of contact hole
102 surface contact angle of dielectric layer (WCA, Wafer Contact Angle) at wall reduces.
Before the Ar plasma bombardment 400,102 surface contact angle of dielectric layer of 109 side-walls of contact hole is 90 °
To 110 °, for example, 93 °, 95 °, 97.6 °, 100 ° or 105 °；After the Ar plasma bombardment 400,109 side of contact hole
102 surface contact angle of dielectric layer at wall is 65 ° to 75 °, for example, 67 °, 68.4 °, 70 ° or 73 °.
Since 102 surface contact angle of dielectric layer of 109 side-walls of contact hole reduces, so that 109 side-walls medium of contact hole
The hydrophilicity on 102 surface of layer is improved, subsequent when carrying out wet clean process, can be further increased at wet-cleaning
Reason goes deimpurity ability.
In a specific embodiment, the technological parameter of the Ar plasma bombardment 400 are as follows: treatment temperature is 85 Celsius
For degree to 110 degrees Celsius, Ar flow is 100sccm to 1000sccm, and reaction chamber pressure is 100 millitorrs to 500 millitorrs, is provided partially
Setting power is 100 watts to 1000 watts, and source power is 100 watts to 2000 watts.
Figure 12 is please referred to, the first etching post-processing, the second etching post-processing and Ar plasma bombardment are being carried out
Later, wet clean process 500 is carried out to the contact hole 109.
First etching carried out to contact hole 109 post-processed due to aforementioned, eliminate fluorine in fluoropolymer impurity from
Son so that the content of fluoride ion in contact hole 109 becomes smaller even zero, therefore fluorine ion and dielectric layer 102 occur chemical reaction,
The probability that fluorine ion is chemically reacted with bottom metal layer 101 significantly becomes smaller, so that forming contact hole 109 to wet-cleaning
In Q-time between processing 200, dielectric layer 102 and bottom metal layer 101 keep good performance, avoid dielectric layer 102 with
And 101 material property of bottom metal layer changes, to improve the production yield of semiconductor structure, improves chip quantum of output.
Also, since content of fluoride ion becomes smaller even zero in contact hole 109, dielectric layer 102 and bottom metal layer 101
The damage very little being subject to, therefore Q-time can be longer in the present embodiment, and the material of dielectric layer 102 and bottom metal layer 101
Material performance remains to remain unchanged, to increase the cycle window (loop window) of semiconductor structure production technology.
Simultaneously as the aforementioned carbon ion eliminated in fluoropolymer impurity, and 109 side-walls dielectric layer of contact hole
The enhancing of 102 surface hydrophilicities, so that the technology difficulty of wet clean process 500 reduces, is more easier to completely remove contact hole 109
Interior fluoropolymer impurity improves the cleannes of contact hole 109.
In a specific embodiment, the cleaning liquid of the wet clean process 500 is hydrofluoric acid solution or hydrogen peroxide
Solution.
Figure 13 is please referred to, the conductive layer 110 of the full contact hole 109 (referring to Figure 12) of filling is formed.
In a specific embodiment, the processing step for forming the conductive layer 110 includes: to form the full contact of filling
The conductive film in hole 109, the conductive film are also covered in 102 surface of dielectric layer；Removal is higher than the conductive film on 102 surface of dielectric layer,
The conductive layer 110 for filling full contact hole 109 is formed, and 110 top surface of the conductive layer is flushed with 102 surface of dielectric layer.
The conductive layer 110 is single layer structure or laminated construction, the material of the conductive layer 110 is TiN, Ti, Ta, TaN,
WN, Cu, Al or W.
One conductive layer 110 of the present embodiment is for single layer structure, the material of conductive layer 110 is W.
In other embodiments, conductive layer include: positioned at contact hole bottom and side wall surface electrically conductive barrier, with
And positioned at conductive barrier layer surface and the conductor layer of the full contact hole of filling.Wherein, the material of the electrically conductive barrier is
TiN, Ti, Ta, TaN or WN；The material of the conductor layer is Cu, Al or W.
It is functional due to bottom metal layer 101, and the cleannes with higher of contact hole 109, so that is formed leads
The quality of electric layer 110 is high, and conductive layer 110 and the electrical connection properties of bottom metal layer 101 are good, and the production of semiconductor structure is good
Rate is high, improves chip quantum of output.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (17)
1. a kind of forming method of semiconductor structure characterized by comprising
The substrate for having bottom metal layer is provided；
Form the dielectric layer for being covered in the substrate surface and underlying metal layer surface；
Graph layer is formed in the dielectric layer surface, there is opening in the graph layer；
Using the graph layer as exposure mask, the dielectric layer is etched along the opening, until underlying metal layer surface is exposed, in institute
It states and forms contact hole in dielectric layer, there is fluoropolymer impurity in the contact hole；
Remove the graph layer；
The first etching is carried out to the contact hole using hydrogen plasma to post-process, and removes the fluorine in the fluoropolymer impurity
Ion；
After carrying out the first etching post-processing, wet clean process is carried out to the contact hole；
Form the conductive layer for filling the full contact hole；
Etching stop layer is formed between the bottom metal layer and dielectric layer；The processing step for forming the contact hole includes:
The dielectric layer is etched along opening using main etching technique, until etching stopping layer surface is exposed, the shape in the dielectric layer
At initial contact hole；Remove the graph layer；Then the first over etching technique is used, etching is located at the portion below initial contact hole
Divide thickness etching stop layer；Then the second over etching technique is used, continues the etching stop layer below etching initial contact hole, directly
To underlying metal layer surface is exposed, the contact hole is formed；
The main etching technique includes: the dielectric layer for first using first step main etching technique etched portions thickness, then proceedes to adopt
With the dielectric layer of second step main etching technique etching remainder thickness；Wherein, first step main etching technique etches Jie to be formed
Angle between matter layer side wall and substrate surface is 88 ° to 95 °, second step main etching technique etch the dielectric layer side wall to be formed with
Angle between substrate surface is 65 ° to 85 °.
2. the forming method of semiconductor structure according to claim 1, which is characterized in that the first etching post-processing
Treatment temperature is 85 degrees Celsius to 110 degrees Celsius.
3. the forming method of semiconductor structure according to claim 1, which is characterized in that the first etching post-processing
Technological parameter are as follows: H is passed through into reaction chamber2, H2Flow be 10sccm to 500sccm, the bias power provided be 100 watts extremely
1000 watts, reaction chamber pressure is 50 millitorrs to 200 millitorrs.
4. the forming method of semiconductor structure according to claim 1, which is characterized in that use hydrogen plasma and nitrogen
Plasma carries out the first etching post-processing；In the first over etching last handling process, it is passed through into reaction chamber
H2And N2, wherein N2Flow is 100sccm to 1000sccm, H2Flow is 10sccm to 500sccm.
5. the forming method of semiconductor structure according to claim 1, which is characterized in that the etching technics and the first quarter
Erosion post-processing carries out in same reaction chamber.
6. the forming method of semiconductor structure according to claim 1, which is characterized in that in the fluoropolymer impurity
Also contain carbon ion；After carrying out the first over etching processing, before carrying out wet clean process, further comprise the steps of: using nitrogen
Plasma carries out the second etching to the contact hole and post-processes, and removes the carbon ion in fluoropolymer impurity.
7. the forming method of semiconductor structure according to claim 6, which is characterized in that the second etching post-processing
Treatment temperature is 85 degrees Celsius to 110 degrees Celsius；In the second etching last handling process, N is passed through into reaction chamber2。
8. the forming method of semiconductor structure according to claim 1, which is characterized in that remove the graph layer it
Afterwards, it before carrying out the second over etching technique, further comprises the steps of: using nitrogen plasma, to initial contact hole sidewall surfaces
And etching stopping layer surface carries out third etching post-processing.
9. the forming method of semiconductor structure according to claim 8, which is characterized in that the third etching post-processing
Treatment temperature is 85 degrees Celsius to 110 degrees Celsius；In third etching last handling process, N is passed through into reaction chamber2。
10. the forming method of semiconductor structure according to claim 1, which is characterized in that the first step main etching work
The technological parameter of skill are as follows: source power is 1500 watts to 3000 watts, and bias power is 2000 watts to 4000 watts, source power and biasing function
The ratio of rate is 1 to 2, and reaction chamber pressure is 5 millitorrs to 40 millitorrs, and etching gas includes CF4, also it is passed through into etching cavity
Ar, Ar flow are 500sccm to 1500sccm；The technological parameter of the second step main etching technique are as follows: source power be 500 watts extremely
2000 watts, bias power is 500 watts to 2000 watts, and the ratio of source power and bias power is 0.5 to 2, and reaction chamber pressure is 5
For millitorr to 40 millitorrs, etching gas includes CF4、CHF3Or CH2F2, He is also passed through into etching cavity, He flow is 100sccm
To 1000sccm.
11. the forming method of semiconductor structure according to claim 1, which is characterized in that the material of the etching stop layer
Material is silicon nitride, carbon dope silicon nitride, silicon carbide or silicon oxynitride.
12. the forming method of semiconductor structure according to claim 1, which is characterized in that in the wet clean process
Before, it further comprises the steps of: and Ar plasma bombardment is carried out to the contact hole, contact the dielectric layer surface of contact hole side-walls
Angle reduces.
13. the forming method of semiconductor structure according to claim 12, which is characterized in that banged in the Ar plasma
Before hitting, the dielectric layer surface contact angle of contact hole side-walls is 90 ° to 110 °；After the Ar plasma bombardment, connect
The dielectric layer surface contact angle of contact hole side-walls is 65 ° to 75 °.
14. the forming method of semiconductor structure according to claim 12, which is characterized in that the Ar plasma bombardment
Technological parameter are as follows: treatment temperature be 85 degrees Celsius to 110 degrees Celsius, Ar flow be 100sccm to 1000sccm, reaction chamber
Pressure is 100 millitorrs to 500 millitorrs, and providing bias power is 100 watts to 1000 watts.
15. the forming method of semiconductor structure according to claim 1, which is characterized in that the wet clean process
Cleaning liquid is hydrofluoric acid or hydrogen peroxide solution.
16. the forming method of semiconductor structure according to claim 1, which is characterized in that the material of the conductive layer is
TiN, Ti, Ta, TaN, WN, Cu, Al or W；The graph layer includes photoresist layer；The material of the bottom metal layer be copper, tungsten,
Aluminium, titanium, titanium nitride, tantalum, tantalum nitride, tungsten nitride or metal silicide.
17. the forming method of semiconductor structure according to claim 1, which is characterized in that the top of the bottom metal layer
Portion surface is higher than substrate surface；Alternatively, the bottom metal layer top surface is lower than substrate surface；Alternatively, the underlying metal
Layer top is flushed with substrate surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510011973.XA CN105826245B (en) | 2015-01-09 | 2015-01-09 | The forming method of semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510011973.XA CN105826245B (en) | 2015-01-09 | 2015-01-09 | The forming method of semiconductor structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105826245A CN105826245A (en) | 2016-08-03 |
| CN105826245B true CN105826245B (en) | 2019-12-03 |
Family
ID=56514286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510011973.XA Active CN105826245B (en) | 2015-01-09 | 2015-01-09 | The forming method of semiconductor structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105826245B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106847745A (en) * | 2017-03-03 | 2017-06-13 | 京东方科技集团股份有限公司 | The preparation method and low temperature polysilicon base plate of a kind of low temperature polysilicon base plate |
| CN108336024B (en) * | 2018-03-12 | 2020-12-04 | 绵阳京东方光电科技有限公司 | Manufacturing method of thin film transistor, manufacturing method of display substrate and display device |
| CN112447510A (en) * | 2019-08-30 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor structure and transistor |
| CN115939030B (en) * | 2022-12-27 | 2024-02-20 | 上海铭锟半导体有限公司 | Method for etching contact hole without stop layer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101452879A (en) * | 2007-12-05 | 2009-06-10 | 联华电子股份有限公司 | Cleaning method after opening etching |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6713402B2 (en) * | 2002-05-31 | 2004-03-30 | Texas Instruments Incorporated | Methods for polymer removal following etch-stop layer etch |
| US20060148243A1 (en) * | 2004-12-30 | 2006-07-06 | Jeng-Ho Wang | Method for fabricating a dual damascene and polymer removal |
| CN101459125B (en) * | 2007-12-13 | 2011-08-17 | 中芯国际集成电路制造(上海)有限公司 | Connection pore forming method |
-
2015
- 2015-01-09 CN CN201510011973.XA patent/CN105826245B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101452879A (en) * | 2007-12-05 | 2009-06-10 | 联华电子股份有限公司 | Cleaning method after opening etching |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105826245A (en) | 2016-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110957356B (en) | Semiconductor device manufacturing method and semiconductor device | |
| US6890391B2 (en) | Method of manufacturing semiconductor device and apparatus for cleaning substrate | |
| TWI234872B (en) | Method for forming novel BARC open for precision critical dimension control | |
| CN105826245B (en) | The forming method of semiconductor structure | |
| CN101452879A (en) | Cleaning method after opening etching | |
| CN105097650B (en) | The forming method of contact plunger | |
| CN105336662B (en) | The forming method of semiconductor structure | |
| US11942362B2 (en) | Surface modification layer for conductive feature formation | |
| CN106206408B (en) | Method for forming semiconductor structure | |
| CN106409751B (en) | Method for forming semiconductor structure | |
| CN106683996B (en) | Metal silicide and method for manufacturing contact hole on metal silicide | |
| CN104900481B (en) | The method for cleaning pad | |
| CN106486365B (en) | The forming method of semiconductor devices | |
| CN104134630B (en) | A kind of method for reducing side wall damage of ultralow dielectric constant film | |
| US11319513B2 (en) | Non-aqueous tungsten compatible metal nitride selective etchants and cleaners | |
| US20120178257A1 (en) | Solutions for cleaning semiconductor structures and related methods | |
| TWI354333B (en) | Cleaning method following opening etch | |
| CN106033719B (en) | Method for forming semiconductor structure | |
| CN105336664B (en) | Lithographic method | |
| CN106653693B (en) | Improve the method for core devices and input and output device performance | |
| US7288487B1 (en) | Metal/oxide etch after polish to prevent bridging between adjacent features of a semiconductor structure | |
| CN105742229B (en) | The forming method of semiconductor structure | |
| CN105742183B (en) | The forming method of semiconductor structure | |
| CN105742182B (en) | The forming method of semiconductor structure | |
| US11670499B2 (en) | Method of forming conductive feature including cleaning step |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |