CN103871886A - Forming method for transistor - Google Patents
Forming method for transistor Download PDFInfo
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- CN103871886A CN103871886A CN201210552997.2A CN201210552997A CN103871886A CN 103871886 A CN103871886 A CN 103871886A CN 201210552997 A CN201210552997 A CN 201210552997A CN 103871886 A CN103871886 A CN 103871886A
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- 239000010410 layer Substances 0.000 claims abstract description 75
- 239000004065 semiconductor Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000011229 interlayer Substances 0.000 claims abstract description 36
- 229920000642 polymer Polymers 0.000 claims abstract description 34
- 238000001312 dry etching Methods 0.000 claims abstract description 23
- 239000003518 caustics Substances 0.000 claims abstract description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 35
- 239000004020 conductor Substances 0.000 claims description 26
- 230000015572 biosynthetic process Effects 0.000 claims description 25
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 18
- 238000001039 wet etching Methods 0.000 claims description 15
- 230000008021 deposition Effects 0.000 claims description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910004166 TaN Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
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- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- SECXISVLQFMRJM-UHFFFAOYSA-N N-Methylpyrrolidone Chemical group CN1CCCC1=O SECXISVLQFMRJM-UHFFFAOYSA-N 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
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- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
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- 238000007254 oxidation reaction Methods 0.000 description 3
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- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000000047 product Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
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- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
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- 239000010936 titanium Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000004480 active ingredient Substances 0.000 description 1
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- 238000000137 annealing Methods 0.000 description 1
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- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a forming method for a transistor. The forming method comprises the following steps of providing a semiconductor substrate, and forming a pseudo gate, and a source area and a drain area, which are positioned in the semiconductor substrate on the two sides of the pseudo gate, on the semiconductor substrate; forming an interlayer dielectric layer on the semiconductor substrate to cover the source area and the drain area; after the interlayer dielectric layer is formed, removing the pseudo gate to form a pseudo gate trench in a dry etching way; after the pseudo gate is removed in the dry etching way, removing a polymer generated in a dry etching process in a wet corrosion way, wherein the PH value of a corrosive agent is greater than 6 and smaller than 7 or greater than 7 and smaller than 8, and the corrosive agent contains fluoride; after the polymer is removed in the wet corrosion way, forming a gate in the pseudo gate trench. According to the forming method, the corrosive agent is used for substantially removing the polymer on the sidewalls and the bottom of the pseudo gate trench, and the gate can form barrier-free contact with the dielectric layer of the gate or the gate on the sidewalls of the pseudo gate trench; the performance of the transistor is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of transistorized formation method.
Background technology
In the prior art, " rear grid (gate last) " technique is a main technique that forms metal gates.The feature of this technology is to form metal gates after silicon chip is leaked/source region Implantation operation and high-temperature annealing step subsequently complete again.
In the rear grid technique of prior art, form transistorized method, generally include: first, in Semiconductor substrate, form dummy grid; Afterwards, in the Semiconductor substrate of dummy grid both sides, form source region and drain region; Then, form interlayer dielectric layer in Semiconductor substrate, cover source region and drain region, the upper surface of interlayer dielectric layer and dummy grid upper surface maintain an equal level; And then, etching is removed dummy grid, forms pseudo-gate groove in interlayer dielectric layer; Finally, in described pseudo-gate groove, fill metal, form metal gates.
But the performance of the semiconductor device that the rear grid technique of use prior art is made is not good.
More knowledge about rear grid technique, please refer to the Chinese patent literature disclosed, publication number is CN102044421A on May 4th, 2011.
Summary of the invention
The problem that the present invention solves is that the transistor performance that forms of the rear grid technique of prior art is not good.
For addressing the above problem, the invention provides a kind of new transistorized formation method, comprising:
Semiconductor substrate is provided, in Semiconductor substrate, is formed with dummy grid, is arranged in source region and the drain region of the Semiconductor substrate of dummy grid both sides;
In Semiconductor substrate, form interlayer dielectric layer, cover described source region and drain region;
Form after interlayer dielectric layer, use dry etching to remove described dummy grid, form pseudo-gate groove;
Remove after described dummy grid at dry etching, use wet etching to remove the polymer producing in described dry etching process, wherein, the pH value of the corrosive agent of use is greater than 6 and is less than 7 or be greater than 7 and be less than 8, and comprises fluoride in described corrosive agent;
Remove after described polymer at wet etching, in described pseudo-gate groove, form grid.
Optionally, described fluoride comprises: hydrofluoric acid or hydrogen PVF.
Optionally, described corrosive agent also comprises hydrogen peroxide, and the concentration (quality) of hydrogen peroxide is less than 1%.
Optionally, use dry etching to remove described dummy grid, the etching gas of use is O
2.
Optionally, use dry etching to remove described dummy grid, the etching gas of use also comprises NF
3, HBr or CF
4in one or more.
Optionally, form the method in dummy grid, source region, drain region, comprising:
Deposition dummy grid material, covers Semiconductor substrate;
Graphical described dummy grid material, forms described dummy grid;
In the Semiconductor substrate of described dummy grid both sides, carry out Implantation, form source region and drain region.
Optionally, the material of described dummy grid comprises polysilicon, silicon nitride or amorphous carbon.
Optionally, form the method for grid, comprising:
Deposits conductive material, covers interlayer dielectric layer, fills pseudo-gate groove;
Removal exceeds the electric conducting material of described interlayer dielectric layer, remains the electric conducting material in described pseudo-gate groove, as grid.
Optionally, also comprise and form the high K dielectric layer being positioned under described grid, as gate dielectric layer;
The method that forms described high K dielectric layer, comprising:
Remove after described polymer at wet etching, deposit before described electric conducting material, deposition high K dielectric layer material, covers interlayer dielectric layer, fills pseudo-gate groove;
When removal exceeds the electric conducting material of described interlayer dielectric layer, also remove the high K dielectric layer material that exceeds interlayer dielectric layer, remain the high K dielectric layer in described pseudo-gate groove, as gate dielectric layer.
Optionally, remove the method for the electric conducting material that exceeds described interlayer dielectric layer, comprise chemico-mechanical polishing or return and carve.
Optionally, the material of described grid comprises: one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
Optionally, also comprise: form source region and drain region in Semiconductor substrate before, form and be positioned at described dummy grid side wall around.
Optionally, form the method that is positioned at dummy grid side wall around, comprising: deposition spacer material, covers Semiconductor substrate, dummy grid;
Use back spacer material described in carving technology etching, around dummy grid, form side wall.
Optionally, the material of described interlayer dielectric layer is silica.
Optionally, described transistor is N-type transistor or P transistor npn npn.
Compared with prior art, the present invention has the following advantages:
The present invention is directed to rear grid technique, remove the process of dummy grid, a kind of new wet etching method is provided, form and be attached to the sidewall of pseudo-gate groove and the polymer of bottom to remove dry etching dummy grid process.In the present invention, the pH value of the corrosive agent of wet etching course is greater than 6 and is less than 7 or be greater than 7 and be less than 8, and comprises fluoride in described corrosive agent.This corrosive agent has weak acid or alkalescent, removing in the process of polymer, can not cause damage to the sidewall of pseudo-gate groove or bottom, also can not cause damage to adjacent semiconductor device.Fluoride in corrosive agent is to remove oxide in polymer and the active ingredient of silicon-containing polymer.Use corrosive agent of the present invention, the polymer in pseudo-gate groove is removed substantially, and pseudo-gate groove has more smooth sidewall.Like this, in pseudo-gate groove, form grid, described grid has more neat surface in pseudo-gate groove side-walls, stablizes and improved transistorized performance, promotes transistorized reliability.In addition, the polymer of pseudo-gate groove bottom is also removed substantially, electric conducting material can with the gate dielectric layer of pseudo-gate groove bottom, also form accessible contact with the grid of pseudo-gate groove sidewall.That is to say, transistorized formation method of the present invention has avoided polymer on the impact of transistor performance, further to have improved transistorized performance.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the transistorized formation method of the specific embodiment of the invention;
Fig. 2～Fig. 5 is the cross-sectional view of the transistorized formation method of the specific embodiment of the invention.
Embodiment
The problem that inventor exists for the rear grid technique of prior art, is studied, and finds: using dry etching to remove in dummy grid, can generate polymer, be attached to bottom and the sidewall of pseudo-gate groove.For example, in dry etch process, conventionally in etching reaction chamber, pass into oxygen, partial oxidation can with polysilicon or etching reaction chamber in other materials react, generate oxide, oxide can be considered a kind of composition of polymer.Although, follow-up use wet etching is removed polymer, but in prior art, normally used corrosive agent is 1-METHYLPYRROLIDONE (NMP, N-methyl-2-pyrrolidone) solvent or EKC solvent (a kind of alkaline solution being provided by EKC Technology Inc of Du Pont).Nmp solvent and EKC solvent all have strong basicity, removing in polymer, have also caused the ability of erosion removal polymer of damage and nmp solvent or EKC solvent not good to adjacent semiconductor device, and most of polymer cannot be removed.This can produce following problem: on the sidewall of pseudo-gate groove, contain residual polyalcohol, the sidewall that makes pseudo-gate groove is uneven, and the sidewall of pseudo-gate groove has surperficial projection.Like this, the metal gates forming in pseudo-gate groove has rough surface in pseudo-gate groove side-walls, and then has influence on transistorized performance.And, do not remove clean polymer and directly contact with grid, also can have influence on transistorized performance.
Inventor, for the problems referred to above, through creative work, obtains a kind of formation method of new semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.A lot of details are set forth in the following description so that fully understand the present invention.But the present invention can implement to be much different from other modes described here, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that, and therefore the present invention is not subject to the restriction of following public specific embodiment.
With reference to Fig. 2, and in conjunction with reference to Fig. 1, execution step S11, provides Semiconductor substrate 100, is formed with dummy grid 101 in Semiconductor substrate 100, be arranged in source region 102 and the drain region 103 of the Semiconductor substrate 100 of dummy grid 101 both sides.
In specific embodiment, the material of described Semiconductor substrate 100 can be monocrystalline silicon, monocrystalline germanium or single-crystal silicon Germanium; Also can be silicon-on-insulator (SOI); Or can also comprise other material, III-V compounds of group such as such as GaAs.In described Semiconductor substrate 100, be formed with device architecture (not shown), the isolation structures such as such as isolation trench structure are for the isolation between adjacent transistor.
In specific embodiment, in the Semiconductor substrate 100 under dummy grid 101, be also formed with titanium nitride layer (not shown), when titanium nitride layer can form grid in follow-up pseudo-gate groove, the electric conducting material of barrier grid spreads in channel region.
In specific embodiment, form the method for dummy grid 101, comprising: in Semiconductor substrate 100, deposit dummy grid material, select chemical vapor deposition method, dummy grid material covers Semiconductor substrate 100; Graphical dummy grid material, forms dummy grid 101.Described graphical dummy grid material is: on dummy grid material layer, form patterned photoresist layer, define the position of dummy grid to be formed; Taking described patterned photoresist layer as mask, etching dummy grid material, stops to Semiconductor substrate 100, if be formed with titanium nitride layer 101 times at dummy grid, stops to titanium nitride layer; Remove patterned photoresist layer.
In specific embodiment, the material of described dummy grid 101 is selected polysilicon, silicon nitride or amorphous carbon.In the present embodiment, select polysilicon, and carry out the elaboration of follow-up scheme as an example of polysilicon example.
In specific embodiment, around dummy grid 101, be also formed with side wall (not shown).Forming after dummy grid 101, be arranged in the source region and drain region of Semiconductor substrate 100 in formation before, formation side wall around dummy grid 101.The method that forms side wall, comprising: deposition spacer material, covers Semiconductor substrate, dummy grid; Use back spacer material described in carving technology etching, around dummy grid, form side wall.Conventionally the material selective oxidation silicon of side wall.
In specific embodiment, form the method in source region 102, drain region 103, comprising: on dummy grid 101, form mask layer; Taking described mask layer as mask, carry out Implantation, in Semiconductor substrate 100, form source region 102 and drain region 103.Wherein, the ionic type of injection, determines according to transistorized type to be formed.If transistor to be formed is nmos pass transistor, the type of Implantation is P type ion, as boron; If transistor to be formed is PMOS transistor, the type of Implantation is N-type ion.Concrete technology condition is well known to those skilled in the art, and does not repeat them here.
With reference to Fig. 3, and in conjunction with Fig. 1, execution step S12 forms interlayer dielectric layer 104 in Semiconductor substrate 100, covers source region 102 and drain region 103.
In specific embodiment, the common selective oxidation silicon of the material of interlayer dielectric layer 104, also has other can material selection certainly, can select according to actual needs.The step that forms interlayer dielectric layer 104, is generally first to deposit, then carries out planarization, and for example chemico-mechanical polishing or time quarter, so that the upper surface of the upper surface of interlayer dielectric layer 104 and dummy grid 101 maintains an equal level.
With reference to Fig. 4, and in conjunction with Fig. 1, execution step S13, forms after interlayer dielectric layer 104, uses dry etching to remove described dummy grid 101, forms pseudo-gate groove 105.
In specific embodiment, use dry etch process, can obtain thering is the pseudo-gate groove compared with vertical sidewall.In dry etching process, can produce etching product, this etching product can be deposited on sidewall and the bottom of pseudo-gate groove 105.In dry etching, conventionally in etching reaction chamber, pass into O
2, can play the effect of removing dummy grid 101, and can supplement the oxygen that interlayer dielectric layer 104 loses in etching process.But producing in above-mentioned positive effect, the oxygen passing into has also generated oxide with some reactant reaction, the polymer that this oxide forms in as dry etching process together with aforementioned etching product.Except pass into O in etching reaction chamber
2outside, in dry etching process, also comprise in reaction chamber and pass into NF
4, HBr or CF
4deng gas one or more, be generally mist multiple in them.These polymer must be removed after dry etching, otherwise can affect transistorized performance.
Therefore, remove after dummy grid 101 at dry etching, continue with reference to Fig. 4, and in conjunction with Fig. 1, execution step S14, uses wet etching to remove the polymer producing in dry etching process, wherein, the pH value of the corrosive agent of use is greater than 6 and is less than 7 or be greater than 7 and be less than 8, and comprises fluoride in corrosive agent.
In specific embodiment, the pH value of described corrosive agent is greater than 6 and is less than 7 or be greater than 7 and be less than 8, has weak acid or alkalescent, can not damage sidewall and the bottom of pseudo-gate groove, and also can not damage adjacent semiconductor device.And fluoride wherein can be removed most silicon-containing polymer and oxide, and silicon-containing polymer is also the main component in polymer.Therefore, the corrosive agent that the present invention uses not only can be removed the polymer that remains in pseudo-gate groove sidewall and bottom, can also avoid adjacent semiconductor device to cause damage.In concrete enforcement, described fluoride comprises the composition such as hydrofluoric acid or hydrogen PVF.
In specific embodiment, described corrosive agent also can comprise hydrogen peroxide (H
2o
2), wherein H
2o
2concentration (quality) scope for being less than 1%, hydrogen peroxide can effectively strengthen removes the effect of oxide.Hydrogen peroxide concentration scope is selected to be less than 1%, can reduce hydrogen peroxide and adjacent semiconductor device be produced to the possibility of damage.
In the present embodiment, described corrosive agent is selected the ATMI TK12-6 solvent that ATMI.Inc produces.Wherein, the pH value of ATMI TK12-6 solvent is greater than 6 and is less than 7, has faintly acid, contains the composition such as hydrogen peroxide, fluoride that concentration (quality) is 0.6% in this solvent.In concrete production, carry out about 2min of duration of wet etching, corrosion rate is approximately
and corrosive agent of the prior art, as EKC solvent, pH value is approximately 9, there is the hydrogen peroxide of strong basicity and higher concentration, can damage other semiconductor device, and the corrosion rate of EKC is larger, can, in erosion removal polymer process, additionally corrode other semiconductor device.The corrosion rate of ATMI TK12-6 solvent is less, has avoided the metal in adjacent semiconductor device or other materials to cause extra corrosion.
In the present embodiment, wet etching has been removed the polymer that remains in pseudo-gate groove 105 sidewalls and bottom, makes sidewall and the bottom flat of pseudo-gate groove 105, has also avoided the negative influence of polymer to transistor performance.
With reference to Fig. 4 and Fig. 5, and in conjunction with Fig. 1, execution step S15, removes after polymer at wet etching, in pseudo-gate groove 105, forms grid 106.Grid 106 can be metal gates, or the grid of other electric conducting materials.
In specific embodiment, form the method for grid 106, comprising: deposits conductive material, covers interlayer dielectric layer 104 and fill pseudo-gate groove 105; Removal exceeds the electric conducting material of interlayer dielectric layer 104, remains the electric conducting material in pseudo-gate groove 105.In the present embodiment, can use chemico-mechanical polishing or return etching technics, remove the electric conducting material that exceeds interlayer dielectric layer 104, comprise and remove the electric conducting material of interlayer dielectric layer 104 upper surfaces and remove the electric conducting material that exceedes pseudo-gate groove 105.
In concrete production, between grid 106 and Semiconductor substrate 100, be also formed with high K dielectric layer, as gate dielectric layer (not shown).The method that forms high K dielectric layer comprises: remove after polymer at wet etching, deposit before described electric conducting material, deposition high K dielectric layer material, covers interlayer dielectric layer and fill pseudo-gate groove; Then, remove while exceeding the electric conducting material of described interlayer dielectric layer, also get rid of the high K dielectric layer that exceeds interlayer dielectric layer, like this, at the remaining high K dielectric layer of sidewall and bottom of pseudo-gate groove, as gate dielectric layer.Certainly, in specific embodiment, also can first form high K dielectric layer in pseudo-gate groove bottom, forming after high K dielectric layer, then on the high K dielectric layer in pseudo-gate groove, form grid.The gate dielectric layer of high K dielectric layer coordinates grid 106, as metal gates, can obtain the transistor of better performance.Transistorized type can be N-type transistor or P transistor npn npn.
In specific embodiment, electric conducting material comprises one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.In concrete production, determine the concrete scope of electric conducting material according to transistorized type to be formed.
Due to, after execution step S14, wet etching has been removed the residual polyalcohol in pseudo-gate groove 105, and the grid 106 of formation has more smooth surface at pseudo-gate groove 105 places, has improved transistorized performance.In addition, the polymer of pseudo-gate groove 105 sidewalls and bottom is removed substantially, electric conducting material can with accessible contact of gate dielectric layer of pseudo-gate groove 105 bottoms.That is to say, avoided polymer on the impact of transistor performance, to have improved transistorized performance, lifting can transistorized reliability.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a transistorized formation method, is characterized in that, comprising:
Semiconductor substrate is provided, in Semiconductor substrate, is formed with dummy grid, is arranged in source region and the drain region of the Semiconductor substrate of dummy grid both sides;
In Semiconductor substrate, form interlayer dielectric layer, cover described source region and drain region;
Form after interlayer dielectric layer, use dry etching to remove described dummy grid, form pseudo-gate groove;
Remove after described dummy grid at dry etching, use wet etching to remove the polymer producing in described dry etching process, wherein, the pH value of the corrosive agent of use is greater than 6 and is less than 7 or be greater than 7 and be less than 8, and comprises fluoride in described corrosive agent;
Remove after described polymer at wet etching, in described pseudo-gate groove, form grid.
2. formation method as claimed in claim 1, is characterized in that, described fluoride comprises: hydrofluoric acid or containing PVF.
3. formation method as claimed in claim 1, is characterized in that, described corrosive agent also comprises hydrogen peroxide, and the concentration (quality) of hydrogen peroxide is less than 1%.
4. formation method as claimed in claim 1, is characterized in that, uses dry etching to remove described dummy grid, and the etching gas of use is O
2.
5. formation method as claimed in claim 3, is characterized in that, uses dry etching to remove described dummy grid, and the etching gas of use also comprises NF
3, HBr or CF
4in one or more.
6. formation method as claimed in claim 1, is characterized in that, forms the method in dummy grid, source region, drain region, comprising:
Deposition dummy grid material, covers Semiconductor substrate;
Graphical described dummy grid material, forms described dummy grid;
In the Semiconductor substrate of described dummy grid both sides, carry out Implantation, form source region and drain region.
7. formation method as claimed in claim 1, is characterized in that, the material of described dummy grid comprises polysilicon, silicon nitride or amorphous carbon.
8. formation method as claimed in claim 1, is characterized in that, forms the method for grid, comprising:
Deposits conductive material, covers interlayer dielectric layer, fills pseudo-gate groove;
Removal exceeds the electric conducting material of described interlayer dielectric layer, remains the electric conducting material in described pseudo-gate groove, as grid.
9. formation method as claimed in claim 8, is characterized in that, also comprises and forms the high K dielectric layer being positioned under described grid, as gate dielectric layer;
The method that forms described high K dielectric layer, comprising:
Remove after described polymer at wet etching, deposit before described electric conducting material, deposition high K dielectric layer material, covers interlayer dielectric layer, fills pseudo-gate groove;
When removal exceeds the electric conducting material of described interlayer dielectric layer, also remove the high K dielectric layer material that exceeds interlayer dielectric layer, remain the high K dielectric layer in described pseudo-gate groove, as gate dielectric layer.
10. formation method as claimed in claim 8, is characterized in that, removes the method for the electric conducting material that exceeds described interlayer dielectric layer, comprises chemico-mechanical polishing or returns and carve.
11. formation methods as claimed in claim 1, is characterized in that, the material of described grid comprises: one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
12. formation methods as claimed in claim 1, is characterized in that, also comprise: form source region and drain region in Semiconductor substrate before, form and be positioned at described dummy grid side wall around.
13. formation methods as claimed in claim 12, is characterized in that, form the method that is positioned at dummy grid side wall around, comprising: deposition spacer material, covers Semiconductor substrate, dummy grid;
Use back spacer material described in carving technology etching, around dummy grid, form side wall.
14. formation methods as claimed in claim 1, is characterized in that, the material of described interlayer dielectric layer is silica.
15. formation methods as claimed in claim 1, is characterized in that, described transistor is N-type transistor or P transistor npn npn.
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