CN102479497B - The drive unit of display panels - Google Patents
The drive unit of display panels Download PDFInfo
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- CN102479497B CN102479497B CN201110404726.8A CN201110404726A CN102479497B CN 102479497 B CN102479497 B CN 102479497B CN 201110404726 A CN201110404726 A CN 201110404726A CN 102479497 B CN102479497 B CN 102479497B
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- source wiring
- driving force
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- display panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
- G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The object of the invention is to, utilizing row reversion to drive in the drive unit driven display panels, reduce power consumption further.Executing in alive output buffer (251) to source wiring, drive in the specified time limit after starting in a frame, biasing circuit (262) applies the bias voltage of the driving force of step-down amplifier (261), first switch (263) becomes open mode, and second switch (264) becomes closure state.If specified time limit terminates, then the first switch (263) becomes closure state, and second switch (264) becomes open mode, is driven by the voltage signal from D-A converter source wiring.
Description
Technical field
The present invention relates to and utilize row reversion to drive the drive unit driving the display panels of display panels.
Background technology
When driving the display panels using TFT (ThinFilmTransistor: thin film transistor (TFT)), the grid cut-off voltage VGL need following voltage: namely, make the gate-on voltage VGH of the TFT gate turn-on of the pixel of the cross part being arranged at each grid wiring and source wiring, the grid of TFT being ended, be applied to TFT source electrode data voltage (source voltage) VD and be applied to the common electric voltage VCOM of public electrode.
Make the reasons such as its lost of life owing to utilizing during direct voltage drive display panels, therefore, generally, use the driving method exchanging and drive as driving display panels.As interchange driving, there is line reversion and drive, arrange reversion driving, some reversion driving etc. (for example, referring to patent documentation 1).
So-called row reversion drives, refer to following a kind of driving method: namely, horizontal pixel group (line: OK) is such as driven from the upper side to the lower side successively in the LCDs that pixel arrangement becomes rectangular, the data voltage in a frame is made such as to become positive polarity, negative polarity, positive polarity, negative polarity from the source wiring in left side (row) towards the row on right side ... make in next frame, the polarity of the polarity of the data voltage of each row former frame is with it contrary.
Hereafter, the current potential of source electrode is called positive polarity state higher than the state of common electric voltage, the current potential of source electrode is called negative polarity state lower than the state of common electric voltage.
In patent documentation 1, describe following methods: namely, in order to reduce the power consumption of drive unit, in vertical blanking period, make the voltage reversal being applied to source wiring, or when vertical blanking period starts, source wiring is temporarily charged to common potential.By adopting this structure, thus when can reduce switch polarity, flow through the peak point current (dash current) of source electrode driver.
In addition, in patent documentation 1, describe following methods: namely, in vertical blanking period, carry out the electric charge shared structure making adjacent source wiring short circuit, then, the positive polarity of assigned voltage and the data voltage of negative polarity are supplied to source wiring, and perform electric charge and share, thus make the current potential of source wiring close to common electric voltage.In addition, for the data voltage of assigned voltage being supplied to source wiring, in the level valid period started most of vertical blanking period, the source electrode driver exporting data voltage to source wiring is provided it to.
Prior art document
Patent documentation
Patent documentation 1:
Japanese Patent Laid-Open 2008-8928 publication
Summary of the invention
But, when using the drive unit of the display panels described in patent documentation 1, the magnitude of voltage precalculating etc. and decide the data voltage exported in the level valid period started most of vertical blanking period must be utilized.In addition, generally speaking, the kind quantity of the magnitude of voltage of the data voltage that can use is the quantity corresponding to number of greyscale levels, can not be set as arbitrary desired value.And, in order to export data voltage in the level valid period started most of vertical blanking period, must according to the structure of general timing control circuit, subtend source electrode driver or gate drivers provide the structure of the timing control circuit of clock signal, latch signal to carry out larger change.In addition, the power consumption during the actual driving carried out for showing can not being reduced in (during display).
Therefore, the object of the invention is to utilize row reversion to drive in the drive unit driven display panels a kind of, utilize simple structure to reduce power consumption further.
The drive unit of display panels of the present invention comprises source electrode driver, this source electrode driver utilizes row reversion to drive and drives the source wiring of display panels, the mode that the source wiring of above-mentioned display panels intersects with many grid wirings and many source wiring is configured, it is characterized in that, the driving force of the baseline (during more than single line) of the single line that source electrode driver is at least initial relative to the driving of each frame and after reducing the baseline of each frame during the driving force of period at least partially.
Source electrode driver reduces the structure of the driving force of whole period during adopting such as after baseline.
Source electrode driver adopts following structure: namely, such as, during after baseline, make with each period regularly generated (such as, during each line) before the driving force of specified time limit (front half-interval) compare, reduce the driving force in the interval (rear half-interval) after regulation interval.By adopting this structure, can try hard to prevent the reduction of display quality etc. and reduce current sinking on the basis of characteristic considering display panels.In addition, the structure of driving force lower than the driving force of baseline in the regulation interval made above can also be adopted.In addition, source electrode driver also can comprise the interval adjustment unit adjusted regulation length of an interval degree above.
Source electrode driver adopts following structure: namely, comprise such as outgoing route configuration part, this outgoing route configuration part is set as the voltage signal corresponding to data-signal being applied to the state of source wiring by amplifier or not being applied to any one state of state of source wiring by amplifier, outgoing route configuration part is when reducing driving force, be set as the state voltage signal corresponding to data-signal not being applied to source wiring by amplifier, when improving driving force, outgoing route configuration part is set as the state voltage signal corresponding to data-signal being applied to source wiring by amplifier, amplifier makes exportable electric current rise to exportable electric current higher than corresponding to when the voltage signal former state of data-signal outputs to source wiring.
Source electrode driver also can adopt following structure: namely, comprise the amplifier that can make exportable curent change, the voltage signal corresponding to data-signal is applied to source wiring by amplifier, amplifier is when improving driving force, under the state making exportable electric current rise to higher than exportable electric current during reduction driving force, the voltage signal corresponding to data-signal is applied to source wiring.
Source electrode driver also can comprise source wiring initial setting section, and this source wiring initial setting section, in vertical blanking period, makes adjacent source wiring short circuit or each source wiring is connected with regulation current potential.By adopting this structure, simpler structure can be adopted, suppressing the dash current flowing into source electrode driver during switch polarity, thus reducing power consumption.
According to the present invention, row reversion can be utilized to drive in the drive unit driven display panels a kind of, utilize simple structure to reduce power consumption further.
Accompanying drawing explanation
Fig. 1 is the block diagram of the structure example representing the liquid crystal indicator applying drive unit of the present invention.
Fig. 2 is the key diagram representing data voltage.
Fig. 3 is the sequential chart of the action case of the embodiment 1 representing drive unit of the present invention.
Fig. 4 is the sequential chart of the action case of the embodiment 1 representing drive unit of the present invention.
Fig. 5 is the block diagram of the structure example representing output buffer.
Fig. 6 is the key diagram of an example of an example of the relation represented between the signal condition of control signal Cont2 and the output state of amplifier and the output state of amplifier.
Fig. 7 is the block diagram of the structure of the outgoing side representing output buffer.
Fig. 8 is the key diagram of the relation of the state representing control signal Cont1 and each switch.
Fig. 9 is the key diagram of the current sinking schematically shown when using row reversion to drive.
Figure 10 is the sequential chart of the action case of the embodiment 2 representing drive unit of the present invention.
Figure 11 carries out amplifying the sequential chart represented to the action case of embodiment 2.
Figure 12 carries out amplifying the sequential chart represented to other action cases of embodiment 2.
Reference numeral
10 display panels
20 source electrode drivers
21 shift registers
22 the 1st latch cicuits
23 the 2nd latch cicuits
24D-A converter
25 buffer circuits
30 gate drivers
40 control parts (timing control circuit)
251,252 output buffers
261 amplifiers
262 biasing circuits
263 the 1st switches
264 the 2nd switches
266 the 1st output switchs
267 the 3rd switches
268 the 2nd output switchs
Embodiment
Below, with reference to accompanying drawing, embodiments of the present invention are described.
Embodiment 1.
Fig. 1 is the block diagram of the structure example representing the liquid crystal indicator applying drive unit of the present invention.In the liquid crystal indicator shown in Fig. 1, rectangular multiple pixels 12 are formed with to display panels 10.In order to form pixel, transverse direction (line direction) being provided with many grid wirings 13, at column direction, the mode crossing with grid wiring 13 being provided with many source wiring 14.Then, TFT15 is formed with at the cross part of grid wiring 13 and source wiring 14.The drain electrode 16 of TFT15 is connected with pixel electrode.
The position relative with the substrate being formed with grid wiring 13, source wiring 14 and pixel 15 is provided with opposing substrate (not shown), between the substrate being formed with pixel 12 and opposing substrate, accompanies liquid crystal.Opposing substrate is formed comparative electrode (public electrode), comparative electrode is set as common potential VCOM.In addition, from electricity, owing to liquid crystal can be regarded as the element with electric capacity, therefore, the capacitor 17 that one end is connected with pixel electrode, the current potential of the other end becomes common potential VCOM has been shown in Fig. 1.
Gate drivers 30 is such as according to the order driving grid wiring 13 successively of line.For the pixel electrode in the pixel be connected with the grid wiring 13 that namely selected grid wiring 13 is applied with gate-on voltage VGH, apply data voltage (voltage corresponding to data-signal) VD by source wiring 14.
In the structure example shown in Fig. 1, the source electrode driver 20 of source wiring 14 is driven to comprise: shift register 21; Successively data-signal DATA is carried out latching and the 1st latch cicuit 22 exported; Disposable the 2nd latch cicuit 23 being taken into the output of the 1st latch cicuit 22; Export the D-A converter 24 of the simulating signal (analog voltage) of the value of the output (numerical data) corresponding to the 2nd latch cicuit 23; And the output of D-A converter 24 is carried out the buffer circuits 25 of Current amplifier.
With what be equivalent to that control part (timing control circuit) 40 exports, shift register 21 represents that the horizontal initial pulse STH of the signal started between selecting period is for opportunity, generate data be taken into signal and export according to the clock signal clk of data shifts.In the present embodiment, the quantity of source wiring 14 is set to m (m be positive integer and be 3 multiple).Data-signal be RGB parallel when, the data corresponding with clock signal clk are three RGB.Therefore, the output signal quantity of shift register 21 is m/3.The output of the 1st group is such as set to conducting state (representing the state that data are taken into) according to l clock (l:1 ~ m/3) of clock signal clk by shift register 21.In addition, in the present embodiment, line is utilized to drive method to drive display panels 10 successively, during being equivalent to drive single line between selecting period.
From timing control circuit 40 to the 1st latch cicuit 22 successively outputting data signals DATA.In addition, m/3 signal is inputted from shift register 21 to the 1st latch cicuit 22.When the signal of the 1st latch cicuit 22 l group (l:1 ~ m/3) in m signal becomes conducting state, the data (data-signal DATA) of l group are carried out latching and exporting.
2nd latch cicuit 23, when the negative edge of gating signal STB (hereinafter referred to as latch signal STB) such as exported from timing control circuit 40, is disposablely taken into from the 1st latch cicuit 22 signal be latched.
The power circuit (not shown) comprised from timing control circuit 40 provides such as voltage Vn (n:0 ~ 15) to D-A converter 24.As shown in Figure 2, V8 ~ V15 is the voltage higher than common electric voltage VCOM, and V0 ~ V7 is the voltage lower than common electric voltage VCOM.In addition, V8 ~ V15 is the voltage driven for positive polarity, and V0 ~ V7 is the voltage driven for negative polarity.
The signal that m represents the value of the level (high level or low level) corresponding to the polarity inversion signal POL exported from timing control circuit 40 is exported from D-A converter 24.Such as, when the level of polarity inversion signal POL is high level, odd number signal in m signal is set to the signal of the value corresponding with the level of the signal inputted by the 2nd latch cicuit 23 and positive polarity, the even number signal in m signal is set to the signal of the value corresponding with the level of the signal inputted by the 2nd latch cicuit 23 and negative polarity.In addition, under the level of polarity inversion signal POL is low level situation, odd number signal in m signal is set to the signal of the value corresponding with the level of the signal inputted by the 2nd latch cicuit 23 and negative polarity, the even number signal in m signal is set to the signal of the value corresponding with the level of the signal inputted by the 2nd latch cicuit 23 and positive polarity.
In addition, in the present embodiment, for the purpose of simplifying the description, source electrode driver 20 uses voltage V8 ~ V15 to input 8 reference voltages of positive polarity, and utilize the ladder shaped resistance in driver to realize 64 gray scales, use voltage V0 ~ V7 to show 64 gray scales with 8 of negative polarity reference voltages.Also the present invention can be applied when realizing a greater variety of gray scale.In addition, in D-A converter 24, be configured with the ladder shaped resistance of input part, realize many gray scales.
In addition, in the construction shown in fig. 1, power circuit comprises timing control circuit 40, but power circuit also can be provided separately with timing control circuit 40.
The signal (voltage signal) of the voltage corresponding with the value shown in each signal of m the signal that the 2nd latch cicuit 23 exports is outputted to buffer circuits 25 by D-A change-over circuit 24.
Each voltage signal of the m exported from D-A converter 24 voltage signal is applied to m root source wiring 14 by buffer circuits 25.
In addition, the source electrode driver 20 shown in Fig. 1, gate drivers 30 and timing control circuit 40 are textural elements of the drive unit of display panels.
Fig. 3 and Fig. 4 is the sequential chart of the action case of the embodiment 1 representing drive unit of the present invention.Timing control circuit 40 as shown in Figure 3, before starting the control carrying out showing for the image of each frame, exports control signal Cont1.Specifically, during more than a horizontal period (during between two horizontal-drive signals) of vertical blanking period, control signal Cont1 is set to effective level.In the example shown in Fig. 3, effective level is high level.Source electrode driver 20 performs control described later based on control signal Cont1.The maximal value be set to during effective level can be vertical blanking period by control signal Cont1.
In addition, as shown in Figure 3, level reverses by polarity inversion signal POL in units of a frame.When polarity inversion signal POL is high level, positive polarity driving is carried out to the source wiring S (2n-1) of odd number root, negative polarity driving is carried out to the source wiring S (2n) of even number root.When polarity inversion signal POL is low level, negative polarity driving is carried out to the source wiring S (2n-1) of odd number root, positive polarity driving is carried out to the source wiring S (2n) of even number root.In addition, if n is 1 ~ (m/2), m is even number.
And in the present embodiment, timing control circuit 40 as shown in Figure 4, exports control signal Cont2.Specifically, horizontal period more than the horizontal period of the moment started from the control for carrying out image display in each frame (being equivalent between a selecting period) (such as, 1 ~ 3 horizontal period) between, the level of control signal Cont2 is set to the level of regulation.In the diagram, the level that citing shows control signal Cont2 becomes the level of regulation between two horizontal period.Source electrode driver 20 performs specific control described later based on control signal Cont2.
In addition, in the diagram, using during the level of control signal Cont2 becomes specified level as illustrating during high level, but as described below, the level of regulation is actual is not limited to high level.In addition, using during not becoming specified level as illustrating between low period, but, be actually not limited to low level.
Fig. 5 is the block diagram of the structure example of the output buffer 251 represented in buffer circuits 25.Buffer circuits 25 comprises the quantity of source wiring 14 and the output buffer of m.The structure of each output buffer of buffer circuits 25 is identical with the structure shown in Fig. 5.
In the example as shown in fig. 5, output buffer 251 comprises: the amplifier 261 that driving force is variable, and the amplifier 261 variable to this driving force inputs the signal exported by D-A converter 24; 1st switch the 263,1st switch 263 forms a certain state in following two states: namely, will the input of amplifier 261 is supplied to the state of lead-out terminal or not be supplied to the state of lead-out terminal; 2nd switch the 264,2nd switch 264 forms a certain state in following two states: namely, the output of amplifier 261 is supplied to the state of lead-out terminal or is not supplied to the state of lead-out terminal; And biasing circuit 262, this biasing circuit 262 is for changing the exportable electric current (maximum output current) of amplifier 261 according to control signal Cont2.In addition, lead-out terminal is the lead-out terminal for source wiring 14.
In addition, 1st switch 263 and the 2nd switch 264 realize outgoing route configuration part, this outgoing route configuration part sets a certain state in following two states: namely, the signal of the voltage corresponding to data-signal is applied to the state of source wiring 14 by amplifier 261 or is not applied to the state of source wiring 14 by amplifier 261.
Control signal Cont2, as an example, can be the signal of 2 bits.Fig. 6 (A) is the key diagram of an example of the relation represented between the signal condition of control signal Cont2 and the output state of amplifier 261.Fig. 6 (B) is the key diagram of an object lesson of the output state representing amplifier 261.Control signal Cont2 can be also 1 bit, but consider caused by the size of display panels application power, power consumption the raising of selecting range, be preferably the signal of 2 bits.
As shown in Figure 6, be (L at the level of control signal Cont2, L) time, the driving force of amplifier 261 is 130%, when the level of control signal Cont2 is (L, H), driving force is 100%, when the level of control signal Cont2 is (H, L), driving force is 80%.In addition, when the level of control signal Cont2 is (H, H), the voltage signal former state from D-A converter 24 is outputted to lead-out terminal.In addition, " H " represents high level, and " L " represents low level.
In addition, driving force 130% and 80% represents relative to driving force when being (L, H) with the level of control signal Cont2 is the maximum output current of benchmark.
In addition, the driving force (being equivalent to the output C shown in Fig. 6 (A)) when being (H, L) from the driving force of the voltage signal of D-A converter 24 than the level of control signal Cont2 is low.Therefore, compare the exportable electric current in the situation (the 1st switch 263 is closure state and the 2nd switch 264 is open mode) the signal former state of the voltage corresponding with data-signal being applied to source wiring 14, exportable electric current when being applied to source wiring 14 by the voltage signal that the data-signal of amplifier 261 is corresponding when being (H, L) by the level with control signal Cont2 wants large.
Fig. 7 is the block diagram of the structure of the outgoing side of the output buffer 251,252 of the driving two adjacent source wirings 14 representing buffer circuits 25.Output buffer 251 drives the source wiring 14 (such as, the source wiring 14 of the 1st row) of odd number root, and output buffer 252 drives the source wiring 14 (such as, the source wiring 14 of the 2nd row) of even number root.
As shown in Figure 7, the outgoing side of output buffer 251 is provided with the 1st output switch the 266,1st output switch 266 and switches the state that the output of output buffer 251 is passed through and the state that the output of output buffer 251 is not passed through.The outgoing side of output buffer 252 is provided with the 2nd output switch the 268,2nd output switch 268 and switches the state that the output of output buffer 252 is passed through and the state that the output of output buffer 252 is not passed through.In addition, be also provided with the 3rd switch the 267, three switch 267 and switch the state and the state not being connected two adjacent source wiring 14 that connect two adjacent source wiring 14.
In addition, the 1st output switch 266, the 2nd output switch 268 and the 3rd switch 267 are examples for the source wiring initial setting section making adjacent source wiring 14 short circuit.
In addition, the inner structure of output buffer 252 is identical with the inner structure of the output buffer 251 shown in Fig. 5.In addition, in buffer circuits 25, the outgoing side of all output buffers driving source wiring S (2n-1) is provided with the 1st output switch 266 shown in Fig. 7.In addition, the outgoing side of all output buffers driving source wiring S (2n-1) is provided with the 2nd output switch 268 shown in Fig. 7.In addition, driving the output buffer of source wiring S (2n-1) and driving (n:1 ~ (m/2)) between the output buffer of source wiring S (2n) to be provided with the 3rd switch 267 shown in Fig. 7.
Fig. 8 is the key diagram of the relation of the state representing control signal Cont1, each switch (the 1st output switch 266, the 2nd output switch 268 and the 3rd switch 267).As shown in Figure 8, when control signal Cont1 is low level, the 1st output switch 266 and the 2nd output switch 268 become conducting state (closure state), and the 3rd switch 267 becomes off-state (open mode).When control signal Cont1 is high level, the 1st output switch 266 and the 2nd output switch 268 become off-state, and the 3rd switch 267 becomes conducting state.
Then, the sequential chart etc. of reference Fig. 4 illustrates the action of source electrode driver 20.Below, stress two output buffers 251,252 of buffer circuits 25, but for the output buffer beyond two output buffers 251,252 of buffer circuits 25, also carry out identical action with output buffer 251,252.
Timing control circuit 40 as shown in Figure 4, is high level during making control signal Cont1 more than a horizontal period of vertical blanking period.If with reference to Fig. 7 and Fig. 8, then when control signal Cont1 is high level, in buffer circuits 25, the 1st output switch 266 being arranged at the outgoing side of the output buffer of driving odd number root source wiring S (2n-1) becomes open mode, and the 2nd output switch 268 being arranged at the outgoing side of the output buffer of driving even number root source wiring S (2n) becomes open mode.In addition, the 3rd switch 267 be arranged between the output buffer driving the output buffer of source wiring S (2n-1) and driving source wiring S (2n) becomes closure state.
That is, the source wiring S (2n-1) of odd number root is connected with the source wiring S (2n) of adjacent even number root respectively.In addition, each source wiring 14 disconnects with output buffer 251,252.
Consequently, perform electric charge and share, this electric charge share the source wiring 14 by utilizing the voltage driven higher than common electric voltage VCOM current potential, and utilize between the current potential of the source wiring 14 of the voltage driven lower than common electric voltage VCOM and neutralize.That is, the current potential of each source wiring 14 is close to common electric voltage VCOM.
Electric charge is shared in vertical blanking period and performs.Thus, when starting during the display of a frame, because the current potential of each source wiring 14 is close to common electric voltage VCOM, therefore, such as be transferred directly to the situation of the state utilizing positive polarity to drive from the state utilizing negative polarity to drive compared with, dash current when starting during can reducing display.
And, in the present embodiment, timing control circuit 40 as shown in Figure 4, in specified time limit more than a horizontal period in each frame from the moment that the control shown for image starts, namely, drive in a frame in the specified time limit after starting (during driving the line of more than single line), the level of control signal Cont2 is set to the level of regulation.In the present embodiment, the level of regulation is (H, L).
If with reference to Fig. 5 and Fig. 6, then in the output buffer 251 of buffer circuits 25, biasing circuit 262 applies to make the driving force of amplifier 261 be the bias voltage of 80% according to the level of control signal Cont2.In addition, according to the level of control signal Cont2,1st switch 263 becomes open mode (input of amplifier 261 not being supplied to the state of lead-out terminal), and the 2nd switch 264 becomes closure state (output of amplifier 261 is supplied to the state of lead-out terminal).
Thus, in the specified time limit that the level of control signal Cont2 becomes specified level, source wiring 14 is driven with the state of driving force 80%.
The level of control signal Cont2, at the end of specified time limit, is set to the level beyond specified level by timing control circuit 40.In the present embodiment, the level beyond the level of regulation is (H, H).
If with reference to figure 5 and Fig. 6, then in the output buffer 251 of buffer circuits 25,1st switch 263 becomes closure state (input of amplifier 261 being supplied to the state of lead-out terminal), and the 2nd switch 264 becomes open mode (output of amplifier 261 is not supplied to the state of lead-out terminal).Thus, source wiring 14 is driven by the voltage signal from D-A converter 24.
Driving force when driving force due to the voltage signal from D-A converter 24 is (H, L) than the level of control signal Cont2 is low, therefore, after terminating specified time limit, is driven by lower driving force source wiring 14.Consequently, the lower power consumption of source electrode driver 20.
Fig. 9 is the key diagram of the current sinking schematically shown when using row reversion to drive.As shown in Figure 9, use row reversion drive as exchange drive time, and use some reverse to drive etc. other to exchange compared with situation about driving, the power consumption during display is less.That is, as shown in the embodiment, in during showing, even if also source wiring 14 can be driven in the state that driving force is lower.In addition, when using the some reversion driving each pixel being carried out to reversal of poles, the output voltage amplitude of source electrode driver 20 increases, and power consumption becomes large.
As shown in Figure 9, when arranging reversion and driving, source electrode line carries out reversal of poles according to every frame.That is, when starting during showing, need such as be transferred to negative polarity from positive polarity and flow through dash current (A with reference to Fig. 9).If the driving force of output buffer 251 is lower, be then difficult to tackle dash current, may the driving voltage of occurring source driver 20 declines instantaneously, display quality reduces problem.Therefore, in the present embodiment, as mentioned above, in the specified time limit after starting during showing, the driving force (exportable electric current) of source electrode driver 20 is improved.Then, source wiring 14 can be driven with lower driving force, can power consumption be reduced.
In addition, as mentioned above, in the present embodiment, before starting during making display owing to utilizing the electric charge of vertical blanking period to share, the current potential of each source wiring 14 is close to common electric voltage VCOM, therefore, it is possible to dash current when starting during reducing display.Thus, the rising degree of the driving force of the specified time limit after starting during can reducing to show.That is, although in the specified time limit after starting during showing, the driving force of output buffer 251 is improved.But without the need to making it high.
But share even if do not carry out electric charge at vertical blanking period, the control that the specified time limit after starting during showing carries out the driving force improving source electrode driver 20 is also effective.
In addition, in the present embodiment, specified time limit after starting during showing (such as, during more than a horizontal period) in, with Fig. 6 (B) the driving force 80% that represents of citing to drive source wiring 14, but also can with Fig. 6 (B) citing represent 100% or 130% driving force to drive source wiring 14.In addition, in the present embodiment, drive with the state of driving force 80% in specified time limit after starting during showing, after have passed through specified time limit, to drive source wiring 14 from the voltage signal of D-A converter 24, but, if the driving force in specified time limit is higher than have passed through the driving force after specified time limit, then also can use driving force 80% and from the combination beyond the combination of the driving force of the voltage signal of D-A converter 24.
As an example, in the specified time limit after also can starting during showing, drive with the state of driving force 130% or 100% (with reference to Fig. 6), after have passed through specified time limit, drive with driving force 80%.In this case, do not need the 1st switch 263 shown in Fig. 5 and the 2nd switch 264, voltage signal from D-A converter 24 is applied to source wiring 14 by amplifier 261 all the time, the voltage signal corresponding to data-signal, during raising driving force, is applied to source wiring 14 with the state of the exportable electric current that will raise than the exportable electric current during after this period by amplifier 261.
In addition, in the present embodiment, in vertical blanking period, perform electric charge share, but, also can carry out the precharge pre-charge voltage (such as, common electric voltage VCOM) of regulation being applied to source wiring 14, replace electric charge to share.When carrying out precharge, in the structure shown in Fig. 7, the 4th switch being set, switching source wiring 14 state be connected with precharge potential and the state be not connected, to replace the 3rd switch 267.If control signal Cont1 becomes high level, then in buffer circuits 25,1st output switch 266 becomes open mode (the 2nd output switch 268 is also identical) (with reference to Fig. 7), and the 4th switch makes source wiring 14 become the state be connected with precharge potential.
In this case, the 1st output switch 266, the 2nd output switch 268 and the 4th switch are equivalent to source wiring initial setting section that each source wiring 14 is connected with regulation current potential.
As mentioned above, in the present embodiment, due to the driving force of source electrode driver 20 at least relative to the driving force during the single line initial in the driving of each frame, namely during driving more than during single line during reducing after which, in other words, due at least make the driving of each frame initial single line during driving force higher than the driving force during after which, therefore, it is possible to utilize simple structure to go forward side by side a step-down low-power consumption to prevent the deterioration of display quality.
Embodiment 2.
In the above-described embodiment, specified time limit after drive unit starts during showing (specifically, be baseline during more than during driving single line) in, control, make to drive source wiring 14 with the driving force 80% (being equivalent to higher driving force) such as shown in Fig. 6 (B), after specified time limit, control, make to drive source wiring 14 with the voltage signal (being equivalent to lower driving force) from D-A converter 24, but, also can control with higher driving force in specified time limit (baseline), during after specified time limit, carry out the control of the situation after specified time limit being different from embodiment 1.
In embodiment 2, during after specified time limit, in the front half-interval of each period regularly generated, drive source wiring 14 with higher driving force, but in rear half-interval, to drive source wiring 14 lower than the driving force of front half-interval.
In addition, for convenience of description, in the following description, during being set to each line of driving each period regularly generated (during each line).
Sequential chart with reference to Figure 10 and Figure 11 illustrates the action of the source electrode driver 20 of embodiment 2.The sequential chart that the sequential chart of Figure 11 amplifies during being the 1st line ~ 3rd line to each frame described in Figure 10.In addition, in Fig. 10, only during the 1st line, control signal Cont2 becomes the level of regulation, but, in the present embodiment, owing to utilizing control signal Cont2, to realize following control: namely, during after during the 1st line, with higher driving force, source wiring 14 is driven in front half-interval, with lower driving force, source wiring 14 is driven in rear half-interval, therefore, in fact, as shown in Figure 11, the level of regulation is also become during after during the 2nd line.
In addition, in Figure 10 and Figure 11, during being high level during the level showing control signal Cont2 becomes specified level, but as described below, actual being not limited to of the level of regulation is high level.In addition, illustrate as between low period during not becoming specified level, but actual being not limited to is low level.In addition, " change " described in Figure 11 means can set arbitrarily first half length of an interval degree.
The structure of source electrode driver 20 and gate drivers 30 is identical with the respective structure of the embodiment 1 shown in Fig. 1.The structure of amplifier 261 and outgoing side thereof is identical with the respective structure of the embodiment 1 shown in Fig. 5 and Fig. 7.The difference of the structure of the timing control circuit 40 of the embodiment 1 shown in the structure of timing control circuit 40 and Fig. 1 is, the output intent of the control signal during after following such 2nd line illustrated has part different, in addition then identical.In addition, use the example shown in Fig. 6 as the output state of the relation between the signal condition of control signal Cont2 and the output state of amplifier 261 and amplifier 261.
Below, stress two output buffers 251,252 (with reference to Fig. 5 and Fig. 7) of buffer circuits 25, but for the output buffer beyond two output buffers 251,252 of buffer circuits 25, also carry out identical action with output buffer 251,252.
Timing control circuit 40 as shown in Figure 10, is high level during making control signal Cont1 more than a horizontal period of vertical blanking period.According to the state of control signal Cont1, identical with the situation of embodiment 1, perform electric charge by the connection status setting output buffer 251,252 and share.
And, in the present embodiment, timing control circuit 40 also as shown in Figure 10, in specified time limit more than a horizontal period in each frame from the moment that the control shown for image starts, namely, drive in a frame in the specified time limit (during the 1st line) after starting, the level of control signal Cont2 is set to the level of regulation.In the present embodiment, the level of regulation is (H, L).
Thus, identical with the mode of embodiment 1, in the specified time limit that the level of control signal Cont2 becomes specified level, source wiring 14 is driven with the state of driving force 80%.
In embodiment 1, the level of control signal Cont2, at the end of specified time limit, is set to the level beyond specified level by timing control circuit 40.Specifically, the level of control signal Cont2 is set to (H, H).Thus, source wiring 14 is driven (with reference to Fig. 6) by the voltage signal from D-A converter 24.
That is, in embodiment 1, timing control circuit 40 controls, and during making after the 2nd line, can drive source wiring 14 in whole period with lower driving force.
But, in the present embodiment, in order in each period after the 2nd line, source wiring 14 is driven with higher driving force in front half-interval, but in rear half-interval, to drive source wiring 14 lower than the driving force of front half-interval, and the way of output of control signal Cont2 is made to be different from the situation of embodiment 1.
That is, as shown in figure 11, after the 2nd line, from drive each line after, in specified time limit (front half-interval), the level of control signal Cont2 is set to the level of regulation by timing control circuit 40.In the present embodiment, the level of regulation is (H, L) (with reference to Fig. 6 (A), (B)).In addition, if front half-interval is terminated, then the level of control signal Cont2 is set to (H, H).Thus, in rear half-interval, drive source wiring 14 (with reference to Fig. 6 (A), (B)) with lower driving force.
In the present embodiment, compared with embodiment 1, power consumption can be reduced on the basis of characteristic considering display panels 10.Namely, when because of the size of display panels 10 or pixel count larger etc. and application implementation mode 1, if generation current quantity not sufficient and the phenomenons such as display quality reduction, then by application present embodiment, thus compared with the situation of embodiment 1, can extend during carrying out driving with higher driving force, try hard to prevent the reduction of display quality, and make not drive with higher driving force during a whole frame, so that the increase of current sinking can be suppressed.
In addition, during after the 2nd line, the output level of control signal Cont2 is set to the level of regulation by timing control circuit 40, afterwards, change the period (being equivalent to the finish time of front half-interval) of removing the level exporting regulation, thus the length improving (that is, front half-interval) during driving force can be changed.Thus, can according to the size of display panels 10, pixel count equal, adjust first half length of an interval degree.That is, meticulous control can be realized, try hard to prevent reduction of display quality etc. and reduce current sinking.Such as, when in order to reduce current sinking and by raising driving force during too shorten, if display quality is lower than desired quality, then extend front half-interval.
As the structure realizing controlling adjustment first half length of an interval degree, as an example, the structure that control input terminal is set at timing control circuit 40 can be adopted.In this case, after the output level of control signal Cont2 is set to specified level by timing control circuit 40, the umber of pulse of clock signal is counted, basis is become to the kind of the signal of control input terminal input (specifically in count value, the kind of signal level) and determine in advance value time, remove export regulation level.In addition, when adopting this structure, timing control circuit 40 is utilized to realize the interval adjustment unit of adjustment first half length of an interval degree.
In addition, in the present embodiment, utilize control signal Cont2 to realize following control: namely, source wiring 14 is driven with higher driving force in front half-interval, in rear half-interval, drive source wiring 14 with lower driving force, but implementation method is not limited to the method using control signal Cont2.Such as, also can as shown in figure 12, timing control circuit 40 after the 2nd line during, utilize other the control signal Cont3 being different from control signal Cont2 to specify front half-interval or rear half-interval.
When using control signal Cont3, the level of control signal Cont3 in (front half-interval), is set to the level of regulation by timing control circuit 40 during regulation.In the present embodiment, the level of regulation is (H, L) (with reference to Fig. 6 (A), (B)).In addition, if front half-interval is terminated, then the level of control signal Cont3 is set to (H, H).Thus, in rear half-interval, drive source wiring 14 (with reference to Fig. 6 (A), (B)) with lower driving force.
In addition, also can after the 2nd line during, do not use control signal Cont2 or control signal Cont3, and buffer circuits 25 inputs the clock signal clk of such as data shifts, the rising edge of clock signal clk or the number of times of negative edge are counted, thus the finish time of first-half period can be determined independently.When adopting this structure, buffer circuits 25 also can be utilized to realize the interval adjustment unit of adjustment first half length of an interval degree.
In addition, in the present embodiment, in front half-interval, with Fig. 6 (B) the driving force 80% that represents of citing to drive source wiring 14, but also can with Fig. 6 (B) citing represent 100% or 130% driving force to drive source wiring 14.In addition, in the present embodiment, drive with the state of driving force 80% in front half-interval, in rear half-interval, to drive source wiring 14 from the voltage signal of D-A converter 24, but, also can by the driving force of rear half-interval higher than display during start after specified time limit (such as, during 1st line) and the driving force of front half-interval as condition, use driving force 80% and from the combination beyond the combination of the driving force of the voltage signal of D-A converter 24.
As an example, also in front half-interval, can drive with the state of driving force 130% or 100% (with reference to Fig. 6), in rear half-interval, drive with driving force 80%.
In addition, in the present embodiment, the driving force of the specified time limit (baseline) after starting during making display with after specified time limit during the driving force of front half-interval identical, but, also can make the driving force of driving force lower than baseline of front half-interval.In addition, when adopt utilize other control signal Cont3 of being different from control signal Cont2 to specify the structure of front half-interval or rear half-interval, more easily carry out making the driving force of front half-interval be different from the control of the driving force of baseline.
In addition, in the above description, display panels 10 also can be any one panel of black and white panel or color panel.
Application in industry
The present invention can be applied to the liquid crystal indicator being installed on portable set, mobile unit, video display apparatus etc.
Claims (7)
1. a drive unit for display panels,
Comprise source electrode driver, this source electrode driver utilizes row reversion to drive and drives the source wiring of display panels, the mode that the source wiring of described display panels intersects with many grid wirings and many source wiring is configured, and it is characterized in that
The driving force of the baseline of the source wiring that described source electrode driver is at least initial relative to the driving of each frame and after reducing the described baseline of each frame during the driving force of period at least partially,
Source electrode driver after baseline during, make compared with the driving force in the regulation interval before each period regularly generated, reduce the driving force in interval after regulation interval,
Source electrode driver comprises the interval adjustment unit adjusted regulation length of an interval degree above.
2. the drive unit of display panels as claimed in claim 1, is characterized in that,
Make the driving force of driving force lower than baseline in regulation interval above.
3. the drive unit of display panels as claimed in claim 1 or 2, is characterized in that,
Source electrode driver comprises outgoing route configuration part, this outgoing route configuration part is set as the voltage signal corresponding to data-signal being applied to the state of source wiring by amplifier or not being applied to any one state of state of described source wiring by described amplifier
Described outgoing route configuration part, when reducing driving force, is set as the state voltage signal corresponding to described data-signal not being applied to described source wiring by described amplifier,
When improving driving force, described outgoing route configuration part is set as corresponding to the voltage signal of described data-signal and to be applied to by described amplifier the state of described source wiring, and described amplifier makes exportable electric current rise to higher than the exportable electric current when voltage signal former state corresponding to described data-signal being outputted to described source wiring.
4. the drive unit of display panels as claimed in claim 1 or 2, is characterized in that,
Source electrode driver adopts following structure: namely, comprises the amplifier that can make exportable curent change,
The voltage signal corresponding to data-signal is applied to source wiring by described amplifier,
The voltage signal corresponding to described data-signal, when improving driving force, under the state making exportable electric current rise to higher than exportable electric current during reduction driving force, is applied to described source wiring by described amplifier.
5. the drive unit of display panels as claimed in claim 1 or 2, is characterized in that,
Source electrode driver comprises source wiring initial setting section, and this source wiring initial setting section, in vertical blanking period, makes adjacent source wiring short circuit or each source wiring is connected with regulation current potential.
6. the drive unit of display panels as claimed in claim 3, is characterized in that,
Source electrode driver comprises source wiring initial setting section, and this source wiring initial setting section, in vertical blanking period, makes adjacent source wiring short circuit or each source wiring is connected with regulation current potential.
7. the drive unit of display panels as claimed in claim 4, is characterized in that,
Source electrode driver comprises source wiring initial setting section, and this source wiring initial setting section, in vertical blanking period, makes adjacent source wiring short circuit or each source wiring is connected with regulation current potential.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010-264893 | 2010-11-29 | ||
| JP2010264893A JP2012008519A (en) | 2010-05-21 | 2010-11-29 | Driving device of liquid crystal display panel |
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| CN102479497A CN102479497A (en) | 2012-05-30 |
| CN102479497B true CN102479497B (en) | 2015-11-25 |
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| CN201110404726.8A Expired - Fee Related CN102479497B (en) | 2010-11-29 | 2011-11-28 | The drive unit of display panels |
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| EP (1) | EP2458581B1 (en) |
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| CN103474041B (en) * | 2013-09-12 | 2017-01-18 | 合肥京东方光电科技有限公司 | Driving device, driving method and display device for LCD panel |
| CN105099432B (en) * | 2014-05-19 | 2019-04-30 | 奇景光电股份有限公司 | Output buffer |
| US10498301B2 (en) * | 2018-04-27 | 2019-12-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Line drivers for wireline transmission devices |
| US10949597B2 (en) | 2018-07-16 | 2021-03-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Through-silicon vias in integrated circuit packaging |
| CN209015701U (en) * | 2018-10-25 | 2019-06-21 | 惠科股份有限公司 | The source voltage control circuit and display device of display panel |
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| KR20030084020A (en) * | 2002-04-24 | 2003-11-01 | 삼성전자주식회사 | Liquid crystal display and driving method thereof |
| JP4964461B2 (en) * | 2005-12-13 | 2012-06-27 | ティーピーオー、ホンコン、ホールディング、リミテッド | Display device and drive circuit for capacitive load thereof |
| JP4773928B2 (en) * | 2006-11-16 | 2011-09-14 | セイコーエプソン株式会社 | Source driver, electro-optical device and electronic apparatus |
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| EP2458581B1 (en) | 2017-02-15 |
| EP2458581A1 (en) | 2012-05-30 |
| CN102479497A (en) | 2012-05-30 |
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