CN105099432B - Output buffer - Google Patents

Output buffer Download PDF

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Publication number
CN105099432B
CN105099432B CN201410209889.4A CN201410209889A CN105099432B CN 105099432 B CN105099432 B CN 105099432B CN 201410209889 A CN201410209889 A CN 201410209889A CN 105099432 B CN105099432 B CN 105099432B
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CN
China
Prior art keywords
transistor
output buffer
coupled
gate pole
4th
Prior art date
Application number
CN201410209889.4A
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Chinese (zh)
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CN105099432A (en
Inventor
王家辉
黄宏裕
徐传健
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奇景光电股份有限公司
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Priority to CN201410209889.4A priority Critical patent/CN105099432B/en
Publication of CN105099432A publication Critical patent/CN105099432A/en
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Publication of CN105099432B publication Critical patent/CN105099432B/en

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Abstract

The present invention relates to a kind of output buffers, include amplification grade circuit, receive simulative display voltage to generate amplification display voltage;Driving stage circuit receives amplification display voltage to generate buffering display voltage, to drive a display panel;And switch, it is set between amplification grade circuit and driving stage circuit.When being in high output impedance state, switch is to disconnect, so that driving stage circuit and amplification grade circuit are electrically isolated from each other, when being in driving condition, switch is closure, so that driving stage circuit and amplification grade circuit electrical couplings each other.

Description

Output buffer

Technical field

The present invention relates to a kind of output buffers, especially with regard to a kind of output buffer of source electrode driver.

Background technique

When the resolution ratio of liquid crystal display panel is higher and higher, source electrode driver has the excessively high problem of temperature and generates.It makes When being that source electrode driver is in driving liquid crystal display panel at excessively high one of the reason of temperature, driving current can flow through source electrode drive Multiplexer in dynamic device.The heat resisting temperature range of general silicon processing procedure is about Celsius between 150~200 degree.When more than resistance to When hot temperature range, the exception of assembly function will cause.Therefore, how to reduce source electrode driver temperature become one it is important Circuit design subject under discussion.The method of the general temperature for reducing source electrode driver is to increase the size of multiplexer.However, such one Come, therefore the entire area of integrated circuit can become excessive.

Therefore it is badly in need of proposing a kind of novel framework, under the premise of not increasing circuit area, is able to that source electrode is effectively reduced The temperature of driver.

Summary of the invention

In view of above-mentioned, the technical problem to be solved in the present invention is that a kind of output buffer is proposed, when display panel is driven When dynamic, driving current does not flow through multiplexer, thus can reduce the bulk temperature and/or circuit face of source electrode driver Product.

According to embodiments of the present invention, output buffer includes amplification grade circuit, driving stage circuit and switch.Amplifying stage electricity Road receives simulative display voltage to generate amplification display voltage.Driving stage circuit receives amplification display voltage to generate buffering display Voltage, to drive display panel.Switch is set between amplification grade circuit and driving stage circuit.When in high output impedance shape When state, switch is to disconnect, so that driving stage circuit and amplification grade circuit are electrically isolated from each other;When being in driving condition, cut Parallel operation is closure, so that driving stage circuit and amplification grade circuit electrical couplings each other.

Detailed description of the invention

Fig. 1 shows the functional block diagram of the output buffer of the embodiment of the present invention.

Fig. 2 shows the circuit diagrams of the output buffer of Fig. 1.

The output buffer that Fig. 3 shows Fig. 2 is in high output impedance state.

The output buffer that Fig. 4 shows Fig. 2 is in driving condition.

Specific embodiment

Fig. 1 shows the functional block diagram of the output buffer 100 of the embodiment of the present invention, can be used to drive display panel 2 (such as liquid crystal display panel).In a specific example, the output buffer 100 of the present embodiment is set in source electrode driver 1, example Such as it is set to the output stage of source electrode driver 1.The input terminal of output buffer 100 can be received from digital analog converter (DAC) 110 Simulative display voltage, the output end of output buffer 100 then export buffering display voltage to display panel 2.

In the present embodiment, output buffer 100 is mainly comprising amplification grade circuit 11 and driving stage circuit 12, wherein amplifying Grade circuit 11 receives simulative display voltage from digital analog converter (DAC) 110, amplification display caused by amplification grade circuit 11 Voltage is then fed to driving stage circuit 12, and buffering display voltage is then to drive display panel 2 caused by driving stage circuit 12. The output buffer 100 of the present embodiment also includes switch SW, is set between amplification grade circuit 11 and driving stage circuit 12, when defeated Buffer 100 is in high output impedance state out, switch SW be disconnect so that driving stage circuit 12 and amplification grade circuit 11 that This is electrically isolated.When output buffer 100 is in driving condition, switch SW is closure, so that driving stage circuit 12 and amplification Grade circuit 11 electrical couplings each other.It is flowed through when output buffer 100 is in driving condition according to one of the feature of the present embodiment The high current of driving stage circuit 12 and without multiplexer is also without the use of big ruler so not will cause the rising of temperature Very little multiplexer.

Fig. 2 shows the circuit diagrams of the output buffer 100 of Fig. 1.Output buffer 100 shown in Fig. 2 uses differential (differential) circuit framework, however the present invention is not limited to such frameworks.As shown in Fig. 2, output buffer 100 wraps 100A containing positive polarity output buffer and negative polarity output buffer 100B.In details of the words, positive polarity output buffer 100A packet 11A containing amplification grade circuit and driving stage circuit 12A, wherein amplification grade circuit 11A includes differential operational amplifier HVOP, is had Positive input terminal (+) and negative input end (-), wherein positive input terminal (+) receives simulative display from digital analog converter (DAC) 110 Voltage Vin1.Amplification grade circuit 11A also includes the first transistor M1 and second transistor M2 being serially connected between power supply and ground.? In the present embodiment, the first transistor M1 can be P type metal oxide semiconductor (PMOS) transistor, and second transistor M2 can be N The drain electrode of type metal oxide semiconductor (NMOS) transistor, the first transistor M1 and second transistor M2 are connected to intermediate node A, and it is coupled to the negative input end (-) of differential operational amplifier HVOP, and the gate pole of the first transistor M1 and second transistor M2 It is respectively coupled to the positive and negative output end of differential operational amplifier HVOP.It can also be coupled between the gate pole of the first transistor M1, drain electrode There is first capacitor device CA, and can also be coupled with the second capacitor CB between the gate pole of second transistor M2, drain electrode.

The driving stage circuit 12A of the present embodiment includes the third transistor M3 and the 4th crystal being serially connected between power supply and ground Pipe M4.In the present embodiment, third transistor M3 can be P type metal oxide semiconductor (PMOS) transistor, the 4th transistor M4 can be N-type metal-oxide semiconductor (MOS) (NMOS) transistor, and third transistor M3 and the drain electrode of the 4th transistor M4 are connected to Output node B, and intermediate node A is coupled to (alternatively, the negative input of differential operational amplifier HVOP via first switch SW1 It holds (-)).The gate pole of third transistor M3 select to be coupled to via first selector SEL1 the first transistor M1 gate pole (or Person, the positive output end of differential operational amplifier HVOP) or select to be coupled to power supply.The gate pole of 4th transistor M4 is via the second choosing It selects device SEL2 and selects the gate pole (alternatively, negative output terminal of differential operational amplifier HVOP) for being coupled to second transistor M2 or choosing It selects and is coupled to ground.Third transistor M3, the 4th transistor M4 size of components generally than the first transistor M1, second transistor M2 Size of components it is bigger, so that biggish driving current is able to flow through third transistor M3, the 4th transistor M4.

The circuit composition of negative polarity output buffer 100B is identical to positive polarity output buffer 100A.In details of the words, it bears Polarity output buffer 100B includes amplification grade circuit 11B and driving stage circuit 12B, wherein amplification grade circuit 11B includes differential Operational amplifier LVOP has positive input terminal (+) and negative input end (-), and wherein positive input terminal (+) is from digital analog converter (DAC) 110 simulative display voltage Vin2 is received.Amplification grade circuit 11B also includes the first crystal being serially connected between power supply and ground Pipe M1 and second transistor M2.In the present embodiment, the first transistor M1 can be P type metal oxide semiconductor (PMOS) crystal Pipe, second transistor M2 can be N-type metal-oxide semiconductor (MOS) (NMOS) transistor, the first transistor M1 and second transistor M2 Drain electrode be connected to intermediate node A, and be coupled to the negative input end (-) of differential operational amplifier LVOP, and the first transistor M1 The positive and negative output end of differential operational amplifier LVOP is respectively coupled to the gate pole of second transistor M2.The first transistor M1's It can also be coupled with first capacitor device CA between gate pole, drain electrode, and can also be coupled between the gate pole of second transistor M2, drain electrode Two capacitor CB.

The driving stage circuit 12B of the present embodiment includes the third transistor M3 and the 4th crystal being serially connected between power supply and ground Pipe M4.In the present embodiment, third transistor M3 can be P type metal oxide semiconductor (PMOS) transistor, the 4th transistor M4 can be N-type metal-oxide semiconductor (MOS) (NMOS) transistor, and third transistor M3 and the drain electrode of the 4th transistor M4 are connected to Output node B, and intermediate node A is coupled to (alternatively, the negative input of differential operational amplifier HVOP via first switch SW1 It holds (-)).The gate pole of third transistor M3 select to be coupled to via first selector SEL1 the first transistor M1 gate pole (or Person, the positive output end of differential operational amplifier HVOP) or select to be coupled to power supply.The gate pole of 4th transistor M4 is via the second choosing It selects device SEL2 and selects the gate pole (alternatively, negative output terminal of differential operational amplifier HVOP) for being coupled to second transistor M2 or choosing It selects and is coupled to ground.Third transistor M3, the 4th transistor M4 size of components generally than the first transistor M1, second transistor M2 Size of components it is bigger, so that biggish driving current is able to flow through third transistor M3, the 4th transistor M4.In addition, this reality The driving stage circuit 12 of example is applied also comprising second switch SW2, both ends are respectively coupled to the output section of driving stage circuit 12A, 12B Point B.

According to Fig. 1 and output buffer 100 shown in Fig. 2, the present embodiment can sequentially operate on state below.Fig. 3 shows The output buffer 100 for having gone out Fig. 2 is in high output impedance state, at this point, positive polarity output buffer 100A and negative polarity are defeated The first switch SW1 of buffer 100B, first selector SEL1 and second selector SEL2 are all to disconnect out, so that driving stage is electric Road 12 and amplification grade circuit 11 are electrically isolated from each other.Under high output impedance state, simulative display voltage Vin1, Vin2 respectively by Differential operational amplifier HVOP, LVOP are amplified, and store charge in node A.At the same time, second switch SW2 is closure, Charge share (charge sharing) is carried out with sharp display panel 2.At the end of high output impedance state, then enter driving shape State.

The output buffer 100 that Fig. 4 shows Fig. 2 is in driving condition.At this point, positive polarity output buffer 100A and negative First switch SW1, first selector SEL1 and the second selector SEL2 of polarity output buffer 100B is all closure, and second Switch SW2 is then disconnection.Under driving condition, the driving of positive polarity output buffer 100A and negative polarity output buffer 100B Grade circuit 12A, 12B drive display panel 2.Driving current compared to traditional output buffer can pass through multiplexer, because And cause the rising of temperature;Review the present embodiment in driving when high current and without multiplexer, so not will cause The rising of temperature is also without the use of large-sized multiplexer.In addition, the driving current of traditional output buffer can also pass through First switch SW1, it is therefore desirable to use biggish switch;Review the driving current of the present embodiment and without first switch SW1, Therefore it only needs using general switch.

The foregoing is only a preferred embodiment of the present invention, the claim being not intended to limit the invention; It is all other without departing from the lower equivalent change or modification completed of revealed spirit is invented, it is special to should be included in application of the invention In sharp range.

Reference signs list

1 source electrode driver

11 amplification grade circuits

11A amplification grade circuit

11B amplification grade circuit

12 driving stage circuits

12A driving stage circuit

12B driving stage circuit

100 output buffers

100A positive polarity output buffer

100B negative polarity output buffer

110 digital analog converters

2 display panels

HVOP differential operational amplifier

LVOP differential operational amplifier

A intermediate node

B output node

M1 the first transistor

M2 second transistor

M3 third transistor

The 4th transistor of M4

CA first capacitor device

The second capacitor of CB

SW switch

SW1 first switch

SW2 second switch

SEL1 first selector

SEL2 second selector

Vin1~Vin2 simulative display voltage

Claims (9)

1. a kind of output buffer, includes:
One amplification grade circuit receives simulative display voltage to generate amplification display voltage;
One driving stage circuit receives the amplification and shows voltage to generate buffering display voltage, to drive a display panel;And
One switch is set between the amplification grade circuit and the driving stage circuit, when being in high output impedance state, the switching Device is disconnection, so that the driving stage circuit and the amplification grade circuit are electrically isolated from each other, when being in driving condition, the switch For closure, so that the driving stage circuit and the amplification grade circuit electrical couplings each other;
Wherein, which includes a first transistor and a second transistor, which includes that a third is brilliant Body pipe and one the 4th transistor, the first transistor and the second transistor are connected to intermediate node, the third transistor with should 4th transistor is connected to output node, which includes a first selector and a second selector and be connected in this A first switch between intermediate node and the output node, when being in driving condition, the gate pole of the third transistor is via this First selector is coupled to the gate pole of the first transistor, and the gate pole of the 4th transistor is coupled to this via the second selector The gate pole of second transistor, first switch closure, driving current is without the first switch.
2. output buffer according to claim 1, wherein the amplification grade circuit also includes a differential operational amplifier, In an input terminal receive the simulative display voltage;
Wherein the first transistor and the second transistor are serially connected between power supply and ground, which is coupled to the differential fortune Calculate another input terminal of amplifier.
3. output buffer according to claim 2, wherein the first transistor is P type metal oxide semiconductor (PMOS) transistor, the second transistor are N-type metal-oxide semiconductor (MOS) (NMOS) transistor, the first transistor and this The drain electrode of two-transistor is connected to the intermediate node, and is coupled to the negative input end of the differential operational amplifier, the differential operational The positive input terminal of amplifier receives the simulative display voltage, and the gate pole of the first transistor and the second transistor is respectively coupled to To the positive and negative output end of the differential operational amplifier.
4. output buffer according to claim 2, wherein the amplification grade circuit further includes:
One first capacitor device is coupled between the gate pole of the first transistor, drain electrode;And
One second capacitor is coupled between the gate pole of the second transistor, drain electrode.
5. output buffer according to claim 2, wherein the third transistor and the 4th strings of transistors are connected to power supply Between ground, which shows voltage to export the buffering.
6. output buffer according to claim 5, wherein the third transistor is P type metal oxide semiconductor (PMOS) transistor, the 4th transistor be N-type metal-oxide semiconductor (MOS) (NMOS) transistor, and the third transistor with should The drain electrode of 4th transistor is connected to the output node.
7. output buffer according to claim 5, wherein the switch includes:
The first selector, to select to couple the third transistor to one of power supply or the first transistor;And
The second selector, to select to couple the 4th transistor to one of ground or the second transistor.
8. output buffer according to claim 7, wherein the first transistor, third transistor are the oxidation of p-type metal Object semiconductor (PMOS) transistor, the second transistor, the 4th transistor are N-type metal-oxide semiconductor (MOS) (NMOS) crystal Pipe, the gate pole of the third transistor select the gate pole for being coupled to the first transistor or selection coupling via the first selector Gate pole to power supply, and the 4th transistor selects the gate pole for being coupled to the second transistor or choosing via the second selector It selects and is coupled to ground.
9. output buffer according to claim 5, wherein the third transistor, the size of components of the 4th transistor are greater than The size of components of the first transistor, second transistor.
CN201410209889.4A 2014-05-19 2014-05-19 Output buffer CN105099432B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410209889.4A CN105099432B (en) 2014-05-19 2014-05-19 Output buffer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410209889.4A CN105099432B (en) 2014-05-19 2014-05-19 Output buffer

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CN105099432A CN105099432A (en) 2015-11-25
CN105099432B true CN105099432B (en) 2019-04-30

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TW201233064A (en) * 2010-11-29 2012-08-01 Realtek Semiconductor Corp Reference voltage buffer and method thereof
CN102779481A (en) * 2012-08-27 2012-11-14 友达光电股份有限公司 Drive circuit for OLED (Organic Light Emitting Diode) panel
CN103066987A (en) * 2011-10-24 2013-04-24 三星电子株式会社 Output driver, integrated circuit, and system

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KR100699829B1 (en) * 2004-12-09 2007-03-27 삼성전자주식회사 Output buffer of source driver in liquid crystal display device having high slew rate and method for controlling the output buffer
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089723A (en) * 1990-11-15 1992-02-18 National Semiconductor Corporation CMOS-based pseudo ECL output buffer
CN1648984A (en) * 2004-01-27 2005-08-03 恩益禧电子股份有限公司 Drive voltage generator circuit for driving LCD panel
CN101089937A (en) * 2006-06-15 2007-12-19 晶门科技有限公司 Source drive amplifier for flat panel display
CN101132174A (en) * 2006-08-24 2008-02-27 索尼株式会社 Drive circuit
CN101453207A (en) * 2007-12-06 2009-06-10 奇景光电股份有限公司 Operational amplifier
JP2009253524A (en) * 2008-04-03 2009-10-29 Asahi Kasei Electronics Co Ltd Output buffer circuit
CN101588172A (en) * 2008-05-20 2009-11-25 联发科技股份有限公司 Reference buffer circuit
CN101656534A (en) * 2008-08-20 2010-02-24 旭曜科技股份有限公司 Output-stage circuit and operational amplifier
CN101674071A (en) * 2008-09-11 2010-03-17 上海华虹Nec电子有限公司 Physical layer interface circuit
TW201013615A (en) * 2008-09-30 2010-04-01 Himax Tech Ltd Output buffer and source driver using the same
TW201039313A (en) * 2009-04-30 2010-11-01 Himax Tech Ltd Source driver with low power consumption and driving method thereof
CN102054450A (en) * 2009-10-27 2011-05-11 硅工厂股份有限公司 Liquid crystal display panel driving circuit
TW201128948A (en) * 2010-02-04 2011-08-16 Novatek Microelectronics Corp Output buffer circuit capable of enhancing stability
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CN102479497A (en) * 2010-11-29 2012-05-30 奥博特瑞克斯株式会社 Drive device for liquid crystal display panel
TW201233064A (en) * 2010-11-29 2012-08-01 Realtek Semiconductor Corp Reference voltage buffer and method thereof
CN103066987A (en) * 2011-10-24 2013-04-24 三星电子株式会社 Output driver, integrated circuit, and system
CN102779481A (en) * 2012-08-27 2012-11-14 友达光电股份有限公司 Drive circuit for OLED (Organic Light Emitting Diode) panel

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