CN102468181A - Vertical transistor having buried junction and method for manufacturing the same - Google Patents

Vertical transistor having buried junction and method for manufacturing the same Download PDF

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Publication number
CN102468181A
CN102468181A CN201110349400XA CN201110349400A CN102468181A CN 102468181 A CN102468181 A CN 102468181A CN 201110349400X A CN201110349400X A CN 201110349400XA CN 201110349400 A CN201110349400 A CN 201110349400A CN 102468181 A CN102468181 A CN 102468181A
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layer
impurity
wall body
lining
impurity layer
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CN102468181B (en
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朴恩实
殷庸硕
卢俓奉
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SK Hynix Inc
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Hynix Semiconductor Inc
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Abstract

The present invention discloses a vertical transistor having a buried junction and a method for manufacturing the same. The method comprises the steps of: forming a trench in a semiconductor substrate to form first and second wall bodies, wherein the trench has sidewalls comprising a first side surface of the second wall body and a second side surface of the first wall body; forming a one side contact mask having an opening that selectively exposes a portion of only the first side surface of the second wall body; and forming a first impurity layer and a second impurity layer surrounding the first impurity layer in the second wall body by diffusing impurities having different diffusivities into the second wall body through the exposed portion of the first side surface.

Description

Vertical transistor and manufacturing approach thereof with flush type knot
Technical field
Example embodiment of the present invention relates to semiconductor device, especially relates to the vertical transistor and the manufacturing approach thereof that have the flush type knot through mixing and doping.
Background technology
Along with the integrated level increase of semiconductor device, and add a large amount of being integrated in the limited substrate area of good general like transistorized cell arrangement.Have the MOSFET device of planar structure and the knot that planar ransistor comprises the either side that is positioned at the transistor gate on the substrate surface, form horizontal channel thus.For integrated a large amount of transistor in the limited area of substrate, just need reduce each transistorized channel length.
Yet, reduce transistor channel length in the horizontal direction and can run into many due to leakage current, short-channel effect, and the opposite difficulty that physical restriction caused of conducting electric current minimizing etc.The ability of reduced plan structure is near its limit in the horizontal direction.Therefore, a kind of vertical transistor structures has been proposed.The active area that this structure is used is projection vertically, and different with the situation of the planar structure of projection flatly.
In vertical transistor structures, should several knots be formed on top and the below of being located at the raceway groove on the vertical direction.Yet, because the geometrical factor relevant with transistorized vertical stratification forms flush type and has technical difficulty below raceway groove.Flush type knot with and the channel region of overlapping vertical gate between the formation position that can tie according to flush type on the vertical direction of distance and the diffusion depth of knot change.The last change of this distance possibly influence the threshold voltage vt of raceway groove.When the diffusion depth of tying was not enough, the distance between raceway groove and the flush type knot possibly increase, and increases the threshold voltage vt of raceway groove thus.Therefore, knot need be controlled with respect to the position of channel region and the diffusion profile of knot accurately.Moreover when the concentration of dopant of knot was hanged down, the contact resistance of the cross tie part of contact knot possibly increase.
Summary of the invention
In one embodiment, a kind of method of making the knot of vertical transistor comprises: in semiconductor substrate, form groove, form first wall body and second wall body thus.Groove has the sidewall of second side of several first sides that comprise second wall body and first wall body.Can form the one-sided contact mask with opening, opening optionally only exposes the part of first side of second wall body.Diffusion of impurities to the first side that can be through will having different diffusivitys by the part that opening exposed, form first impurity layer and form second impurity layer at second wall body around first impurity layer.
In another embodiment, a kind of method that forms the knot of vertical transistor comprises: form first wall body and second wall body from semiconductor substrate, wherein each wall body has second side on first side and opposite.First impurity layer and the second also low impurity layer of concentration ratio first impurity layer are formed on wall body first side a part and make second impurity layer around first impurity layer.
In another embodiment, a kind of method of making vertical transistor comprises: first wall body and second wall body that form vertical protuberance from semiconductor substrate.Each wall body has second side on first side and opposite, and wherein first wall body and second wall body are by first groove separately.Formation has the one-sided contact mask of opening, and opening optionally exposes the part of first side of second wall body.First impurity through will having different diffusivitys and second diffusion of impurities to the first side by the part that opening exposed, form and comprise first impurity layer and around the flush type knot of second impurity layer of first impurity layer.Embedded type bit line is formed between the wall body, wherein embedded type bit line electrical couplings to flush type is tied via the opening of one-sided contact mask.
In another embodiment, a kind of vertical transistor comprises: a plurality of second sides that have first side and opposite from active post and each active post of semiconductor substrate projection.Embodiment also can have one-sided contact mask, and one-sided contact mask has opening, and opening optionally exposes the bottom of first side of active post.Flush type in vertical transistor knot can comprise first impurity layer and around second impurity layer of first impurity layer, and wherein the part by opening exposed of first impurity and second impurity layer diffusion of impurities to the first side through will having different diffusivitys forms.The embedded type bit line that is embedded between the active post can see through the opening of one-sided contact mask and contact the flush type knot.
Impurity can comprise arsenic (As) and phosphorus (P), can first impurity layer be formed to comprise As, and can second impurity layer be formed and comprise P, and wherein As can be different with the diffusivity of P.
Description of drawings
In conjunction with accompanying drawing, more than will become clearer by following detailed description with other aspects, characteristic and advantage, in the accompanying drawings:
Fig. 1 to 16 illustrates the vertical transistor with flush type knot of embodiments of the invention and the figure of manufacturing approach thereof;
The figure of the vertical transistor with flush type knot of Figure 17 to 19 explanation embodiments of the invention and the effect of manufacturing approach thereof;
Figure 20 to 26 illustrates the figure with the modification of the method for the vertical transistor with flush type knot of making embodiments of the invention; And
Figure 27 illustrates the figure that uses metal level to form bit line.
Embodiment
Embodiments of the present invention will be described by referring to the drawings.Yet the purpose of embodiment just is used for explanation but not is used to limit scope of the present invention.
With reference to Fig. 1, etching mask 200 is formed on the semiconductor substrate 100 like silicon substrate.Under the situation of DRAM device, can etching mask 200 be formed the wire of on bit line direction, extending.Can in the etch process that is used to form first groove 110 that defines several active areas 101, use etching mask 200.Etching mask 200 can comprise insulating material, for example the silicon in the semiconductor substrate 100 is had the silicon nitride (Si of etching selectivity 3N 4).
With reference to Fig. 2, with the optionally etching and on the either side of first groove 110, form first groove 110 that has several wall bodies 111 of the part of being exposed by first mask pattern 200 of semiconductor substrate 100.Each wall body 111 can include source region 101 and first side 113 and second side 115.The wall body 111 that includes source region 101 with the direction of the Surface Vertical of substrate 100 on.
Form first lining 310 with the side 113 that covers several wall bodies 111 and the bottom surface of 115 and first groove 110.Import first lining 310 in groove 110, to form one-sided contact mask, this one-sided contact mask is optionally opened the bottom of first side 113 in subsequent technique.When forming the memory cell of DRAM device when importing; The vertical transistor of embodiments of the invention is configured to comprise: the grid on the side of active area 101, be located at below the active area 101 the flush type knot (for example; Drain electrode), knot (for example, source electrode) and on the correspondence of the upper end of active area 101.Can the flush type knot is arranged to contact with embedded type bit line (not being shown in Fig. 2) and be coupled, this embedded type bit line be embedded in the bottom of first groove 110.See through one-sided contact and be connected to embedded type bit line, this one-sided contact only contacts with the flush type knot at 113 places, first side.In order to realize this one-sided contact, need only on the part of first side 113, to have the one-sided contact mask of opening.
Deposition capable of using or thermal oxidation be silica (SiO for example 2) layer form first lining 310.First lining 310 can be used as the layer of active area 101 with embedded type bit line isolation and insulation usefulness, and this embedded type bit line forms the bottom of inserting first groove 110.Buried horizon 330 is formed first groove 110 of inserting first lining, 310 tops.Deposition capable of using for example forms buried horizon 330 to the material layer that first lining 310 has a polysilicon layer of etching selectivity.
With reference to Fig. 3, implement first recess process and make buried horizon 330 depression and make the buried horizon of depression be positioned at the bottom of first groove 110.Implement first recess process so that the upper surface of the buried horizon 331 of depression is positioned at apart from first depth D, 1 place, first groove, 110 bottoms.Can change first depth D 1 according to the layout (placement) of the flush type knot that will be formed on active area 101 (for example, drain electrode).When utilizing first recess process to make buried horizon 330 depressions, also can make first lining, 310 depressions.Therefore because buried horizon 330 possibly have etching selectivity to first lining 310, possibly need to implement the part of exposing by first recess process that other technology is come optionally etching first lining 310.In view of the above, the not part 311 of depression of first lining is retained between the buried horizon 331 and active area 101 of depression.
With reference to Fig. 4, second lining 350 is formed on the sidewall 113 and 115 of the active area 101 that is exposed through several parts depressions that make first lining 310.Each second lining 350 is formed on the sidewall (113 or 115) of active area 101 so that the end is connected to the end of the first corresponding lining 311.Can through the material of deposition second lining 350 be formed sept shape (spacer shape) through anisotropic etching then through depositing the material that first lining 311 is had the for example silicon nitride of etching selectivity.The anisotropic etching that is used to form the sept shape of second lining 350 can partly expose buried horizon 331, and is as shown in Figure 5.The sept shape can refer to be separated two surfaces at an interval.
With reference to Fig. 5, utilize second recess process, make the buried horizon 331 that in first groove 110, has first depth D 1 as shown in Figure 4 further be recessed to second depth D 2.Can this buried horizon that further caves in be called buried horizon 332.In view of the above, because of make buried horizon 331 further the depression part G that forms first lining 311 that buried horizon 332 causes in first groove 110, expose.The part G that exposes of first lining 311 can be changed and corresponding to will be in follow-up technology the coverlet lateral erosion carve (one-side etched) part to expose the part that is used to form flush type knot (for example, drain electrode) of active area 101.Therefore, can consider that the width of the knot corresponding with the drain electrode of vertical transistor sets the part G that exposes of first lining 311.First lining 311, second lining 350, and buried horizon 332 as mask, utilize this mask to be set with the part of the formation flush type knot in source region 101.That is, mask comprises: be coated with first lining 311 of a part of the lower wall in source region 101, as first; To the buried horizon 332 of second depth D 2, as second portion; And be coated with second lining 350 of the upper side wall that is not covered by first in source region 101, as third part.
With reference to Fig. 6, form the 3rd lining 370 to cover the part G that exposes of second lining 350 and first lining 311.Import the 3rd lining 370 so as the first side wall that faces with each other 113 in the etched trench 110 and second sidewall 115 one of them.Can this be called " one-sided etching " (one-side etching) and can be used for after a while optionally the part G that exposes of first lining 311 is exposed.If the first side wall 113 is carved the coverlet lateral erosion; Then second lining 350 need be retained as being coated with the mask of second sidewall 115 in source region 101, and can use the material that second lining 350 is had a for example titanium nitride (TiN) of etching selectivity to form the 3rd lining 370.But the depositing TiN layer is also given anisotropic etching and the 3rd lining 370 is formed the sept shape.Anisotropic etching can be implemented so that expose the upper surface of buried horizon 332.
Then, form sacrifice layer 390 and insert first groove 110 to cover the 3rd lining 370 and buried horizon 332.Sacrifice layer 390 is as the mask that is used for one-sided etch process, in this one-sided etch process, has only the part of one of the 3rd lining 370 on the sidewall 113 and 115 in first groove 110 to be selected and etching.That is, sacrifice layer 390 is as being used to prevent non-selected the 3rd lining 370 etched masks.Therefore, deposition capable of using has the for example silica (SiO of etching selectivity to the 3rd lining 370 2) material form sacrifice layer 390, and then the material of deposition is eat-back or polishes.The polishing of the material that chemico-mechanical polishing capable of using (CMP) technology is implemented to deposit.Be utilized in and implement CMP technology on the sacrifice layer 390, can the upper surface of etching mask 200 be exposed.
With reference to Fig. 7, make sacrifice layer 390 and the 3rd lining 370 be recessed to desired depth, form second groove 117 thus.Therefore, in second groove 117, has only second lining 350 on each sidewall 113 or 115.On the bottom of second groove 117, have only the upper surface of sacrifice layer 390 of upper surface and depression of the 3rd lining 370 of depression to be exposed.
With reference to Fig. 8, the etch stop layer 400 that will have first 401 and second portion 402 is formed on second groove 117.First 401 comprises first bight 411, and second portion 402 comprises second bight 412.Use etch stop layer 400 to be formed for one-sided contact mask patterned etch is stopped, this one-sided contact mask is selected and is exposed bight 411 and one of them of 412 in second groove 117.Deposition capable of using for example polysilicon layer forms such etch stop layer 400.
After forming etch stop layer 400, implement angle-tilt ion and inject 410 foreign ion is injected the second portion with second bight 412 402 of etch stop layer 400.With the inclination angle (for example; To the tilt inclination angle of 10 and 20 degree of the directions vertical with semiconductor substrate 100) mode of injecting twice foreign ion implements angle-tilt ion and injects 410; Because this inclination angle; Foreign ion can not be injected into the first 401 of etch stop layer; The first 401 of this etch stop layer receives shadow effect (shadow effect) protection that is caused by wall body 111 and etching mask 200, but foreign ion optionally only is injected into the second portion 402 of the shadow effect protection that does not receive wall body 111.Foreign ion can be the for example material of boron (B), arsenic (As) or phosphorus (P).
Because foreign ion is injected the second portion 402 of the etch stop layer 400 that is formed by polysilicon by part, so the etch-rate of the comparable first 401 that does not have a foreign ion injection of the etch-rate of second portion 402 (etch rate) is low.See through ion injection, can increase the etching selectivity between first and the second portion like the impurity of boron (B).In view of the above, can in same polysilicon layer, optionally form the part that several have different etching selectivities.The foreign ion of different types of foreign ion of injection capable of using or different amounts comes relatively to increase the etch-rate of the part that is injected into foreign ion, and can be in follow-up technology these parts of etching optionally.In an embodiment of the present invention, injection B capable of using comes relatively to reduce the etch-rate of second portion 402, and the part of injecting B can be remained at follow-up etch process.
With reference to Fig. 9, with etch stop layer 400 optionally etching optionally to remove first 401, the unadulterated polysilicon layer that this first 401 is not injected into for foreign ion.In view of the above, have only the second portion 402 of etch stop layer 400 to remain.From at this time beginning, also can second portion 402 be called etch 402.Use capable of using comprises for example ammonia and/or oxyammonia (NH 4The wet etch process of wet etchant OH) is implemented etch process.Etching rate difference between the first 401 of the foreign ion that the second portion 402 of the foreign ion that has an injection capable of using and not having injects comes optionally to remove first 401, stays the etch of optionally first bight 411 of second groove 117 being exposed 402 thus.
Use etch 402 as etching mask, with the optionally etching and removing of the exposed portions serve of the 3rd lining 370.Etch 402 is optionally only exposed the 3rd lining 370 at 113 places, first side of wall body 111, and the 3rd lining 370 is covered at 115 places, second side of side over there.Therefore, only carve in the 3rd lining 370 coverlet lateral erosion of first side 113.In view of the above, in second groove 117, form open circuit (open path) 371, and the part G of first lining 311 is exposed to the bottom of open circuit 371.
With reference to Figure 10, the exposed portions serve G that removes first lining 311 is to form opening 410, and this opening 410 exposes the part that will form the flush type knot of active area 101.Etch process capable of using sees through the technology that open circuit 371 implements to remove the part G that exposes of first lining 311.Yet because sacrifice layer 390 can be by forming (Fig. 9) with first lining, 311 essence identical materials (for example, silica), therefore the part G that exposes of first lining 311 can be etched and remove together with sacrifice layer 390.In view of the above, mode forms opening 410 so that open the part that will form the flush type knot of active area 101 according to this.
With reference to Figure 11, will the 3rd lining 370 (Figure 10) that sacrifice layer 390 (Fig. 9) has etching selectivity thereby when removing sacrifice layer 390, can be retained in opposite side wall optionally be removed, and expose second lining 350.(Figure 10) optionally removes with buried horizon 332.The one-sided contact mask that in view of the above, will have an opening 410 is formed on first side 113.Opening 410 is positioned at the bottom of the active area 101 of wall body 111, and in the position of considering to form embedded type bit line, the distance of being scheduled to the bottom interval one of first groove 110.
Referring to figs. 1 through 11,, the single side face of wall body 111 forms one-sided contact mask as above-mentioned so that having the mode of the opening 410 of a part of exposing first side 113.Then, the flush type knot with the drain electrode that is used as vertical transistor sees through opening 410 formation.When forming one-sided contact mask, can use etching mask as shown in Figure 9 402 to implement angle-tilt ion according to embodiments of the invention and inject.Yet be not limited thereto, can use the opening 410 that various additive methods form a part of exposing first side 113 shown in figure 11.Utilize impurity to form the flush type knot, and in order to reduce the contact resistance that contacts with the flush type knot of embedded type bit line, high-dopant concentration possibly expected.Yet flush type knot must have a kind of diffusion profile: the flush type knot is diffused to can make the flush type knot be suitable as the degree of depth (or distance) of drain electrode work.Tie the required diffusion profile and the impurity concentration of expectation in order to ensure flush type, several have the method for the impurity of different diffusivitys to carry out doping.
With reference to Figure 12, the opening 410 that the impurity that will have different diffusivitys sees through one-sided contact mask diffuses to the part of exposing of first side 113 of wall body 111, forms thus to comprise first impurity layer and around the flush type knot of second impurity layer of first impurity layer.When several had the impurity of different diffusivitys when doping, several impurity can be flooded to the degree of depth different in the active area 101 or distance according to the grade of diffusivity.Therefore, capable of using through diffusion have low relatively diffusivity formed first impurity layer of impurity, and realize the flush type knot through formed second impurity layer that can spread deeplyer of impurity that diffusion has a high relatively diffusivity.
Capable of usingly form first impurity layer, and capable of usingly form second impurity layer with low relatively doped in concentrations profiled second impurity (for example, phosphorus (P)) with high relatively doped in concentrations profiled first impurity (for example, arsenic (As)).When mode according to this forms the flush type knot and when comprising first impurity layer and second impurity layer of the different impurities with different diffusivitys, can see through opening 410 with the contact interface place formation ohmic contact between the embedded type bit line that is formed and the flush type knot.Therefore, can realize the minimizing of contact resistance.Moreover, when utilizing when P being diffused to the darker degree of depth and forms second impurity layer, can realize the diffusion depth of expecting with low concentration.In view of the above, the degree of depth of expectation can be the diffusion profile of flush type knot extended to, and high value can be the impurity concentration of the contact portion between flush type knot and embedded type bit line be maintained.
The method of utilizing several impurity with different diffusivitys that mix to form first impurity layer and second impurity layer can comprise following technology: import doped dielectric layer 500; With doping impurity to doped dielectric layer 500; And see through heat treatment with diffusion of impurities.For example, the deposit spathic silicon layer is to insert first groove 110.Phosphine (PH is provided together 3) and be used for silicon source gas (for example, the silane (SiH of polysilicon layer 4)) and dopant deposition has the polysilicon layer of P.Under 400 ℃ to 600 ℃ temperature ranges, 0.3 to 2Torr deposit cavity pressure conditions, implement deposition.
Utilize top that dry-etching is etched back to opening 410 with the polysilicon layer of deposition to form doped dielectric layer 500, it sees through the surface of exposing of opening 410 contacts first side 113.After forming the doped dielectric layer 500 of doping P, As is used as first impurity injects doped dielectric layer 500 as second impurity.Consider that ion injects the penetration depth (penetration depth) of As, can eat-back polysilicon layer in such a way: the As of ion implanted polysilicon layer is in the concentration at the height place that equates with opening 410 convergence maximum haply.The ion that sees through As injects, and P and As are entrained in the doped dielectric layer 500 together.
Because P has high relatively diffusivity, so the diffusion depth of P maybe be deeply to the degree of not expecting.In order to prevent that P from being spread too deeply, capable of using carbon (C) is doped into the diffusivity that doped dielectric layer 500 is controlled P.Therefore, C is penetrable or diffuse to the position that P will spread or penetrate in silicon (Si) the crystal structure inside, hinders the diffusion of P thus.In view of the above, the diffusivity of may command P or diffusion length.Ion capable of using injects C is injected into doped dielectric layer 500.
With reference to Figure 13, implement heat treatment, make that P and the As in doped dielectric layer 500 sees through the active area 101 that opening 410 diffuses to 113 inside, first side.Such heat treatment rapid thermal annealing (RTA) technology that can apply heat of high temperature at short notice capable of using is implemented, and can implement in for example 800 to 1100 ℃ temperature range.Can be through using for example nitrogen (N 2) environment implements RTA technology.Or, can use the for example oxygen (O in the oxygen environment 2) annealing enforcement RTA technology.When using nitrogen or oxygen atmosphere, the oxygen passivation that oxide skin(coating) caused (oxygen passivation) by being formed on the doped dielectric layer 500 can suppress the doping impurity agent and be wasted to the outside.In the case, can the doping impurity agent more effectively be spread.
Therefore because the first impurity A s has the diffusivity far below the second impurity P, the diffusion depth of the As in active area 101 is lower than the diffusion depth of the P on equidirectional relatively in a lateral direction.Therefore, the diffusion of active area 101 has the part of As to form first impurity layer 511.Because P has the diffusivity higher than As, therefore can make P in a lateral direction in active area 101 diffusion inside to the degree of depth also bigger than As, the diffusion profile that forms around second impurity layer 513 of first impurity layer 511 is provided thus.Therefore, flush type knot 510 is formed the As diffusion profile that comprises first impurity layer 511, the P diffusion profile that reaches second impurity layer 513 that centers on first impurity layer 511.
With reference to Figure 14, optionally remove doped dielectric layer 500 (Figure 13), and bit line conductive layer (the for example metal level 620 of titanium nitride (TiN)) is deposited on first groove 110.Metal level 620 can comprise TiN layer or tungsten (W) layer.Interface between metal level 620 and flush type knot 510 can import like TiSi when metal level 620 is formed by W xSilicide layer or comprise Ti and the compound layer of TiN as boundary layer 610.The embedded type bit line 600 that comprises boundary layer 610 and metal level 620 sees through opening 410 contact flush type knots 510.In view of the above, one-sided contact is formed the sidewall 113 that only contacts active area 101 but not sidewall 115.
With reference to Figure 15, after forming bit line 600, will be used for first insulating barrier 710 of embedded type bit line 600 insulation is formed on first groove 110.First insulating barrier 710 can comprise for example silicon nitride (Si 3N 4).On first insulating barrier 710, form second insulating barrier 720 and insert first groove 110.Can the SOD densification be formed second insulating barrier 720 through for example applying the dielectric material of rotary coating (SOD) (like polysilazane (polysilazane)) and seeing through heat treatment.Can be further high-density plasma (HDP) oxide skin(coating) be formed on the SOD layer and as being used for the layer that the SOD layer is fixing.That is, can second insulating barrier 720 be formed the bilayer that comprises SOD layer and HDP oxide skin(coating).
Form the 3rd groove 116 is separated into several unit cells (unit cell) as the wall body that will include source region 101 111 separation groove to form several active posts 112.
With reference to Figure 16, the 3rd groove 116 is formed and embedded type bit line 600 intersects (cross), and form the 3rd side 119 of exposing active post 112, on the 3rd side 119 of active post 112, formation is used as the grid 750 of word line.In order not allow embedded type bit line 600 to expose, first insulating barrier 710 or second insulating barrier 720 can partly be retained on the bottom of the 3rd groove 116.
The 3rd side 119 of the active post 112 that will be exposed by the 3rd groove 116 forms to have with first side 113 and second side 115 and intersects the plane of (intersecting).On the 3rd side 119, for example form gate dielectric 751 through implementing thermal oxidation or similar approach.
On gate dielectric 751, form the grid 750 that is used as word line.Grid 750 formed be attached to gate dielectric 751, and can comprise metal level like the W layer.Can be deposited upon in the 3rd groove 116 and then can implement anisotropic etch process one and on the 3rd side 119 that the 3rd groove 116 faces with each other, form other grid 750 at each.In view of the above, can each active post 112 be attached in the middle of several grids 750.Interface between W layer and gate dielectric 751 can import the Ti/TiN layer as adhesive linkage.Grid 750 formed on the direction of intersecting with embedded type bit line 600 extend.After deposition is used for the layer of grid 750 and makes its depression side with the upper end of exposing active post 112; Can be with the impurity that has with first impurity and the second impurity same conductivity; P for example; Be doped into the upper end of active post 112, form the upward knot 550 that can be used as source terminal (source terminal) thus.Thus, can form vertical transistor, and with several capacitors integrated and be coupled to the knot 550, form the DRAM memory cell thus.
In the vertical transistor of embodiments of the invention, form flush type knot 510 as mixing and doping method (hybrid doping method) with impurity of different diffusivitys through using As and P.Therefore, utilize the contact resistance that reduces the flush type knot, can the knot diffusion profile be formed desired shapes.
With reference to Figure 17, form flush type knot 510 as one-sided contact (OSC, one side contact) at the wall body that includes source region 101 111 or through the bottom of separating wall body 111 formed active posts 112.Flush type knot 510 comprises: diffusion have the low As of diffusivity first impurity layer 511, and diffusion second impurity layer 513 of the high relatively P of diffusivity is arranged.Therefore because the As in first impurity layer 511 has low diffusivity, the diffusion profile of first impurity layer 511 can significantly not extended in a lateral direction, even but with high-concentration dopant As, still can be restricted and more near first side 113 of OSC.In other words, can suppress the diffusion profile of first impurity layer 511 and significantly extend in a lateral direction, and can increase the As concentration in first impurity layer 511.Therefore because first impurity layer 511 is set to adjacent, will sees through the embedded type bit line 600 that opening 410 contacts and be electrically connected to first impurity layer 511 with the superficial layer that is exposed to opening 410 of first side 113.
Can form the contact resistance that ohmic contact reduces embedded type bit line 600 (Figure 16).In order to form ohmic contact, can the concentration of first impurity layer 511 be made as high value.Yet when the dopant that diffusivity is also bigger than the diffusivity of As was doped into first impurity layer 511, diffusion depth distributes can be along with concentration increases.In the case, diffusion profile 53 (Figure 18) can be extended towards second side 115 of same wall body 111.When the diffusion profile 53 of flush type knot when first side 113 extends to second side 115, in the part and place that semiconductor substrate 100 be isolated from each other of diffusion profile 53, can form the floating body structure with active area 101 overlapping grids 750.In such floating body structure, the hole charge of part that is accumulated in grid 750 belows of active area 101 can not be escaped to semiconductor substrate 100.Therefore, possibly minus effect arranged to transistorized running by the hole charge of accumulation continuously, thereby cause fault.
Because use the doping impurity agent of As as first impurity layer 511 in an embodiment of the present invention, even therefore increase concentration of dopant, the low diffusivity of As still can suppress the diffusion profile of first impurity layer 511 and can not extend too deeply in a lateral direction.In view of the above, can the concentration of first impurity layer 511 be set at the required high concentration of ohmic contact, for example, at 5E19 dosage/cm 3To 7E20 dosage/cm 3Scope.
When formation has first impurity layer 511 of As doping; The low diffusivity of As helps suppressing the bad degree of depth extension (depth extension) of diffusion profile, but the low diffusivity of As possibly be unfavorable for separating a distance B 3 with first impurity layer 511 and by the raceway groove position of grid 750 overlappings.Opening 410 is arranged at the lower position of opening a predetermined distance B 4 with grid in 750 minutes.Provide such structure with the embedded type bit line 600 guaranteeing to see through opening 410 and be connected to flush type knot 510 with form with the crossing grid 750 of embedded type bit line 600 between separate tolerance limit (separation margin).Can the embedded type bit line 600 and the tolerance limit of separating between the grid 750 be set at for example about 40nm.Separately tolerance limit like this can prevent the short circuit between embedded type bit line 600 and the grid 750 through guaranteeing process tolerant (process margin).
When this separately tolerance limit reduces, just be difficult to guarantee process tolerant.Moreover; During the transistor running; The phenomenon that possibly not match (mismatch phenomenon), in this phenomenon, the threshold voltage vt during the running that reads or writes of DRAM may change because of the generation or the interference of the parasitic capacitance between embedded type bit line 600 and the grid 750.Therefore, can guarantee distance of separation and the insulation expected between embedded type bit line 600 and the grid 750 through first insulating barrier 710 (Figure 16) and/or second insulating barrier 720 (Figure 16) are imported.
Form the flush type knot 510 that only has first impurity layer 511 and possibly cause not desired characteristics.This possibly be the cause that the end of the diffusion profile of first impurity layer 511 should overlap with grid 750.Yet, because diffusion length D5 is subject to the low diffusivity of As, therefore can between first impurity layer 511 and grid 750 distance of separation D3 appear.The appearance of distance of separation D3 possibly cause the quick increase of transistorized threshold voltage vt.Compared to when first impurity layer 511 and grid 750 not being separated from each other, when recording distance of separation D3 and be 20nm, at channel doping density 1E12 dosage/cm 3Following experiment records threshold voltage to be increased more than the 1V accordingly.When the concentration with As is divided in 7E20 dosage/cm 3To 3E20 dosage/cm 3Scope the time, experiment records threshold voltage vt and is increased to the grade of scope from 1.2 to 1.6V fast.In order to suppress the increase of threshold voltage, just must reduce distance of separation D3.In order to realize that this reduces, can reduce the distance of separation D4 of opening 410, but because of guaranteeing that the distance of separation of expecting between embedded type bit line 600 and the grid 750 possibly be difficult to carry out.
In order to compensate the threshold voltage that when only using As, increases, so that tying 510, flush type has wider diffusion profile and form second impurity layer 513 with low diffusivity.The P that diffusivity is high relatively is doped into second impurity layer 513, and can the concentration also lower than the concentration of As mix.For example, can approximate range from 6.3E16 dosage/cm 3To 5.7E19 dosage/cm 3Doped in concentrations profiled P.Because the high relatively diffusivity of phosphorus, therefore second impurity layer 513 is spread also deeplyer than first impurity layer 511.In view of the above, diffusion profile can extend to the bigger degree of depth.Can second impurity layer 513 be formed around first impurity layer 511, and the extensible and raceway groove that partly overlaps of the diffusion profile of whole flush type knot 510 this raceway groove part that to be active area 101 overlap with grid 750.This is because shown in figure 19, the diffusivity of P or diffusion length are also bigger than diffusivity or the diffusion length of As.
Figure 19 shows the result that diffusion profile obtained who utilizes through ion microprobe (SIMS) measurement arsenic-75 (75As) and phosphorus-31 (31P).75As and 31P are stable and be considered to monoisotopic element.When at 1E18 dosage/cm 3Concentration under when measuring diffusion depth, the diffusion depth of the 75As that records is 203
Figure BDA0000106303790000121
The diffusion depth of the 31P that records simultaneously is 175
Figure BDA0000106303790000122
The concentration of the 75As of surface is made as 6.5E19 dosage/cm 3, and the concentration of 31P is made as 5.7E19 dosage/cm 3, and overall density is made as 1.2E20 dosage/cm 3Under 1000 ℃ temperature, see through 10 seconds of heat treatment that the RTA process implementing is used to spread.In Figure 19, the distribution that records with SIMS demonstrates 31P and spreads deeplyer.
Because utilize doping P to form second impurity layer 513, the diffusion profile of therefore whole flush type knot 510 may extend in abutting connection with raceway groove, and this raceway groove is the part of the overlapping grid 750 of active area 101.In view of the above, can transistorized threshold voltage vt be reduced to the level of scope 0.6 to 0.2V.This expression can compensate the quick increase of the threshold voltage that when flush type knot 510 includes only first impurity layer 511 of the As that only mixes, takes place.Be set at the doping content that is lower than As because will be used for the doping content of the P of second impurity layer 513, therefore can second impurity layer 513 and second side be opened a preset distance 520 (Figure 21) in 115 minutes.That is the concentration that, can reduce P is excessively extended towards second side 115 with the diffusion profile that suppresses second impurity layer 513.
When reaching the required doping impurity concentration of ohmic contact and utilizing doping P to reach wide diffusion profile, just can realize such structure through the doping content that increases As.Because second impurity layer 513 and second side were opened preset distance 520 in 115 minutes, therefore, can realize body construction (body structure) in the part below raceway groove and the not separated position of semiconductor substrate of active area 101.In view of the above, hole charge can flow to semiconductor substrate 100, suppresses hole charge thus effectively and is accumulated.
In an embodiment of the present invention, because guarantee exposure concentration and guarantee junction depth, therefore flush type knot 510 is formed the wide knot (broad junction) with gentle distribution through the P that uses high diffusivity through the As that uses low diffusivity.In view of the above, wide knot capable of using is realized the minimizing of electric field, and can raceway groove and junction resistance be reduced to reach stable transistor running.Though the concentration of As is maintained high value, can guarantees flush type knot 510 and the overlapping between the raceway groove below the grid 750.Therefore, can guarantee embedded type bit line 600 with as the tolerance limit of separating between the word line of grid 750, and can avoid the threshold voltage vt of cell transistor to increase effectively.Moreover the depositing device that can use ion injection and deposit spathic silicon to use implements to realize the technology of flush type knot 510.In view of the above, new equipment needn't be imported and just vertical transistor can be made.
Can use the method for various modified doping methods, as long as mix As and P simultaneously as the flush type knot of the vertical transistor that is used to form embodiments of the invention.With reference to Figure 20～26 these modification are described.
With reference to Figure 20, deposition is doped with the polysilicon layer of low concentration P and high concentration As simultaneously.Then polysilicon layer is etched back to the top of the opening 410 of one-sided contact mask, forms doped dielectric layer 501 thus.
With reference to Figure 21, RTA technology capable of using comprises doped dielectric layer 501 diffusions the flush type knot 525 of first impurity layer 521 and second impurity layer 523 with formation.In the case, As and the P of when the depositing doped polycrystalline silicon layer, mixing together capable of using omits ion implantation technology or similar technology.
With reference to Figure 22, deposit the not unadulterated polysilicon of impurity, then be etched back to the top of the opening 410 of one-sided contact mask.Then, the doping method of injecting like ion capable of using mix low concentration P and high concentration As form doped dielectric layer 503 thus.RTA technology capable of using comprises doped dielectric layer 503 diffusions the flush type knot 530 of first impurity layer 531 and second impurity layer 533 with formation.The doping that can provide As compound or P-compound to implement As and P through form with doped source gas, and substitution ion injects.In the case, when depositing unadulterated polysilicon layer and utilizing ion implantation doping As and P, can simplify the formation technology of doped polycrystalline silicon layer.
With reference to Figure 23, the opening 410 like doped source to the one-sided contact mask of the P-compound of phosphine gas is provided, and P directly is doped into first side 113.In view of the above, form the layer 544 of doping P.Then, the technology of the As that can implement to mix, for example, ion implantation technology.In the case, can As directly be injected the exposed portions serve of first side 113.
Perhaps, with reference to Figure 24, can form doped dielectric layer 505 as the polysilicon layer of doping As.Then, with reference to Figure 25, utilize RTA technology diffusing, doping dielectric layer 505 to comprise the flush type knot 540 of first impurity layer 541 and second impurity layer 543 with formation.Following technology capable of using forms the doped dielectric layer 505 of the polysilicon layer of doping As: deposit unadulterated polysilicon layer and eat-back; And then the As ion is injected to form doped dielectric layer 505.
With reference to Figure 26, can P and As directly be doped into first side 113 that the opening 410 that sees through one-sided contact mask exposes, form the layer 555 that mixes thus.Then, when with the P-compound plasma exciatiaon and when providing to first side 113, can be with P plasma doping to the first side 113 that excites.In addition, when with As compound plasma exciatiaon and when providing to first side 113, can be with As plasma doping to the first side 113 that excites.Layer 555 to the formed doping of plasma doping is implemented RTA technology, the doping impurity agent of diffusing, doping thus.Then, can form the flush type knot 550 that comprises first impurity layer 551 and second impurity layer 553.
After forming doped dielectric layer 500 as shown in figure 13, see through the diffusion that heat treatment causes impurity.Then, can use doped dielectric layer 500 as bit line, but not remove.For example, with reference to Figure 14, deposition is used for the independent conductive layer of bit line 600, and can will stay as the polysilicon layer of the not impurity of doped dielectric layer 500 and be used as bit line 600 not implementing optionally to remove under the technology of doped dielectric layer 500.Because through only using polysilicon layer to form bit line 600, therefore can omit selective etch technology, and the technology of the independent conductive layer of deposition and etching.Therefore, can reduce the technology number.
Can implement to be used for the RTA technology of diffusion impurity through the oxygen annealing process that uses the carrier of oxygen environment.For example, when use comprises the gaseous environment of nitrogen or oxygen, utilize the oxygen passivation that is formed on the oxide skin(coating) on the doped dielectric layer 500 can suppress the doping impurity agent and run off to outside.In the case, diffusion impurity dopant more effectively.In view of the above, can be suppressed at impurity in the doped dielectric layer 500 and during RTA technology, leak to the outside on surface and run off, and can keep the high conductivity of the bit line that comprises doped dielectric layer 500.
With reference to Figure 27, can be with metal level with high conductivity, the metal level 630 of W or Ti for example, additional deposition forms bit line 605 thus on the polysilicon layer that is used as doped dielectric layer 500.In the case, for the layer that suppresses oxidation is formed on the polysilicon layer surface of doped dielectric layer 500, can in the inert gas environment that can not cause the oxygen passivation, implement RTA technology.Inert gas environment for example can be the nitrogen environment.In some cases, can doped dielectric layer 500 partly be recessed to desired depth, and can follow depositing metal layers 630.。
According to various embodiments of the present invention, the junction depth of may command diffuse dopants is maintained high value with concentration of dopant simultaneously.Therefore, can cause wider knot and distribute removing the distance of separation between knot and the channel region, and can suppress the quick increase of channel threshold voltage.Moreover, because the diffusion profile that can avoid effectively tying is extended too far, and prevent that substantially channel region from being tied isolation, and can suppress the initiation (induction of the floating body effect) of floating body effect effectively.Moreover, because can the concentration of dopant at the surface portion of tying be set at high value, therefore can reduce knot contact resistance with the embedded type bit line that contacts and be coupled to knot.
The priority to the korean patent application case of Korea S Department of Intellectual Property application 10-2010-0110515 number on November 8th, 2010 is advocated in this case, and incorporates it into this paper in full by reference.

Claims (42)

1. method of making the knot of vertical transistor comprises:
In semiconductor substrate, form groove to form first wall body and second wall body, wherein this groove has the sidewall of second side of several first sides that comprise this second wall body and this first wall body;
Formation has the one-sided contact mask of opening, and this opening optionally only exposes the part of this first side of this second wall body; And
The part of exposing that sees through this first side through the impurity that will have different diffusivitys diffuses to second impurity layer that this second wall body forms first impurity layer and centers on this first impurity layer.
2. this impurity that method as claimed in claim 1, this impurity that wherein is used to form this first impurity layer comprise arsenic (As) and be used to form this second impurity layer comprises phosphorus (P).
3. method as claimed in claim 2, wherein the concentration of the phosphorus (P) in this second impurity layer is lower than the concentration of the arsenic (As) in this first impurity layer.
4. method as claimed in claim 2, wherein this second impurity layer extends towards first side of this second wall body.
5. method as claimed in claim 1 wherein forms this first impurity layer and this second impurity layer comprises:
Apply this part of exposing of this first side of first impurity and second impurity to this second wall body via the doped dielectric layer in this groove; And
Implement heat treatment and diffuse to this second wall body with this part exposed that this first impurity and second impurity is seen through this first side of this second wall body.
6. method as claimed in claim 5, wherein this doped dielectric layer comprise arsenic as this first impurity, and as the phosphorus of this second impurity.
7. method as claimed in claim 5 wherein forms this doped dielectric layer and comprises:
This doped dielectric that is doped with as the phosphorus (P) of this second impurity is deposited upon in the groove between this first wall body and second wall body; And
With the etching in addition of the part above this opening of this one-sided contact mask of this doped dielectric layer, and the part of the reservation of this doped dielectric layer is contacted with this part of exposing of this first side of this second wall body.
8. method as claimed in claim 7 wherein is infused in arsenic (As) ion the part of this reservation of this doped dielectric layer after etching.
9. method as claimed in claim 5 is wherein substantially implemented this heat treatment under 800 ℃ to 1,100 ℃ the temperature range.
10. method as claimed in claim 5 is wherein comprising that nitrogen and oxygen implements this heat treatment under one of them the gaseous environment at least.
11. method as claimed in claim 1 wherein forms this one-sided contact mask and comprises:
Form first lining and second lining, this first lining covers the bottom of this second side of this first side and this first wall body of this second wall body, and this second lining covers the top of this first lining top on respectively this first side and second side;
Buried horizon is formed in the bottom of this groove of this second lining below;
Form the 3rd lining, the 3rd lining covers the part that is not covered by this buried horizon of this second lining and this first lining;
Above this buried horizon, form sacrifice layer, and make sacrifice layer be filled in the 3rd lining and the interval between the 3rd lining on this second wall body on this first wall body;
A part of and this sacrifice layer that removes the 3rd lining is to expose the top of this second lining;
Form etch, etch is used for optionally exposing: this end of the 3rd lining on this second lining on this second lining on this first side of this second wall body, this first side at this second wall body, and this sacrifice layer and this first side at this second wall body on second lining on the adjacent part of the 3rd lining;
To remove by the 3rd lining that this etch is exposed so that between this sacrifice layer on this first side of this second wall body and first and second lining, form groove;
Form this opening, this opening exposes this part of this first side through the part that is exposed to this groove that optionally removes this first lining; And
Form this one-sided contact mask, first and second lining that this one-sided contact mask comprises this reservation through this sacrifice layer and the 3rd lining that optionally removes on this second side that is retained in this first wall body.
12., wherein form this etch and comprise like the method for claim 11:
Form the polysilicon layer that covers this wall body, this second lining, the 3rd lining, reaches the end face of this sacrifice layer;
With the inclination angle ion implantation technology is implemented at the top of this wall body, optionally foreign ion being injected this polysilicon layer, except in the part on this first side of this second wall body, and the part near this groove of covering of this second wall body; And
Optionally remove the part that is not injected into foreign ion of this polysilicon layer.
13. a method that forms the knot of vertical transistor comprises:
Form first wall body and second wall body from semiconductor substrate, each wall body has second side on first side and opposite; And
With first impurity layer, and the second also low impurity layer of concentration ratio first impurity layer be formed on the part of this first side of this second wall body, and make this second impurity layer around this first impurity layer.
14., wherein form this first impurity layer and this second impurity layer comprises like the method for claim 13:
Formation has the one-sided contact mask of opening, and this opening optionally exposes the part of this first side of this second wall body;
The polysilicon layer that forms doping P is to contact the part that this opening was exposed by this one-sided contact mask of this first side;
See through the ion injection As is doped into this polysilicon layer; And
Implement heat treatment this doped P and As are diffused to this part of this first side.
15. a method of making vertical transistor comprises:
Form first wall body and second wall body of vertical protuberance from semiconductor substrate, each wall body has second side on first side and opposite, and this first wall body and second wall body are by first groove separately;
Formation has the one-sided contact mask of opening, and this opening optionally exposes the part of this first side of this second wall body;
First impurity through will having different diffusivitys and second diffusion of impurities to this first side by this part that this opening exposed, form and comprise first impurity layer and around the flush type knot of second impurity layer of this first impurity layer; And
Formation is embedded in the embedded type bit line between this wall body, wherein via this opening of this one-sided contact mask this embedded type bit line electrical couplings to this flush type is tied.
16. like the method for claim 15, wherein use the first impurity A s to form this first impurity layer, and use the second impurity P to form this second impurity layer.
17. like the method for claim 16, wherein the concentration of the P in this second impurity layer is lower than the As in this first impurity layer.
18., wherein form this second impurity layer and make this second impurity layer can not contact this second side of this second wall body through diffusion P like the method for claim 17.
19., wherein form the flush type knot that comprises this first impurity layer and this second impurity layer and comprise like the method for claim 15:
Formation comprises the doped dielectric layer of second impurity and makes this doped dielectric layer contact the part that this opening exposed by this one-sided contact mask of this first side;
With diffusivity than low first doping impurity of second impurity to this doped dielectric layer; And
Implement heat treatment with first impurity that will mix and second diffusion of impurities to this first side by this part that this opening was exposed.
20. like the method for claim 19, wherein the formation of this doped dielectric layer comprises:
The polysilicon layer that is doped with as the P of this second impurity is deposited between this first wall body and second wall body;
This polysilicon layer is etched back to above this opening of this one-sided contact mask; And
To be injected into the polysilicon layer that this eat-backs as the As ion of this first impurity.
21., wherein use this polysilicon layer to form this embedded type bit line like the method for claim 20.
22. like the method for claim 21, its also comprise with layer metal deposition on this polysilicon layer to form this embedded type bit line.
23., wherein form this flush type knot that comprises this first impurity layer and this second impurity layer and comprise like the method for claim 15:
Formation comprises the doped dielectric layer of first impurity with different diffusivitys and second impurity and makes this part that this opening exposed by this one-sided contact mask of this this first side of doped dielectric layer contact; And
Implement heat treatment with first impurity that will mix and second diffusion of impurities to this first side by this part that this opening was exposed.
24., wherein form this doped dielectric layer and comprise like the method for claim 23:
Dopant deposition has As and P respectively as the polysilicon layer of this first impurity and second impurity; And
This polysilicon layer is etched back to above this opening of this one-sided contact mask.
25., wherein form this doped dielectric layer and comprise like the method for claim 23:
Deposit unadulterated polysilicon layer and insert the interval between this first and second wall body;
This polysilicon layer is etched back to above this opening of this one-sided contact mask; And
As and P ion are injected this polysilicon layer.
26., wherein form this flush type knot that comprises this first impurity layer and this second impurity layer and comprise like the method for claim 15:
Through this part that this opening exposed that phosphine gas to this first side is provided P that mixes by this one-sided contact mask;
Formation comprises the doped dielectric layer of As, and make this first side of this doped dielectric layer contact by this part that this one-sided contact mask exposed; And
Implement heat treatment diffuses to this first side with the As that will mix this part that is contacted by this doped dielectric layer forming this first impurity layer, and this doped P is spread to form this second impurity layer.
27., wherein form the polysilicon layer that this doped dielectric layer that comprises As comprises dopant deposition As like the method for claim 26.
28. like the method for claim 26, wherein formation comprises that this doped dielectric layer of As comprises:
Deposit unadulterated polysilicon layer; And
The As ion is injected this polysilicon layer.
29., wherein form this flush type knot that comprises this first impurity layer and this second impurity layer and comprise like the method for claim 15:
As and P are doped into this part that this opening exposed of this first side by this one-sided contact mask; And
Implement As and the P of heat treatment to spread this doping.
30., wherein implement the doping of As and P and this part that this opening exposed by this one-sided contact mask to this first side be provided with the plasma of As and P through plasma doping technology like the method for claim 29.
31., wherein form this one-sided contact mask and comprise like the method for claim 15:
Form first lining and second lining, this first lining covers the bottom of this second side of this first side and this first wall body of this second wall body, and this second lining covers the top of this first lining top on this first and second side respectively;
Buried horizon is formed in the bottom of this first groove of this second lining below;
Form the 3rd lining, it covers the part that is not covered by this buried horizon of this second lining and this first lining;
Above this buried horizon, form sacrifice layer and make sacrifice layer be filled in the 3rd lining and the interval between the 3rd lining on this second wall body on this first wall body;
Make the 3rd lining and this sacrifice layer depression so that the bottom in the zone of this depression comprises the upper surface of the 3rd lining and the upper surface of this sacrifice layer, and the sidepiece in the zone of this depression comprise this second lining;
Form etch, be used for optionally exposing: this end of the 3rd lining on this second lining on this second lining on this first side of this second wall body, this first side at this second wall body;
To remove by the 3rd lining that this etch is exposed, and between this sacrifice layer on this first side of this second wall body and this first and second lining, form groove;
Form opening, this opening exposes this part of this first side through this part that is exposed to this groove that removes this first lining; And
Form this one-sided contact mask, first and second lining that this one-sided contact mask comprises this reservation through this sacrifice layer and the 3rd lining that optionally removes on this second side that is retained in this first wall body.
32., wherein form this etch and comprise like the method for claim 31:
Form the polysilicon layer that covers this wall body, this second lining, the 3rd lining, reaches the end face of this sacrifice layer;
With the inclination angle angle-tilt ion injection technology is implemented at the top of this wall body, optionally foreign ion being injected this polysilicon layer, except in the part on this first side of this second wall body, and the part near this first groove of covering of this second wall body; And
Optionally remove the part that is not injected into foreign ion of this polysilicon layer.
33. like the method for claim 15, it also comprises:
Form and separate groove, this separation groove intersects with this first groove and this first wall body and second wall body is separated into a plurality of active posts;
Gate dielectric is formed on the part that is exposed to this separation groove of side of this active post;
In this separation groove, form grid and this grid and this embedded type bit line are intersected; And
Form the knot of going up of becoming a partner and answering with this flush type of active post through the upper end that the 3rd impurity layer is doped into this active post.
34. like the method for claim 33, wherein this second impurity layer and this grid are not separated in vertical direction; And
This first impurity layer is separated with this grid on this vertical direction.
35., wherein this grid is arranged at than the also high position of this opening of this one-sided contact mask this first impurity layer is separated with this grid on this vertical direction like the method for claim 34.
36. a vertical transistor comprises:
A plurality of second sides that have first side and opposite from active post and each active post of semiconductor substrate projection;
One-sided contact mask with opening, this opening optionally expose the bottom of this first side of this active post;
Flush type knot comprises first impurity layer and around second impurity layer of this first impurity layer, and wherein the part by this opening exposed of this first impurity and second impurity layer diffusion of impurities to this first side through will having different diffusivitys forms; And
Embedded type bit line is embedded between this active post and contacts this flush type through this opening of this one-sided contact mask and ties.
37., wherein form this first impurity layer, and through forming this second impurity layer with the doped in concentrations profiled P lower than As through doping As like the vertical transistor of claim 36.
38. like the vertical transistor of claim 36, it also comprises: gate dielectric is formed on the 3rd side of this active post;
Grid is formed on this gate dielectric and with this embedded type bit line and intersects; And
Last knot is formed on the upper end of this active post and corresponding to this flush type knot through the 3rd impurity layer that mixes.
39., wherein in specific active post, this grid is arranged to vertically separate with this first impurity layer, and this second impurity layer does not contact this second side of this specific active post like the vertical transistor of claim 38.
40. like the vertical transistor of claim 39, wherein this grid is in vertical direction at least in abutting connection with this second impurity layer that perhaps overlaps at least.
41. like the vertical transistor of claim 39, wherein this opening of this one-sided contact mask separates with this grid in vertical direction.
42. like the vertical transistor of claim 38, it also comprises: insulating barrier imports at this grid intersected with each other and the interface between this embedded type bit line, and this first impurity layer is separated with this grid in vertical direction.
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