JPH02298039A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a deterioration in a characteristic by a method wherein a pattern film corresponding to a gate electrode is formed on a semiconductor region, at least one part on the pattern film from a semiconductor layer con nected to the semiconductor region is removed and, after that, the pattern film is removed. CONSTITUTION:Pattern films 21, 22 having a pattern corresponding to a gate electrode 26 are formed on a semiconductor region 11 ; at least one part on the pattern films 21, 22 from a semiconductor layer 13 connected to the semicon ductor region 11 is removed; after that, the pattern films 21, 22 are removed. Accordingly, even when a removal selection ratio such as an etching selection ratio or the like is small at the semiconductor region 11 and the semiconductor layer 13, the semiconductor layer 13 in a part where the gate electrode 26 is formed can be removed without damaging the semiconductor region 11 when the pattern films 21, 22 are formed of a material whose selection ratio with reference to them is large.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor layer covers a source/drain region.

[Summary of the invention]

The present invention provides a method for manufacturing a semiconductor device as described above.
A patterned film having a pattern corresponding to the gate electrode is formed on the semiconductor region, at least a portion of the semiconductor layer connected to the semiconductor region on the patterned film is removed, and then the patterned film is removed. This makes it possible to manufacture semiconductor devices with excellent characteristics.

[Conventional technology]

In order to miniaturize semiconductor devices, for example, in MOS transistors, it is necessary to
It is necessary to reduce the area of the area.

For this purpose, an MO3I transistor in which the source/drain region is covered with a semiconductor layer has been considered, and one of its manufacturing methods was described in the rVLSI Symposium, May 10-13, 1988, p. 11-12. Are listed.

According to this manufacturing method, as shown in FIG. 3A, a Sing film 12 for element isolation is formed on the surface of a Si substrate 11, and a pure polycrystalline Si layer 13 containing no impurities is formed to a thickness of 200 nm.
As+ ions 14 and P' ions 1
5 polycrystalline 5ili13 is sequentially implanted.

Next, as shown in FIG. 3B, 5i is placed on the polycrystalline 54 layer 13.
(The h film 16 is deposited by CVD, and from this state
ing film 16 and polycrystalline St layer 13 are etched into patterns of source wiring and drain wiring.

Therefore, at this time, SiO□lI! of the part where the channel region, that is, the gate electrode is to be formed! 16 and polycrystalline Si layer 13
Also etching.

Next, as shown in FIG. 3C, polycrystalline 5rJl! A 5i01 film 17 with a thickness of 15 m is grown on the side surfaces of the silicon base 13 and the surface of the channel region of the Si-based 4Fi11.
The second film 17 is used as a gate oxide film.

Then, a polycrystalline 81 layer 18 is deposited on the Sin film 16 and 17, P is contained in the polycrystalline Si layer 18, and the polycrystalline 5iji 18 and 5i02 film 16 is patterned into a gate electrode pattern.

Finally, by two-step ramp annealing, the 3D
As shown in the figure, TiS is applied to the surface of the polycrystalline Si layer 13.18.
Forming the i2 layer 19, these polycrystalline Si layers 13.1
Aiming to lower the resistance of 8.

[Problem to be solved by the invention]

However, since the etching selectivity of polycrystalline Si and Si is small, when the polycrystalline Si layer 13 is etched in the step shown in FIG. 3B, the channel region of the Si substrate 11 is also etched, and this portion of the Si substrate receive damage. Therefore, in the above-mentioned conventional example, a semiconductor device with excellent characteristics cannot be manufactured.

Although the above-mentioned document also describes a method for recovering damage to the Si substrate 11, it is naturally preferable that the Si substrate 11 not be damaged.

Moreover, the S
The above-mentioned document also states that when the i-substrate 11 is etched, deterioration of the characteristics of the semiconductor device is unavoidable.

[Means to solve the problem]

In the method of manufacturing a semiconductor device according to the present invention, the gate electrode 26
a step of forming a patterned film 21.22 having a pattern corresponding to the above on the semiconductor region 11, and a step of connecting the semiconductor layer 13 containing the impurity 14.15 to the semiconductor region 11 and covering the patterned film 21.22. a step of diffusing the impurity 14.15 from the semiconductor layer 13 to the semiconductor region 11; and a step of forming the pattern film 21.
．． a step of removing at least a portion of the semiconductor layer 13 on the semiconductor layer 22; a step of removing the pattern film 21 and 22 after the removal of at least a portion of the semiconductor M13;
a step of oxidizing the surface of the semiconductor layer 13 and the surface of the semiconductor region 11 not covered with the semiconductor layer 13 after the removal of the pattern film 21.22; and a step of forming the gate electrode 26 in the previously formed portion.

(Function) In the method for manufacturing a semiconductor device according to the present invention, the gate electrode 2
Patterned films 21 and 22 having a pattern corresponding to 6 are formed on the semiconductor region ll, and the patterned films 21 and 22 are formed in the semiconductor layer 13 connected to the semiconductor region 11.
At least a portion of the top is removed, and then pattern H21 is removed.
, 22 are removed.

Therefore, even if the removal selectivity such as etching selectivity is small between the semiconductor region 11 and the semiconductor layer 13, the gate electrode 26 can be formed by forming the patterned films 21 and 22 with a material that has a large selectivity with respect to these. The desired portion of the semiconductor layer 13 can be removed without damaging the semiconductor region 11.

Further, impurity 14 from the semiconductor layer 13 to the semiconductor region 11
．． By the diffusion of 15, source/drain regions 23 and 24 are formed in the semiconductor region 11 in a self-aligned manner, and the semiconductor layer 13 becomes a source wiring and a drain wiring.

Furthermore, an insulating film 25 is formed between the source wiring, the drain wiring and the gate electrode 26 by oxidation of the surface of the semiconductor layer 13, and the semiconductor region 1 not covered with the semiconductor layer 13 is
By oxidizing the surface of 1, a gate oxide film 25 is formed.

〔Example〕

An embodiment of the present invention applied to the manufacture of MO3I transistors will be described below with reference to FIGS. 1 and 2.

In this embodiment as well, as shown in FIG. 1A and FIG.
Up to 12 g films and 2 films are processed in the same manner as in the above-mentioned conventional example. In this embodiment, after that, the thin 5i02 film 21 and the PSG film 2
2 and 2 are sequentially formed on the Si substrate 11, and the PSG film 22 and the SiO2 film 21 are etched in the pattern of the gate electrode.

Since the etching selectivity between PSG, Sto, and Si is large, the portions of the Si substrate 11 that will become the source and drain regions are etched during the processing and etching of PSG Tsukimi 2Z and 5i (hl! Virtually no one receives it.

Moreover, since PSG has a faster etching speed than Sin, SungMl is used when etching the PSG film 22.
The amount of 2 etched is very small.

Therefore, the etching selectivity ratio to St is large and SiO2
In place of the PSG film 22, a film made of any other material other than PSG may be used as long as the material has a faster etching rate than the PSG film 22.

Thereafter, a polycrystalline Si layer 13 is deposited and As" ions 14 and P
``Ion 15 implantation is performed, and the polycrystalline Si layer 13 is further etched into patterns of source wiring and drain wiring.

At this time, the polycrystalline Si layer 1 in the part where the gate electrode is to be formed is
Although etching is performed by 3°, as is clear from FIGS. 1A and 2, the PSG film 22 is formed in this portion, and the etching selectivity between PSG and polycrystalline St is high.

Therefore, even though the etching selectivity between polycrystalline Si and Si is small, the portion of the Si substrate 11 where the gate electrode is to be formed is etched and damaged at the same time as the polycrystalline Si layer 13 is etched. There is no.

Thereafter, As and P are solid-phase diffused from the polycrystal 5ill13 into the Si substrate 11 to form source/drain regions, but P has a larger diffusion coefficient than As.

Therefore, in the sin plate 11, there is n containing both ^S and P.
″area 23 and an n-area 24 containing only P are formed,
A double diffused drain structure is formed.

Moreover, page area 23, which is the source/drain order page area,
Since the n- region 24 is formed by solid phase diffusion, shallow source/drain regions can be formed.

Note that this solid phase diffusion may be performed before patterning the polycrystalline 31 layer 13, or may be performed in the steps shown in FIGS. 1B and 1C, which will be described later.

Next, as shown in FIG. 1B, the PSG film 22 and the 5 iodine film 21 are removed by wet etching using hydronic acid. At this time as well, since the etching selectivity between PSG and SiO□ and Si is high, when etching the PSG film 22 and the 5i02 film 21, the portion of the Si substrate 11 where the gate electrode is to be formed will be etched and damaged. There are virtually no

Thereafter, the Sto film 25 is formed by thermal oxidation.

This Sin, polycrystalline Sil'! in the film 25! The portion formed on the surface of the Si substrate 13 to serve as an insulating film between the source wiring, the drain wiring, and the gate electrode is thicker than the portion formed on the surface of the Si substrate 11 to serve as a gate oxide film.

Next, as shown in FIGS. 1C and 2, a polycrystalline Si layer 2
6 is deposited, P ions, etc. are implanted into the polycrystalline Si layer 26, and the polycrystalline St layer 26 is patterned into the pattern of a gate electrode.

Note that among the parts of the polycrystalline Si layer 26 to be patterned, the part above the channel NM is on the polycrystalline 5ijila, and since the polycrystalline Si layer 26 in this part is flat,
Patterning of the polycrystalline Si layer 26 is easy.

After that, Ti is deposited on the entire surface and sinking is performed in an inert atmosphere. Then, the Ti deposited on the surface of the polycrystalline Si layer 26 is silicided to form a TiSi layer 19, and the resistance value of the gate electrode is reduced.

On the other hand, the Ti deposited on the surface of the 5iOz film 25.12 remains in a metallic state. Therefore, in order to prevent a short circuit with the polycrystalline Si layer 26 serving as the gate electrode, Ti in a metallic state is etched afterwards.

Note that sinking of Ti may be performed in N, atmosphere, or the like.

In this case, Ti deposited on the surface of polycrystalline 5i126
is still the TiSix layer 19, but the 5iOt film 25.
The Ti deposited on the surface of 12 becomes insulating nitride.

Therefore, in this case, it is not necessary to etch the Ti nitride in order to prevent a short circuit with the polycrystalline St layer 26.

Further, the metal for forming the silicide layer on the surface of the polycrystalline 5iJii 26 may be other than Ti, and for example, PT or the like may be used.

(Effects of the Invention) In the method for manufacturing a semiconductor device according to the present invention, the semiconductor layer in the portion where the gate electrode is to be formed can be removed without damaging the semiconductor region, so a semiconductor device with excellent characteristics can be manufactured. be able to.

[Brief explanation of the drawing]

Fig. 1 is a side sectional view sequentially showing one embodiment of the present invention;
The figure is a plan view of a semiconductor device manufactured according to one embodiment. FIG. 3 is a side sectional view sequentially showing a conventional example of the present invention. In addition, in the symbols used in the drawings, 11-...----1~--...St substrate 13--... Polycrystalline S
I layer 14...------------^S+ ion 15-------------------P+ ion 21...・・・−・−・・・−・・・・5iO
1) III22・・・・・・・・・・・・PS
G film 23...--...--------n-region 24---n- region 25--- -・-・・・・・5i02 film 26
・・・・・・・・・・・・・・・・・・Polycrystalline 5iJ
ii.

Claims (1)

[Claims] A step of forming a patterned film having a pattern corresponding to a gate electrode on a semiconductor region, and a step of forming a semiconductor layer containing impurities so as to connect to the semiconductor region and cover the patterned film. a step of diffusing the impurity from the semiconductor layer into the semiconductor region; a step of removing at least a portion of the semiconductor layer on the pattern film; and a step of removing the pattern after the removal of at least a portion of the semiconductor layer. removing a film; oxidizing a surface of the semiconductor layer and a surface of the semiconductor region not covered by the semiconductor layer after the removal of the pattern film; and forming the pattern film after the oxidation. and forming the gate electrode in the previously formed portions.