CN102446837B - 包括半导体芯片的器件的制造 - Google Patents

包括半导体芯片的器件的制造 Download PDF

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Publication number
CN102446837B
CN102446837B CN201110306014.2A CN201110306014A CN102446837B CN 102446837 B CN102446837 B CN 102446837B CN 201110306014 A CN201110306014 A CN 201110306014A CN 102446837 B CN102446837 B CN 102446837B
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Prior art keywords
semiconductor chip
electrical insulating
type surface
insulating material
electric conducting
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Expired - Fee Related
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CN201110306014.2A
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CN102446837A (zh
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I.尼基廷
H-J.蒂姆
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及包括半导体芯片的器件的制造。一种方法，包括：提供半导体芯片，所述半导体芯片具有第一主表面和与所述第一主表面相对的第二主表面。使用等离子体沉积方法将电绝缘材料沉积在所述半导体芯片的第一主表面上。使用等离子体沉积方法将第一导电材料沉积在所述半导体芯片的第二主表面上。

Description

包括半导体芯片的器件的制造
技术领域
本发明涉及一种制造包括半导体芯片的器件的方法。本发明还涉及一种包括半导体芯片的器件。
背景技术
半导体器件制造商一直以来致力于增强其产品的性能，同时降低其制造成本。半导体器件的制造中的成本密集型部分是封装半导体芯片。如本领域技术人员公知的，集成电路是在晶片中制造的，然后对晶片进行分离以产生半导体芯片。将一个或多个半导体芯片置于封装中以保护其免受环境和物理应力。封装半导体芯片提高了制造半导体器件的成本和复杂度，这是由于封装设计不仅应当提供保护，它们还应当允许向半导体芯片以及从半导体芯片传输电信号，以及具体地，去除由半导体芯片产生的热量。
附图说明
附图被包括进来以提供对实施例的进一步理解，并且并入本说明书中并构成本说明书的一部分。附图示意了实施例并与该描述一起用于解释实施例的原理。其他实施例以及实施例的许多预期优势将随着通过参照以下详细描述变得更好理解而被容易地认识到。附图的元素不必相对于彼此按比例绘制。相似的附图标记表示对应的类似部分。
图1A至1C示意性地示出了方法的一个实施例的横截面视图，该方法包括将电绝缘材料和导电材料沉积在半导体芯片上；
图2示意性地示出了包括半导体芯片和沉积在半导体芯片上的层的器件的一个实施例的横截面视图；
图3A至3J示意性地示出了制造器件的方法的一个实施例的横截面视图，该器件包括半导体芯片以及使用等离子体沉积方法而沉积在半导体器件上的电绝缘层和导电层；
图4示意性地示出了在电路板上安装的器件的一个实施例的横截面视图；
图5示意性地示出了等离子体沉积设备的一个实施例的横截面视图；以及
图6示出了通过等离子体沉积方法而沉积的层的电子显微图像。
具体实施方式
在以下详细描述中，参照了附图，这些附图形成以下详细描述的一部分，并且其中以示意的方式示出了可实施本发明的具体实施例。在这一点上，参照所描述的附图的定向，使用了方向性术语，如“顶”、“底”、“前”、“后”、“首”、“尾”等等。由于实施例的组件可以以多个不同定向而定位，因此方向性术语用于示意的目的而决不进行限制。应当理解，在不脱离本发明的范围的前提下，可以利用其他实施例并且可以进行结构上或逻辑上的改变。因此，以下详细描述不应视为具有限制意义，并且本发明的范围有所附权利要求限定。
应当理解，这里描述的各个示例性实施例的特征可以相互组合，除非另有具体说明。
本说明书中所采用的术语“耦合的”和/或“电耦合的”并不意在表示元件必须直接耦合在一起；可以在“耦合的”或“电耦合的”元件之间提供介于其间的元件。
以下描述包含一个或多个半导体芯片的器件。半导体芯片可以具有不同类型，可以利用不同技术而制造，并可以包括例如集成电路、光电电路或机电电路或者无源电路（passive）。例如，集成电路可以被设计为逻辑集成电路、模拟集成电路、混合信号集成电路、功率集成电路、存储电路或集成无源电路。此外，半导体芯片可以被配置为所谓的MEMS（微机电系统）并可以包括微机械结构，如桥、膜、舌结构。半导体芯片可以被配置为传感器或促动器，例如压力传感器、加速传感器、旋转传感器、磁场传感器、电磁场传感器、麦克风等。半导体芯片不需要由特定半导体材料（如Si、SiC、SiGe、GaAs）制造，此外可以包含非半导体的无机和/或有机材料（如绝缘体、塑料或金属）。此外，半导体芯片可以是封装的或未封装的。
具体地，可以涉及具有垂直结构的半导体芯片，即，半导体芯片可以被制造为使得电流可以沿与半导体芯片的主表面垂直的方向流动。具有垂直结构的半导体芯片可以具有具体处于其两个主表面上（即，处于其顶侧和底侧上）的接触元件。具体地，功率半导体芯片可以具有垂直结构。例如，垂直功率半导体芯片可以被配置为功率MOSFET（金属氧化物半导体场效应晶体管）、IGBT（绝缘栅双极晶体管）、JFET（结型场效应晶体管）、功率双极晶体管或功率二极管。作为示例，功率MOSFET的源电极和栅电极可以位于一个主表面上，而功率MOSFET的漏电极布置于另一个主表面上。此外，以下描述的器件可以包括用于对功率半导体芯片的集成电路进行控制的集成电路。
半导体芯片可以具有允许与半导体芯片中包括的集成电路进行电接触的电极（或者接触元件或接触板）。可以对电极施加一个或多个金属层。金属层可以利用任何期望的几何形状和任何期望的材料成分而制造。例如，金属层可以采用覆盖区域的层的形式。任何期望的金属或金属合金（例如铝、钛、金、银、铜、钯、铂、镍、铬或镍钒）可以用作所述材料。金属层不需要是同质的或由仅一种材料制造，即，金属层中可能包含各种成分和浓度的材料。
器件可以包含一个或多个导电层，例如金属层。例如，导电层可以用于产生再分布层。导电层可以用作布线层，以从器件外与半导体芯片进行电接触或与器件中包含的其他半导体芯片和/或组件进行电接触。导电层可以利用任何期望的几何形状和任何期望的材料成分而制造。例如，导电层可以整个由金属或金属合金构成。例如，导电层可以被加工为导体迹线，但还可以采用覆盖区域的层的形式。任何期望的金属（例如铜、铝、镍、钯、银、锡或金）、金属合金或金属堆叠可以用作材料。导电层不需要是同质的或由仅一种材料制造，即，导电层中可能包含各种成分和浓度的材料。此外，导电层可以布置于电绝缘层之上、之下或之间。可以规定，至少一个导电层通过等离子体沉积方法而产生。
半导体芯片或半导体芯片的至少部分可以利用电绝缘材料而覆盖。电绝缘材料可以覆盖器件的组件的任何数目的表面的任意一小部分。电绝缘材料可以提供各种功能。例如，其可以用于将器件的组件彼此电绝缘和/或与外部组件电绝缘，而电绝缘材料还可以用作平台以安装其他组件（如布线层）。电绝缘材料可以用于产生扇出（fan-out）类型的封装。在扇出类型的封装中，外部接触元件和/或将半导体芯片连接至外部接触元件的导体迹线中的至少一些横向地位于半导体芯片的轮廓外，或者至少与半导体芯片的轮廓交叉。因此，在扇出类型的封装中，典型地（附加地），半导体芯片的封装的外围部分用于将该封装电键合至外部应用，如应用板等。相对于半导体芯片的覆盖区（footprint），包围半导体芯片的封装的该外部部分有效地扩大了封装的接触面积，从而导致针对后续加工（例如第二级组装）在封装焊盘大小和间距（pitch）方面的约束放宽。
电绝缘材料和/或导电材料可以使用等离子体沉积方法而沉积。为此目的，可以生成等离子体射流（jet）并且可以将其与包含电绝缘材料和/或导电材料的载气进行混合。通过将等离子体射流与载气进行混合，激活了载气或者生成了撞击半导体芯片的粒子束。可以在与等离子体射流的生成物理分离的反应室中将等离子体射流与载气进行混合。相同的等离子体沉积设备可以用于电绝缘材料和导电材料的沉积。
以下描述的器件包括外部接触元件，其可以具有任何形状、大小和材料。外部接触元件可以是可从器件外接近的，从而可以允许从器件外与半导体芯片进行电接触。此外，外部接触元件可以进行热传导，并可以用作用于耗散由半导体芯片生成的热量的散热器。外部接触元件可以由任何期望的导电材料构成。外部接触元件可以包括外部接触焊盘。焊接材料可以沉积在外部接触焊盘上。焊接材料可以具有焊球的形状，并可以例如由SnPb、SnAg、SnAgCu、SnAgCuNi、SnAu、SnCu和/或SnBi构成。
图1A至1C示意性地示出了制造器件100的方法的横截面视图，器件100在图1C中示出。如图1A所示提供了半导体芯片10。半导体芯片10具有第一主表面11和与第一表面11相对的第二主表面12。如图1B所示，电绝缘材料13沉积在半导体芯片10的第一主表面11上。如图1C所示，导电材料14沉积在半导体芯片10的第二主表面12上。根据一个实施例，电绝缘材料13使用等离子体沉积方法而沉积。根据一个实施例，导电材料14使用等离子体沉积方法而沉积。根据一个实施例，电绝缘材料13和导电材料14使用等离子体沉积方法而沉积。
图2示意性地示出了器件200的横截面视图。器件200包括半导体芯片10，半导体芯片10具有第一主表面11和与第一主表面11相对的第二主表面12。电绝缘材料13覆盖半导体芯片10的第一主表面11，并且导电材料14覆盖半导体芯片10的第二主表面12。根据一个实施例，电绝缘材料13是等离子体沉积的。根据一个实施例，导电材料14是等离子体沉积的。根据一个实施例，电绝缘材料13和导电材料14这二者都是等离子体沉积的。
图3A至3J示意性地示出了制造器件300的方法的一个实施例的横截面视图，器件300在图3J中示意。图3A至3J所示的制造方法是图1A至1C所示的制造方法的实现。因此，制造方法的下述细节同样可以应用于图1A至1C的方法。此外，器件300是图2所示的器件200的实现。因此，器件300的下述细节同样可以应用于器件200。器件100、200和300的相似或相同组件由相同的附图标记表示。
图3A示出了提供了载体20。载体20可以是由刚性金属（例如金属或金属合金，如铜、铝、镍、CuFeP、钢或不锈钢、层压材料、薄膜、聚合物复合材料、陶瓷或材料堆叠）制造的板或箔。载体20可以具有半导体芯片10可稍后置于其上的平坦上表面。载体20的形状不限于任何几何形状，并且载体20可以具有任何适当大小。例如，载体20的厚度可以处于从50 μm至1 mm的范围内。聚合箔21（例如双侧胶带）可以置于载体20的上表面上。
图3B示出了两个半导体芯片10以及可能的另外半导体芯片10置于聚合箔21上。半导体芯片10的任何合适阵列可以置于聚合箔21上（仅两个半导体芯片10在图3B中示出）。例如，多于50或500或100个半导体芯片10可以置于聚合箔21上。半导体芯片10以与其在晶片键合中相比更大的间隔重新定位于聚合箔21上。半导体芯片10可能已经在相同的半导体晶片上制造，但是可替换地可能已经在不同的晶片上制造。此外，半导体芯片10可以在物理上相同，而还可以包含不同的集成电路和/或表示其他组件和/或可以具有不同的外部尺寸度量和/或几何结构。半导体芯片10可以具有厚度d1（第一主表面11与第二主表面12之间的距离），其在20 μm与几百微米之间的范围内，具体地在从50 μm至100 μm的范围内。
每个半导体芯片10具有第一主表面11、与第一主表面11相对的第二主表面以及从第一主表面11延伸至第二主表面12的侧表面23。半导体芯片10可以置于聚合箔21上，其中，其第二主表面12面向聚合箔21，并且其第一主表面11背向聚合箔21。
半导体芯片10可以是功率半导体芯片，并且可以在第一主表面11上具有第一电极24以及在第二主表面12上具有第二电极25。例如，功率半导体芯片10可以是功率二极管或功率晶体管，如功率MOSFET、IGBT、JFET或功率双极晶体管。在功率MOSFET的情况下，如图3B中示例性地示出，第一和第二电极24和25可以分别是源和漏电极（负载电极）。此外，在功率半导体芯片10是功率MOSFET的情况下，功率半导体芯片10可以在其第一主表面11上具有作为栅电极（控制电极）工作的第三电极26。在操作期间，高达5、50、100、500或1000 V甚至更高的电压可以施加在负载电极24和25之间。对控制电极26施加的切换频率可以处于从1 kHz至100 MHz的范围内，但还可以处于该范围之外。
可以对在半导体芯片10的背向聚合箔21的第一主表面11上布置的电极24、26施加金属层27。金属层27可以是在半导体芯片10仍处于晶片键合中时制造的。金属层27可以形成电极24和26上的接触焊盘。任何期望的金属或金属合金（包括例如铝、钛、金、银、铜、钯、铂、镍、铬或镍钒）可以用作材料。金属层27可以具有厚度d2，其在从3 μm至50 μm的范围内，具体地在从5 μm至30 μm的范围内。
可以与每个半导体芯片10相邻地放置柱（post）28。柱28可以由金属或金属合金（如铜或铝）制造。柱28可以具有高度d3，其在从20 μm至200 μm的范围内，具体地在从80 μm至120 μm的范围内。根据一个实施例，柱38具有与具有金属层27的半导体芯片10相似或相同的高度，例如，d3 = d1 + d2 ± 5 μm或d3 = d1 + d2。
可以使用拾放（pick-and-place）机，其能够拾取半导体芯片10和柱28并将其放置在聚合箔21上。包括载体20、聚合箔21、半导体芯片10和柱28的工件19可以用于下一加工步骤。
图3C示出了通过大气压等离子体沉积方法而沉积在半导体芯片10和柱28上的电绝缘材料13。为此目的，工件19可以置于如图5中示意性地示出的等离子体沉积设备中。在等离子体沉积期间，通常达不到高于150℃的温度。因此，聚合箔21以及半导体芯片10的第二主表面12上的金属层27不受等离子体沉积的影响。例如，电绝缘材料13可以是聚合物或陶瓷材料。电绝缘材料13可以覆盖金属层27、柱28、半导体芯片10的侧表面23和聚合箔21的暴露部分。由电绝缘材料13形成的层可以具有与载体20的上表面共面的上表面。由电绝缘材料13制造的层的厚度d4（从聚合箔21的上表面至电绝缘材料13的上表面测量）可以处于从30 μm至200 μm的范围内，具体地处于从80 μm至120 μm的范围内。可替换地，厚度d4可以大于60 μm或70 μm或80 μm或90 μm或100 μm。厚度d4可以大于或等于具有金属层27的半导体芯片10的厚度，即，d4 ≥ d1 + d2。厚度d4还可以大于或等于柱28的高度d3，即，d4 ≥ d3。
图3D示出了可以使电绝缘材料13的层变薄直到金属层27和柱28的上表面暴露为止。为此目的，可以部分地去除电绝缘材料13，例如通过研磨和抛光。在变薄步骤之后，电绝缘材料13的上表面29（也是金属27和柱28的上表面）可以是实质上平坦的并与载体20的上表面共面。
图3E示出了通过聚合箔31而附着至电绝缘材料13的平坦表面29的载体30。与载体20类似，载体30可以是由刚性金属（例如金属或金属合金，如铜、铝、镍、CuFeP、钢或不锈钢、层压材料、薄膜、聚合物复合材料、陶瓷或材料堆叠）制造的板或箔。载体30可以具有附着至电绝缘材料13的表面29的平坦表面。在附着至电绝缘材料13之前，聚合箔31（例如双侧胶带）可能已经附着至载体30。
图3F示出了载体20和聚合箔21从电绝缘材料13、半导体芯片10和柱28释放（release）。聚合箔21可以对UV光敏感并可以通过暴露于UV光而释放。此外，聚合箔21可以具有热释放属性，这允许在热处理期间去除聚合箔21。
在去除载体20和聚合箔21之后，电绝缘材料13的平坦表面32暴露。平坦表面32与平坦表面29相对。包括半导体芯片10的第二电极25的第二主表面12以及柱28的表面也暴露在平坦表面32上。载体30可以在后续加工步骤中实现对包括半导体芯片10、柱28和电绝缘材料13的工件33的处理。
图3G示出了通过大气压等离子体沉积方法而沉积在工件33的平坦表面32上且覆盖电绝缘材料13、半导体芯片10和柱28的已暴露表面的导电材料14。为此目的，工件33可以置于等离子体沉积设备中，该等离子体沉积设备可以是用于电绝缘材料13的沉积的相同设备。
例如，导电材料14可以整个由金属或金属合金（例如铜、铝、镍、钯、银、锡或金）构成。由导电材料14制造的层的厚度d5可以处于从30 μm至150 μm的范围内，具体地，可以大于30 μm或40 μm或50 μm或60 μm或70 μm或80 μm。
导电层14可以电连接至半导体芯片10的第二电极25以及柱28。由于等离子体沉积工艺，导电层14表现出特定多孔性（porosity）。
在导电层14的沉积之后，载体30和聚合箔31从电绝缘材料13的表面29释放。聚合箔31可以对UV光敏感并通过暴露于UV光而释放。可替换地，聚合箔31可以具有热释放属性，这允许在热处理期间去除聚合箔31。电绝缘材料13、金属层27和柱28的现在暴露的平坦表面29可以用作平台以沉积再分布层。
图3H示出了对电绝缘材料13的表面29施加且电连接至金属层27和柱28的种子层40。此外，种子层40被构造为生成如图3H所示的导体迹线。例如，种子层40可以由钛、钛钨或钯构成。种子层40的沉积可以通过来自一种溶液的无电镀沉积或者通过溅射而执行。种子层40可以具有厚度d6，其在从10 nm至300 nm的范围内。
图3I示出了可电沉积到种子层40上的金属层41。种子层40可以用作用于电沉积金属层41的电极。金属层41可以具有厚度d7，其大于1 μm，具体地为几微米。
图3J示出了通过将电绝缘材料13和导电材料14分离（例如，通过锯、切、研磨、蚀刻或激光束）来将器件300彼此分离。
金属层41的部分分别形成外部接触元件42、43和44。外部接触元件42经由金属层27电耦合至半导体芯片10的第一电极24。外部接触元件43经由柱28和导电层14电耦合至半导体芯片10的第二电极25。外部接触元件44经由金属层27电耦合至半导体芯片10的第三电极26。
通过上述方法制造的器件300是扇出类型的封装。电绝缘材料13允许再分布层延伸至半导体芯片10的轮廓之外。因此，外部接触元件42、43和44不需要布置在半导体芯片10的轮廓内，而是可以分布在更大的区域上。外部接触元件42、43和44中的至少一些可以完全布置在半导体芯片10的轮廓之外。由于电绝缘材料13而使可用于布置外部接触元件42、43和44的区域增大意味着：外部接触元件42、43和44不仅能以彼此间较大的距离布置，而且与所有外部接触元件42、43和44布置在半导体芯片10的轮廓内的情形相比，可布置在所述区域处的外部接触元件42、43和44的最大数目同样增加。
对于本领域技术人员来说显而易见，如上所述的图3J所示的器件300及其制造仅意在作为示例性实施例，许多变型是可能的。例如，不同类型的另外半导体芯片或无源电路可以包括在相同器件300中。半导体芯片和无源电路可以在功能、大小、制造技术等方面不同。此外，再分布层可以包括另外的金属层。
根据一个实施例，可以通过大气压等离子体沉积方法来沉积形成再分布层的（一个或多个）金属层。具体地，与用于沉积导电材料14的设备相同的等离子体沉积设备可以用于该目的。
根据一个实施例，在沉积导电材料14和释放载体30之后执行使如图3D所示的电绝缘材料13变薄。
根据一个实施例，通过在电绝缘材料13中产生孔以及将导电材料沉积在该孔中来制造穿过电绝缘材料13的导电通孔（作为柱28的替换）。
图4示意性地示出了包括安装在电路板50（如印制电路板（PCB））上的器件300的系统400。器件300的外部接触元件42、43和44可以面向电路板50。电路板50可以具有接触焊盘51，并且外部接触元件42、43和44可以通过焊接沉积物52焊接至接触焊盘51。
图5示意性地示出了等离子体沉积设备500。等离子体沉积设备500可以用于沉积如图3C和3G所示的电绝缘材料13和/或导电材料14。
等离子体沉积设备500由等离子体射流（或者束）生成器60和与等离子体射流生成器60物理分离的反应室61构成。
等离子体射流生成器60包括介电阻挡（barrier）62（如电绝缘管）、同中心地围绕介电阻挡62的外部电极63以及至少部分地容纳于介电阻挡62内的内部电极64。等离子体射流生成器60在一端以等离子体头65完成。
当操作等离子体射流生成器60时，通过对两个电极63和64施加适当的电压来生成辉光放电。在图5中箭头66所指示的方向上提供工艺气体，从而生成等离子体射流67。等离子体射流67经由等离子体头65离开等离子体射流生成器60。
等离子体射流生成器60经由反应室61中的开口68连接至反应室61，以允许等离子体射流67流入反应室61。开口68可以对等离子体头65的开口密封，以避免环境空气进入反应室61。反应室61与等离子体射流67的生成物理分离。
反应室61具有入口69，入口69允许载气70被吹入反应室61。将载气70引入反应室61并将其与所生成的等离子体射流67进行混合，从而激活载气70或生成粒子束。激活的载气71经由出口72离开反应室61。工件73（例如，图3B和3F的工件19和33之一）被定位为使得激活的载气71涂覆工件73的表面。
如图5所示，可以对等离子体射流67横向地布置载气70的入口69，从而将载气70引入反应室61，使等离子体射流67得以涡旋或偏转。
载气70包含要沉积在工件73（即，电绝缘材料13或导电材料14）上的粒子。在反应室61中将载气70中的气流和/或粒子流与等离子体射流67进行混合。从而，将等离子体射流67的能量的大部分转移至载气70中的气流和/或粒子流。因此，等离子体射流67的仅非常小的部分与工件73的表面形成接触。
可以将环境空气从反应室61中排除，例如通过施加合适的压力。这避免了环境空气、等离子体射流67和载气70之间的不期望的副作用。
等离子体沉积设备500允许产生等离子体沉积材料的厚层，该等离子体沉积材料可以是电绝缘的或导电的。可以通过等离子体沉积设备500来产生比30 μm或40 μm或50 μm或60μm或70μm或80 μm或更高厚度更厚的层。
等离子体沉积设备500可以用于创建等离子体聚合层。在等离子体聚合工艺中，被泵入反应室61的载气70包含单体气体。单体可以开始作为液体，并在被泵入反应室61之前在蒸发器中被转换为气体。在反应室61中，等离子体射流67电离单体分子。单体分子分裂（分馏（fractionate）），从而产生自由电子、离子、受激分子和自由基。自由基在衬底73上吸收、缩聚和聚合。电子和离子交联或产生与已沉积分子的化学键。由于单体被分馏至不同的反冲粒子中，因此仅部分地维持载气70的化学结构，从而导致交联以及聚合层的随机结构。等离子体聚合还可以用于产生不在正常化学聚合条件下聚合的有机化合物的聚合物层，不在正常化学聚合条件下聚合是由于这种工艺涉及化学反应的电子碰撞解离和电离。
可以通过使用单体的等离子体聚合来制备电绝缘层13，这些单体包括例如四乙氧基硅烷（TEOS）、六甲基二硅氧烷（HMDSO）、四甲基硅烷、乙烯基三甲基硅烷、顺丁烯二酸酐、六氟丙烯（HFP）、四氟乙烯（TFE）、氯乙烯、环氧化合物和/或任何其他适当的化合物。
图6示出了通过与图5所示的等离子体沉积设备类似的等离子体沉积设备而沉积的铜层的电子显微图像。从图6中可见，铜层表现出由于等离子体沉积而引起的特定多孔性。
此外，尽管可能已经参照多个实施方式中的仅一个实施方式公开了本发明实施例的特定特征或方面，但是如对于任何给定的或特定的应用来说可能期望且有利的，可以将这种特征或方面与其他实施方式的一个或多个其他特征或方面进行组合。此外，在详细描述或权利要求中使用术语“包含”、“具有”、“具备”或其变型这方面来说，这些术语意在以与术语“包括”类似的方式是包含性的。此外，应当理解，可以在分立的电路、部分集成的电路或全部集成的电路或者编程装置中实现本发明的实施例。此外，术语“示例性”仅表示作为示例，而不是最佳或最优。还应当认识到，为了简明和易于理解，利用相对于彼此而言特定的规模示出了这里所示的特征和/或元素，并且，实际规模可以与这里示出的规模实质上不同。
尽管这里示出并描述了具体实施例，但是本领域技术人员应当认识到，在不脱离本发明的范围的前提下，可以利用多种替换和/或等同替换实施方式代替所示出和描述的具体实施例。本申请意在涵盖这里讨论的具体实施例的任何改编或变型。因此，意图是本发明仅由权利要求及其等同替换方式来限定。

Claims (20)

1.一种方法，包括：
提供半导体芯片，所述半导体芯片具有第一主表面和与所述第一主表面相对的第二主表面；
使用等离子体沉积方法将电绝缘材料沉积在所述半导体芯片的第一主表面上；
使用等离子体沉积方法将第一导电材料沉积在所述半导体芯片的第二主表面上；
将第二导电材料沉积在所述电绝缘材料之上；以及
在所述电绝缘材料中形成导电通孔，其中，所述导电通孔将由所述第一导电材料形成的层电耦合至由所述第二导电材料形成的层。
2.根据权利要求1所述的方法，其中，所述电绝缘材料的层具有至少20 μm的厚度。
3.根据权利要求1所述的方法，其中，所述第一导电材料的层具有至少20 μm的厚度。
4.根据权利要求1所述的方法，其中，所述半导体芯片在所述第一主表面上具有第一电极并在所述第二主表面上具有第二电极。
5.根据权利要求4所述的方法，还包括：对所述半导体芯片的第一电极施加金属层。
6.根据权利要求5所述的方法，还包括：在沉积所述电绝缘材料之后，部分地去除所述电绝缘材料，直到所述金属层部分地暴露为止。
7.根据权利要求1所述的方法，其中，所述半导体芯片具有侧表面，并且，其中沉积所述电绝缘材料还包括将所述电绝缘材料沉积在所述侧表面上。
8.根据权利要求1所述的方法，还包括：在沉积所述电绝缘材料之前，将所述半导体芯片置于载体上。
9.根据权利要求8所述的方法，还包括：在沉积所述电绝缘材料之后去除所述载体。
10.根据权利要求1所述的方法，还包括：由所述第二导电材料形成外部接触元件。
11.根据权利要求1所述的方法，
其中，提供半导体芯片包括提供多个半导体芯片，每个半导体芯片具有第一主表面和与所述第一主表面相对的第二主表面；
其中，沉积电绝缘材料包括将所述电绝缘材料沉积在所述多个半导体芯片中的每一个的第一主表面上；以及
其中，沉积第一导电材料包括将所述第一导电材料沉积在多个其他半导体芯片中的每一个的第二主表面上。
12.根据权利要求1所述的方法，其中，所述电绝缘材料和/或所述第一导电材料是通过以下操作来沉积的：生成等离子体射流并将所述等离子体射流与载气进行混合，从而激活所述载气或生成撞击所述半导体芯片的第一和第二主表面中的至少一个的粒子束。
13.根据权利要求12所述的方法，其中，所述电绝缘材料和/或所述第一导电材料是通过以下操作来沉积的：生成等离子体射流并将所述等离子体射流与载气进行混合，从而激活所述载气，其中，所述等离子体射流是在与等离子体射流的生成物理分离的反应室中与所述载气进行混合的。
14.根据权利要求12所述的方法，其中，所述电绝缘材料和所述第一导电材料是使用相同的等离子体沉积设备来沉积的。
15.一种方法，包括：
提供半导体芯片，所述半导体芯片具有第一主表面和与所述第一主表面相对的第二主表面；
将电绝缘材料沉积在所述半导体芯片的第一主表面上；
将第一导电材料沉积在所述半导体芯片的第二主表面上；
将第二导电材料沉积在所述电绝缘材料之上；以及
在所述电绝缘材料中形成导电通孔，其中，所述导电通孔将由所述第一导电材料形成的层电耦合至由所述第二导电材料形成的层，其中
所述电绝缘材料和/或所述第一导电材料是通过以下操作来沉积的：生成等离子体射流并将所述等离子体射流与载气进行混合，从而激活所述载气或生成分别撞击所述半导体芯片的第一主表面和/或第二主表面的粒子束。
16.一种方法，包括：
提供半导体芯片，所述半导体芯片具有第一主表面和与所述第一主表面相对的第二主表面；
将所述半导体芯片置于载体上；
使用等离子体沉积方法将电绝缘材料沉积在所述半导体芯片的第一主表面以及所述载体上；
去除所述载体，从而暴露所述电绝缘材料的表面；
使用等离子体沉积方法将第一导电材料沉积在所述电绝缘材料的暴露表面以及所述半导体芯片的第二主表面上；
将第二导电材料沉积在所述电绝缘材料之上；以及
在所述电绝缘材料中形成导电通孔，其中，所述导电通孔将由所述第一导电材料形成的层电耦合至由所述第二导电材料形成的层。
17.一种器件，包括：
半导体芯片，具有第一主表面和与所述第一主表面相对的第二主表面；
等离子体沉积电绝缘材料，覆盖所述半导体芯片的第一主表面；
等离子体沉积第一导电材料，覆盖所述半导体芯片的第二主表面；
与所述电绝缘材料相邻的第二导电材料；以及
在所述电绝缘材料中形成的导电通孔，所述导电通孔将所述第一导电材料电耦合至所述第二导电材料。
18.根据权利要求17所述的器件，其中，所述电绝缘材料具有至少20 μm的厚度。
19.根据权利要求17所述的器件，其中，所述第一导电材料具有至少20 μm的厚度。
20.根据权利要求17所述的器件，其中，所述半导体芯片在所述第一主表面上具有第一电极并在所述第二主表面上具有第二电极。
CN201110306014.2A 2010-10-11 2011-10-11 包括半导体芯片的器件的制造 Expired - Fee Related CN102446837B (zh)

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