CN102428022B - 使用分段预图案的定向自组装嵌段共聚物 - Google Patents
使用分段预图案的定向自组装嵌段共聚物 Download PDFInfo
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- CN102428022B CN102428022B CN201080021334.7A CN201080021334A CN102428022B CN 102428022 B CN102428022 B CN 102428022B CN 201080021334 A CN201080021334 A CN 201080021334A CN 102428022 B CN102428022 B CN 102428022B
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- 125000000959 isobutyl group Chemical group [H]C([H])([H])C([H])(C([H])([H])[H])C([H])([H])* 0.000 description 1
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- 125000001971 neopentyl group Chemical group [H]C([*])([H])C(C([H])([H])[H])(C([H])([H])[H])C([H])([H])[H] 0.000 description 1
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- JFNLZVQOOSMTJK-KNVOCYPGSA-N norbornene Chemical compound C1[C@@H]2CC[C@H]1C=C2 JFNLZVQOOSMTJK-KNVOCYPGSA-N 0.000 description 1
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- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229920000428 triblock copolymer Polymers 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00404—Mask characterised by its size, orientation or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0147—Film patterning
- B81C2201/0149—Forming nanoscale microstructures using auto-arranging or self-assembling material
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Nanotechnology (AREA)
- Analytical Chemistry (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
Abstract
Description
Claims (22)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/468,391 US8398868B2 (en) | 2009-05-19 | 2009-05-19 | Directed self-assembly of block copolymers using segmented prepatterns |
US12/468,391 | 2009-05-19 | ||
PCT/EP2010/055412 WO2010133422A2 (en) | 2009-05-19 | 2010-04-23 | Directed self-assembly of block copolymers using segmented prepatterns |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102428022A CN102428022A (zh) | 2012-04-25 |
CN102428022B true CN102428022B (zh) | 2015-04-15 |
Family
ID=43123882
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201080021334.7A Active CN102428022B (zh) | 2009-05-19 | 2010-04-23 | 使用分段预图案的定向自组装嵌段共聚物 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8398868B2 (zh) |
EP (1) | EP2379441B1 (zh) |
JP (1) | JP5596133B2 (zh) |
CN (1) | CN102428022B (zh) |
TW (1) | TW201115622A (zh) |
WO (1) | WO2010133422A2 (zh) |
Families Citing this family (63)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CH699836B1 (de) * | 2007-09-18 | 2010-05-14 | Ct Concept Holding Ag | Leiterkarte und Verfahren zum Herstellen einer solchen Leiterkarte. |
US8114306B2 (en) * | 2009-05-22 | 2012-02-14 | International Business Machines Corporation | Method of forming sub-lithographic features using directed self-assembly of polymers |
JP5537400B2 (ja) * | 2010-12-22 | 2014-07-02 | 株式会社東芝 | パターン形成方法及び装置 |
KR20120126725A (ko) | 2011-05-12 | 2012-11-21 | 에스케이하이닉스 주식회사 | 반도체 소자의 형성 방법 |
FR2975823B1 (fr) * | 2011-05-27 | 2014-11-21 | Commissariat Energie Atomique | Procede de realisation d'un motif a la surface d'un bloc d'un substrat utilisant des copolymeres a bloc |
KR101963924B1 (ko) * | 2011-07-29 | 2019-03-29 | 위스콘신 얼럼나이 리서어치 화운데이션 | 박막의 유도 조립을 위한 블록 공중합체 재료 |
US8728714B2 (en) | 2011-11-17 | 2014-05-20 | Micron Technology, Inc. | Methods for adhering materials, for enhancing adhesion between materials, and for patterning materials, and related semiconductor device structures |
US20130200498A1 (en) * | 2012-02-03 | 2013-08-08 | Applied Materials, Inc. | Methods and apparatus for lithography using a resist array |
JP5979660B2 (ja) * | 2012-02-09 | 2016-08-24 | 東京応化工業株式会社 | コンタクトホールパターンの形成方法 |
CN104105750A (zh) | 2012-02-10 | 2014-10-15 | 纳幕尔杜邦公司 | 高-x两嵌段共聚物的制备、纯化和使用 |
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