CN102412220A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN102412220A
CN102412220A CN2011102763136A CN201110276313A CN102412220A CN 102412220 A CN102412220 A CN 102412220A CN 2011102763136 A CN2011102763136 A CN 2011102763136A CN 201110276313 A CN201110276313 A CN 201110276313A CN 102412220 A CN102412220 A CN 102412220A
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mentioned
semiconductor device
solder bump
diameter
convexity
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CN2011102763136A
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右田达夫
江泽弘和
山下创一
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Toshiba Corp
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Toshiba Corp
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Publication of CN102412220A publication Critical patent/CN102412220A/zh
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Abstract

本发明的半导体装置具备多个焊料凸起，其在半导体基板上以小于等于40μm的节距并列的多个电极衬垫上经由凸起下金属分别与相应的电极衬垫电连接。上述焊料凸起的距离上述半导体基板最远的部分的直径和该焊料凸起的底边的直径的比值是1∶1～1∶4。

Description

半导体装置及其制造方法
相关申请的引用
本申请要求2010年9月22日提出的日本专利申请第2010-212781号的优先权，该日本专利申请的全部内容在本申请中被引用。
技术领域
本发明的实施方式一般涉及半导体装置及其制造方法。
背景技术
近年来，为了实现半导体器件的高集成化和高功能化，要求提高器件的工作速度和/或存储器的大容量。根据器件，还开发了变成单芯片的eDRAM并将逻辑电路和大容量DRAM以叠层芯片(CoC)连接的方式封装的芯片。
在形成CoC连接用的微小凸起时，考虑到CoC性能，存在要求高的深宽比的凸起的情况。此时，经由Cu、Ni、Au等柱状物形成焊料凸起。关于CoC连接，其凸起节距近年来向微细化进展，正在成为40μm、30μm。
发明内容
本发明的实施方式的半导体装置具有多个焊料凸起，其在半导体基板上以小于等于40μm的节距并列的多个电极衬垫上经由凸起下金属分别与相应的电极衬垫电连接。上述焊料凸起的距离上述半导体基板最远的部分的直径与该焊料凸起的底边的直径的比值是1∶1～1∶4。
本实施方式提供具有与凸起节距的超微细化对应的高可靠性的焊料凸起的半导体装置及其制造方法。
附图说明
图1A是表示第1实施方式的半导体装置及其制造方法的图。
图1B是表示第1实施方式的半导体装置及其制造方法的图。
图1C是表示第1实施方式的半导体装置及其制造方法的图。
图2A是表示第2实施方式的半导体装置及其制造方法的图。
图2B是表示第2实施方式的半导体装置及其制造方法的图。
图2C是表示第2实施方式的半导体装置及其制造方法的图。
图3A是表示第3实施方式的半导体装置及其制造方法的图。
图3B是表示第3实施方式的半导体装置及其制造方法的图。
具体实施方式
以下参照附图对实施方式所涉及的半导体装置及其制造方法进行详细地说明。另外，本发明并不由这些实施方式限定。
第1实施方式
图1A～图1C是表示第1实施方式的半导体装置及其制造方法的剖面图。在本实施方式中，在通过传统的LSI形成技术制成的硅基板上形成微小的焊料凸起。
首先，如图1A所示，例如，在基板1上形成铝的电极衬垫2，进而以使电极衬垫2的中心露出并覆盖电极衬垫2的边缘部和基板1的方式形成例如SiN膜3作为钝化膜。在此，在本实施方式中，电极衬垫2和未图示的相邻电极衬垫按小于等于40μm的间隔并列。在此之上，使用溅射法、CVD法、ALD(原子层沉积)法、电镀法等形成Cu膜或者Cu和Ti的叠层膜，作为焊料凸起的凸起下金属4(UBM)。
作为凸起下金属4的最上层，使用Cu，并具有后续工序即电镀工序的通电层的功能。接着，为了形成凸起图案，涂敷光致抗蚀剂5，将光掩膜6曝光成掩膜，并使用光刻技术形成所期望的凸起图案。作为光致抗蚀剂5，在此使用例如负性型抗蚀剂。
在此，光刻技术主要通过将曝光时的焦距(Focus)条件变成比通常的直线形状(图1A)大，形成特殊的开口形状，因此，将焦距值设定为16μm，形成凸起图案(图1B)。
然后，通过电解电镀在凸起图案部的凸起下金属4上析出Ni，形成Ni的柱状物7，接着通过电场电镀析出焊料8。接着，用剥离液除去光致抗蚀剂5，并通过蚀刻法除去凸起下金属4。其后，通过回流工序熔化焊料8，并再凝固形成焊料凸起8’。此时，通过将光刻工序从获得通常的直线形状的焦距值8μm变大到16μm并进行曝光，可获得如图1C所示的下摆宽的凸起形状。
一般地，随着将曝光时的焦距值从小的值改变到大的值，凸起形状的底面和侧面在凸起侧形成的角度(图1C的α)从大的值(大于等于90度)变成小的值(小于等于90度)。即使选择负性型和正性型抗蚀剂中的任意一种，也取决于抗蚀剂，确定α＝90度的焦距值。该焦距值是曝光成直线形状的焦距值。在本实施方式中，为了如图1C所示地成为α＜90度，以比曝光成直线形状的焦距值大的焦距值进行曝光。
得到了此时的凸起底部直径B比直线形状曝光时的20μm大3.6μm的形状。通过形成上述形状的焊料凸起8’，可以确保焊料8下面的柱状物7和基底的凸起下金属4之间的界面的底部面积增大约40％，并可以提高接触性。此外，对于小于等于40μm的凸起节距，由于能够确保焊料凸起8’的顶部直径T比底部直径B小，因此，能够降低其与相邻凸起的短路风险。根据上述结果，在凸起超微细化时，也能形成可靠性高的焊料凸起。在此，所谓顶部直径T，如图1B和图1C所示，是焊料凸起8’的距离半导体基板1最远的部分的直径，所谓底部直径B，同样如图1B和图1C所示，是焊料凸起8’的底边的直径。
另外，优选地，上述的顶部直径T和底部直径B的比值T∶B是1∶1～1∶4，或者凸起形状的底面和侧面在凸起侧形成的角度α是45度＜α＜90度。进一步地，优选地，比值T∶B和角度α二者都在上述的范围内。
在比值T∶B在上述范围以外且B比T小的情况下，或者在α是上述范围外的大于等于90度的情况下，凸起的底部直径B变小，并且与基底界面的接触面积变小。进一步地，凸起的顶部直径T相对地过于大，产生凸起连接时的短路风险增大的问题。
此外，相反地，在B比T的4倍大的情况下，或者在α是小于等于45度的情况下，凸起的底部直径B过于粗，相邻的凸起间的短路风险增大。进一步地，凸起顶部直径T过小，会产生凸起连接变得非常困难的问题。
进一步地，如果考虑提高凸起的集成度的情况等，则为了降低与相邻凸起的短路风险，顶部直径T与底部直径B的比值T∶B是1∶1～1∶3，或者凸起形状的底面和侧面在凸起侧形成的角度α是55度＜α＜90度更合适。此外，优选地，比值T∶B和角度α这二者都在上述的范围内。
如上所说明的，在设置了半导体元件的半导体基板上形成的本实施方式的凸起形成中，即使该凸起节距变成超微细图案，也能够提高其与基底的接触性，而且降低焊料凸起间的短路风险，提高半导体封装的可靠性。
第2实施方式
本发明的第2实施方式使用例如正性型抗蚀剂作为光致抗蚀剂5，并将光刻工序的曝光时的焦距值设定为比第1实施方式中的焦距值大的28μm(第1焦距值)(图2A)，进一步地，为了扩大抗蚀剂上部的开口，将焦距值设定为通常使用的条件的焦距值(第2焦距值)8μm，并进行二次曝光(图2B)。这样，与第1实施方式相比，能够形成焊料凸起8’与基底的凸起下金属4之间的界面的底部面积更大的焊料凸起8’。
得到了此时的凸起底部直径B比直线形状曝光时的20μm大16.0μm的形状。如图2C所示，通过形成上述形状的焊料凸起8’，能够确保焊料凸起8’与基底的凸起下金属4之间的界面的底部面积增大约220％，进一步提高接触性。
第3实施方式
本发明的第3实施方式与在通过光刻工序向所开口的凸起图案部的凸起下金属4上进行电解电镀而析出Ni的第1实施方式不同，其在凸起图案部的凸起下金属4上析出Cu而形成Cu柱状物9。进一步地，在其上形成Ni柱状物7，接着用剥离液除去光致抗蚀剂，并通过蚀刻法除去凸起下金属4(未图示)。
在此，作为凸起下金属4的电镀通电用材料，使用了Cu，因此，在蚀刻Cu的凸起下金属4时，也同时蚀刻了Cu柱状物9(图3A)。在通常的光刻的焦距值8μm下，Cu柱状物部分9变细，同时接触性降低，但是，在本实施方式中，焦距值设为16μm，比通常的大。因此，能够形成底部直径大的焊料凸起(图3B)。此外，如第2实施方式那样，能够通过二次曝光进一步地任意设定顶部和底部的形状。
另外，在上述实施方式中，虽然说明了使用负性型或正性型作为光致抗蚀剂5，但是，在各个实施例中，也可以使用负性型、正性型中的任意一种抗蚀剂。如上所述，即使选择负性型、正性型中的任意一种抗蚀剂，也取决于抗蚀剂，确定α＝90度的焦距值。此外，随着将曝光时的焦距值从小的值变到大的值，凸起形状的底面和侧面在凸起侧形成的角度(图1C的α)从大的值(大于等于90度)变到小的值(小于等于90度)的趋势是共同的。因此，通过将焦距值设置成比直线形状时的值大，能够取得与上述相同的效果。作为负性型抗蚀剂，可以使用橡胶系列、丙烯树脂系列的树脂等，作为正性型抗蚀剂，可以使用酚醛树脂系列的树脂等，但是并不限于这些。此外，作为焊料和柱状部等构成焊料凸起的材料，可以自由选择Ni、Cu、Au、Sn、Ag、Pb、Cr或其组合。
虽然对本发明的若干实施方式进行了说明，但这些实施方式仅作为例子而提出，并不用于限定本发明的范围。这些新颖的实施方式能够以其它各种方式实施，并在不脱离本发明的要旨的范围下进行各种省略、置换、变更。这些实施方式和/或其变形包含在本发明的范围和/或要旨内，并且包含在与权利要求书所记载的发明等同的范围内。

Claims (20)

1.一种半导体装置，其特征在于，具备：
多个焊料凸起，其在半导体基板上以小于等于40μm的节距并列的多个电极衬垫上经由凸起下金属分别与相应的电极衬垫电连接；
其中，上述焊料凸起的距离上述半导体基板最远的部分的直径(顶部直径)与该焊料凸起的底边的直径(底部直径)的比值是1∶1～1∶4。
2.如权利要求1所述的半导体装置，其特征在于，上述比值是1∶1～1∶3。
3.如权利要求1所述的半导体装置，其特征在于，上述焊料凸起是Ni、Cu、Au、Sn、Ag、Pb、Cr或其组合。
4.如权利要求1所述的半导体装置，其特征在于，上述凸起下金属是Cu膜或者Cu和Ti的叠层膜。
5.如权利要求1所述的半导体装置，其特征在于，上述焊料凸起的底边和该焊料凸起的侧面在该焊料凸起侧形成的角度是45度～90度。
6.如权利要求2所述的半导体装置，其特征在于，上述焊料凸起是Ni、Cu、Au、Sn、Ag、Pb、Cr或其组合。
7.如权利要求2所述的半导体装置，其特征在于，上述凸起下金属是Cu膜或者Cu和Ti的叠层膜。
8.一种半导体装置，其特征在于，具备：
多个焊料凸起，其在半导体基板上以小于等于40μm的节距并列的多个电极衬垫上经由凸起下金属分别与相应的电极衬垫电连接；
其中，上述焊料凸起的底边和该焊料凸起的侧面在该焊料凸起侧形成的角度是45度～90度。
9.如权利要求8所述的半导体装置，其特征在于，上述角度是55度～90度。
10.如权利要求8所述的半导体装置，其特征在于，上述焊料凸起是Ni、Cu、Au、Sn、Ag、Pb、Cr或其组合。
11.如权利要求8所述的半导体装置，其特征在于，上述凸起下金属是Cu膜或者Cu和Ti的叠层膜。
12.如权利要求8所述的半导体装置，其特征在于，上述焊料凸起的距离上述半导体基板最远的部分的直径(顶部直径)和该焊料凸起的底边的直径(底部直径)的比值是1∶1～1∶4。
13.如权利要求9所述的半导体装置，其特征在于，上述焊料凸起是Ni、Cu、Au、Sn、Ag、Pb、Cr或其组合。
14.如权利要求9所述的半导体装置，其特征在于，上述凸起下金属是Cu膜或者Cu和Ti的叠层膜。
15.一种半导体装置的制造方法，其特征在于，
在形成有以小于等于40μm的节距并列的多个电极衬垫和在该电极衬垫上层叠的凸起下金属的半导体基板上形成抗蚀剂膜，并以比在与上述抗蚀剂膜的表面垂直的方向曝光为直线形状的焦距值大的第1焦距值进行曝光。
16.如权利要求15所述的半导体装置的制造方法，其特征在于，进一步以曝光宽度比通过上述曝光而成为可溶性的上述抗蚀剂膜的凸起形状部分的距离上述半导体基板最远的部分的直径(顶部直径)大且比该凸起形状部分的底面的直径(底部直径)小的直线形状的第2焦距值进行曝光。
17.如权利要求15所述的半导体装置的制造方法，其特征在于，上述抗蚀剂膜是正性型抗蚀剂。
18.如权利要求15所述的半导体装置的制造方法，其特征在于，上述抗蚀剂膜为负性型抗蚀剂。
19.如权利要求15所述的半导体装置的制造方法，其特征在于，上述凸起下金属通过溅射法、CVD法、ALD(原子层沉积)法或电镀法形成。
20.如权利要求15所述的半导体装置的制造方法，其特征在于，上述凸起下金属是Cu膜或者Cu和Ti的叠层膜。
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