CN102376683A - 带有金属焊盘的密封圈结构 - Google Patents

带有金属焊盘的密封圈结构 Download PDF

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Publication number
CN102376683A
CN102376683A CN2011102248281A CN201110224828A CN102376683A CN 102376683 A CN102376683 A CN 102376683A CN 2011102248281 A CN2011102248281 A CN 2011102248281A CN 201110224828 A CN201110224828 A CN 201110224828A CN 102376683 A CN102376683 A CN 102376683A
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Prior art keywords
ring structure
metal pad
anterior
passivation layer
layer
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CN2011102248281A
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CN102376683B (zh
Inventor
林政贤
杨敦年
刘人诚
李新辉
王文德
蔡纾婷
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

方法包括提供具有密封圈区域和电路区域的基板，在密封圈区域上形成密封圈结构，在密封圈结构上形成第一前部钝化层，在第一前部钝化层中蚀刻邻近密封圈结构的外部的前部孔，在前部孔中形成前部金属焊盘以连接前部金属焊盘和密封圈结构的外部，在密封圈结构下形成第一背部钝化层，在第一背部钝化层中蚀刻邻近密封圈结构的外部的背部孔，和在背部孔中形成背部金属焊盘以连接背部金属焊盘和密封圈结构的外部。也提供了通过所述方法制造的半导体器件。

Description

带有金属焊盘的密封圈结构
优先权日
本申请要求2010年8月13日提交的美国临时申请序列号61/373,634号，代理人卷号24061.1553的优先权，其全部内容通过引用结合到本文中作为参考。
技术领域
本发明设计一种带有金属焊盘的密封圈结构及其制造方法。
背景技术
在半导体集成电路(ICs)的设计和封装中，有许多关注领域。需要防止水汽进入电路，因为：(1)水汽可能被困入到氧化物中从而增加其介电常数；(2)水汽可能在栅极氧化物中产生陷阱电荷中心从而导致互补-金属-氧化物半导体(CMOS)晶体管中的阈值电压漂移；(3)水汽可能在Si-栅极氧化物界面中产生界面态从而通过增加的热电子敏感性导致晶体管寿命的下降；(4)水汽可能导致金属互连的腐蚀，降低IC的可靠性；和(5)当被Si-氧化物捕集时，水汽可能降低氧化物的机械强度，因此在拉伸应力下氧化物可能变得更容易断裂。离子污染物也可能导致IC的损坏，因为它们可以迅速地扩散在氧化硅中。例如，离子污染物可以导致CMOS晶体管中的阈值电压不稳定以及改变离子污染物附近的Si表面的表面电势。使相邻的IC管芯互相分离的切割工艺也可能导致IC的潜在损伤。
在工业中使用密封圈以使IC避免水汽损害、离子污染和切割工艺，但是仍需要改进。特别地，使用机械管芯切割的切割工艺可能由于管芯切割的切削力导致层的脱落。尤其是具有层间金属或层间介电膜(介电常数(low-k)低)的背部照明器件更容易管芯切割脱落。因此，需要半导体器件制造的改进方法和通过这个方法制造的器件。
发明内容
针对现有技术中的问题，本发明提供了一种半导体器件，包括：
基板，所述基板具有密封圈区域和电路区域；
密封圈结构，位于所述密封圈区域上；
第一前部钝化层，位于所述密封圈结构上；
前部金属焊盘，在所述第一前部钝化层中，所述前部金属焊盘与所述密封圈结构的外部连接；
第二前部钝化层，位于所述前部金属焊盘上；
载具晶圆，与所述第二前部钝化层接合；和
第一背部钝化层，位于所述密封圈结构下面。
根据本发明所述的半导体器件，其中所述密封圈结构由围绕所述电路区域布置的金属层堆叠组成。
根据本发明所述的半导体器件，其中所述前部金属焊盘由铝组成。
根据本发明所述的半导体器件，其中所述第一前部钝化层和所述第一背部钝化层由氧化硅组成。
根据本发明所述的半导体器件，其中所述第二前部钝化层由氧化硅和/或氮化硅组成。
根据本发明所述的半导体器件，其中所述前部金属焊盘直接与所述密封圈结构的顶部金属层连接。
根据本发明所述的半导体器件，其中所述第一前部钝化层和所述第二前部钝化层由相同的材料或不同的材料组成。
根据本发明所述的半导体器件，还包括：
背部金属焊盘，位于所述第一背部钝化层中，所述背部金属焊盘与所述密封圈结构的外部连接；和
第二背部钝化层，位于所述背部金属焊盘下。
根据本发明所述的一种半导体器件，包括：
基板，具有密封圈区域和电路区域；
密封圈结构，位于所述密封圈区域中；
第一前部钝化层，位于所述密封圈结构上；
第一背部钝化层，位于所述密封圈结构下；
背部金属焊盘，在所述第一背部钝化层中，所述背部金属焊盘与所述密封圈结构的外部连接；和
第二背部钝化层，位于所述背部金属焊盘下面。
根据本发明所述的半导体器件，其中所述密封圈结构由围绕所述电路区域布置的金属层堆叠组成。
根据本发明所述的半导体器件，其中所述背部金属焊盘由铝组成。
根据本发明所述的半导体器件，其中所述背部金属焊盘或者直接与所述密封圈结构的底部金属层连接，或者与触点连接，所述触点与所述密封圈结构的底部金属层连接。
根据本发明所述的半导体器件，其中所述第一背部金属层由氧化硅组成，而且所述第二背部钝化层由氮化硅组成。
根据本发明所述的半导体器件，其中所述第一背部钝化层和所述第二背部钝化层由相同的材料或不同的材料组成。
根据本发明所述的半导体器件，还包括：
前部金属焊盘，在所述第一前部钝化层中，所述前部金属焊盘与所述密封圈结构的外部连接；
第二前部钝化层，位于所述前部金属焊盘和所述第一前部钝化层上；和
载具晶圆，与所述第二前部钝化层接合。
根据本发明所述的一种制造半导体器件的方法，所述方法包括：
提供具有密封圈区域和电路区域的基板；
形成在所述密封圈区域上的密封圈结构；
形成在所述密封圈结构上的第一前部钝化层；
蚀刻邻近所述密封圈结构的外部的所述第一前部钝化层中的前部孔；
形成在所述前部孔中的前部金属焊盘以连接所述前部金属焊盘和所述密封圈结构的外部；
形成在所述密封圈结构下的第一背部钝化层；
蚀刻邻近所述密封圈结构的外部的所述第一背部钝化层中的背部孔；和
形成在所述背部孔中的背部金属焊盘以连接所述背部金属焊盘和所述密封圈结构的外部。
根据本发明所述的方法，其中所述前部金属焊盘与所述密封圈结构的顶部金属层连接。
根据本发明所述的方法，其中所述背部金属焊盘与所述密封圈结构的底部金属层连接。
根据本发明所述的方法，还包括形成在所述前部金属焊盘上的第二前部钝化层和/或形成在所述背部金属焊盘下的第二背部钝化层。
根据本发明所述的方法，还包括晶圆接合载具晶圆和所述第二前部钝化层；和背面蚀刻所述基板。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1是根据本公开的各个方面，示出制造带有密封圈结构的半导体器件的方法的流程图，所述密封圈结构具有防止管芯切割脱落的金属焊盘。
图2是根据本公开的各个方面，示出带有密封圈结构的集成电路(IC)管芯的俯视图。
图3A和图3B是根据本公开的各个方面的，可选的密封圈部分沿着图2中的线I-I’的横截面视图。
图4是根据本公开的各个方面的器件的实施例的横截面视图，示出了受阻的管芯切割效应。
图5是以前的密封圈结构的横截面视图，示出了以前的半导体器件上的管芯切割效益。
图6A-图6F是根据本公开的各个方面的，在各个制造阶段的半导体器件的横截面视图。
具体实施方式
据了解为了实施本公开的不同部件，以下公开提供了许多不同的实施例或示例。以下描述元件和布置的特定示例以简化本公开。当然这些仅仅是示例并不打算限定。再者，以下描述中第一部件形成在第二部件上可包括其中第一和第二部件以直接接触形成的实施例，并且也可包括其中额外的部件形成插入到第一和第二部件中的实施例，使得第一和第二部件不直接接触。为了简明和清楚，可以任意地以不同的尺寸绘制各种部件。
参考附图，图1是根据本公开的各个方面，示出制造带有密封圈结构的半导体器件的方法100的流程图，所述密封圈结构包含防止或阻止器件上管芯切割脱落效应的金属焊盘。图2是根据本公开的各个方面，示出包括集成电路(IC)管芯和围绕IC管芯的密封圈结构的半导体器件的俯视图。图3A和图3B是根据本公开的各个方面，示出密封圈结构210的可选实施例的横截面视图。图4是根据本公开的各个方面的，图3的密封圈结构的实施例的横截面视图，其示出了半导体器件上受阻的管芯切割效应。相反地，图5示出了以前的密封圈结构的横截面视图，其示出了器件上的管芯切割脱落效应。图6A到图6F是根据本公开的各个方面，示出不同制造阶段的半导体器件的横截面视图。
应该注意到，为了简洁和清楚，相同的部件被相同地标号。还应该注意到，可以使用CMOS工艺流程制造一部分半导体器件200。因此，应该理解，可以在图1的方法100之前、中间、和之后提供额外的工艺，而且本文可以只简要地描述一些其它工艺。半导体器件200可以被制造成包含背部照明(BSI)器件，所述背部照明器件具有层间介质(ILD)，如低-k金属间介质(IMD)。
现参考图1，方法100开始于方框102，其中提供了包含密封圈区域和电路区域的半导体基板。在实施例中，密封圈区域围绕电路区域形成，而且密封圈区域是用于在其上形成密封圈结构，电路区域是用于在其中至少形成晶体管器件。方法100继续到方框104，其中集成电路形成在电路区域上而且密封圈结构形成在密封圈区域上。方法100继续到方框106，其中第一前部钝化层形成在密封圈区域的密封圈结构上，然后继续到方框108，其中在第一前部钝化层中邻近密封圈结构的外部蚀刻前部孔。方法继续到方框110，其中前部金属焊盘形成在第一前部钝化层的前部孔中，从而连接第一金属焊盘和密封圈结构的外部。在方框112中，第二前部钝化层形成在前部金属焊盘上，在方框114中，实施背部加工工艺，包括第二前部钝化层和载具晶圆的晶圆接合，和减薄基板的基板蚀刻。
方法100继续到方框116，其中第一背部钝化层形成在密封圈结构下，继续到方框118，其中在第一背部钝化层中邻近密封圈结构的外部蚀刻背部孔。在方框120中，背部金属焊盘形成在第一背部钝化层的背部孔中，从而连接背部金属焊盘和密封圈结构的外部。在方框122中，第二背部钝化层形成在背部金属焊盘下。也可以在方法100的步骤之前、中间或之后提供其它层、线、通孔、和结构。有利地，由于金属焊盘与密封圈结构的外部和它们各自的钝化层连接，因此阻挡管芯切割脱落效应影响密封圈结构的内部部分，因此也保护了集成电路。
现参考图2，根据本公开的各个方面示出了器件200的俯视图，其包括集成电路(IC)管芯202、围绕IC管芯202的密封圈结构210、和处于中间的组装隔离区域204。图3A和图3B示出了密封圈区域沿着线I-I’的可选横截面视图。
现结合图2参考图3A，示出了根据图1方法100制造半导体器件200的实施例的横截面视图。半导体器件200可以包括半导体基板230，如硅基板(如p-掺杂基板)所述基板包括密封圈区域201和围绕电路区域中IC管芯202的组装隔离区域204。在实施例中，密封圈区域201围绕电路区域形成，而且密封圈区域是用于在其上形成密封圈结构，电路区域是用于在其中至少形成晶体管器件。基板230可以可选地包括硅锗、砷化镓、或其它合适的半导体材料。基板230还可以包括掺杂区域，如P-阱、N-阱、和/或掺杂的有源区域如P+掺杂的有源区域。一方面，掺杂有源区域可以被配置在其它区域中。基板230还包括其它部件，如埋氧层、和/或外延层。另外，基板230可以是绝缘体上的半导体，如绝缘体上硅(SOI)。在其它实施例中，半导体基板230可以包括掺杂的外延层、梯度半导体层、和/或还可以包括半导体层覆盖在其它不同类型的半导体层上，如硅层在硅锗层上。在其它实施例中，化合物半导体基板可以包括多层硅结构，或硅基板可以包括多层化合物半导体结构。
器件200还可以包括隔离结构，如形成在基板230中的浅沟槽隔离(STI)部件或LOCOS部件，其用于隔离有源区域和基板的其它区域。在一个实例中，有源区域可以被配置成NMOS器件(如nFET)或PMOS器件(如pFET)。
器件200还可以包括覆盖基板230的虚拟栅极和/或栅极结构(未示出)，其可以由各种材料层和通过各种蚀刻/图案化技术形成在器件200的各个区域上。
器件200还包括触点条218，从而电连接有源区域和随后形成的密封圈结构210(包括外部210a和内部部分210b)。应该注意到，可以在密封圈区域中提供其它层，从而形成在密封圈结构上和/或下的各种部件，如通过CVD、旋压技术等等沉积的钝化层、氮化物层、和聚酰亚胺层。
半导体基板230还可以包括在先前工艺步骤中或在随后工艺步骤中形成的底层、覆层、器件、连接、和其它部件。
器件200包括位于基板230上，密封圈区域201中的密封圈结构210。在一个实施例中，密封圈结构210可以由各种堆叠导电层212和分布在介电层216中的通孔层214组成，并且可能具有约5微米和约15微米之间的宽度。密封圈结构210还包括邻近芯片边缘和切割槽的外部210a，和邻近组装隔离204和电路区域的内部部分210b。
第一前部钝化层226位于密封圈结构210上。在一个实施例中，可以通过高纵横比工艺(HARP)和/或高密度等离子体(HDP)CVD工艺沉积第一前部钝化层226。在一个实施例中，第一前部钝化层226包括电介质并且其为氧化物。
器件200还包括在第一前部钝化层226中的第一金属焊盘或前部金属焊盘224。第一金属焊盘或前部金属焊盘224与密封圈结构210的外部210a连接，而且在一个实施例中，前部金属焊盘224与密封圈结构210的外部210a的顶部金属层连接。在一个实施例中，前部金属焊盘224可以由铝组成，而且密封圈结构的金属层可以由铜组成。可以使用其它金属。
第二前部钝化层222可以位于前部金属焊盘224和第一前部钝化层226上。载具晶圆220可以随后与第二前部钝化层222接合。
在一个实施例中，基板230可以包括下面的第一背部钝化层，其在密封圈区域中作为底层。在一个实施例中，可以通过高纵横比工艺(HARP)和/或高密度等离子体(HDP)CVD工艺沉积氧掺杂或沉积钝化层形成第一背部钝化层。在一个实例中，第一背部钝化层包括电介质(ILD或IMD)而且其为氧化物。另外，在一个实施例中，在形成第一背部钝化层之前可以通过蚀刻减薄基板230。
器件200还包括在基板230中(如第一背部钝化层)的第二金属焊盘或背部金属焊盘232。在这个实施例中，背部金属焊盘232与密封圈结构210的外部210a直接连接，而且在一个实施例中，背部金属焊盘232与密封圈结构210的外部210a的底部金属层直接连接。在一个实施例中，背部金属焊盘232可以由铝组成，而且密封圈结构的金属层可以由铜组成。可以使用其它金属。
第二背部钝化层233、234可以位于第二金属焊盘或背部金属焊盘232和基板230上。在一个实施例中，背部钝化层233可以由氧化硅组成，并且背部钝化层234可以由氮化硅组成。金属焊盘和各种钝化层可以经历图案化和蚀刻步骤从而形成所需的结构外观。
应该可以理解，半导体器件200可以经历电路区域中的进一步加工工艺从而形成各种部件如触点/通孔、互连金属层、层间介质、钝化层等等，形成本领域公知的半导体电路。应该还可以理解，在一些实施例中，半导体器件200可以只包括前部金属焊盘或背部金属焊盘，而不是两个金属焊盘都包括。
现参考图3B，示出了密封圈结构210和器件200的可替换实施例。各个结构与图3A公开的实施例基本相似，并且这里不再重复一般结构的描述，尽管这些结构也完全可以应用到这个实施例中。在这个实施例中，第二金属焊盘或背部金属焊盘232不与密封圈结构210的外部210a的底部金属层直接连接。反而，背部金属焊盘232与触点218连接，触点218与密封圈结构的底部金属层连接。因此，背部金属焊盘232与密封圈结构电连接但是间接地通过触点218。
现参考图4和图5，图4是图3A的密封圈结构的实施例的横截面视图，根据本公开的各个方面，示出了半导体器件200上受阻的管芯切割效应，相反，图5示出了以前的密封圈结构的横截面视图，显示了器件上的管芯切割脱落效应。管芯切割效应，如锯齿线240a到240c所示，被密封圈结构的外部210a中的金属焊盘224和232阻挡，从而使密封圈结构的内部部分210b避免了管芯切割脱落效应和使内部电路器件避免了层脱落。连接和接触密封圈结构的外部并且进一步分别连接前部和背部钝化层的金属焊盘224和232，阻挡管芯切割脱落效应横越到密封圈结构的内部部分和内部电路器件。
相反，图5示出了锯齿线340a到340c表示的管芯切割脱落效应横越到密封圈结构的内部部分210b，因为缺少金属焊盘224和/或232(图4)。特别地，图5示出了沿着钝化层222、230和234的界面所示的管芯切割脱落效应340a-340c，而图4示出了被金属焊盘224和232阻挡的管芯切割脱落效应240a-240c。在一个实施例中，根据本公开的各个方面，可以使用金刚石切割器而不是激光沿着包含密封圈结构的器件的切割槽切割，所述密封圈结构包括金属焊盘，从而降低生产成本。
图6A到图6F根据本公开的各个方面，示出了在制造的各个阶段的器件200的横截面视图。图6A示出了基板230a、密封圈区域上的密封圈结构210、和密封圈结构210上的第一钝化层226的形成。在这个实施例中，触点218被从密封圈结构210的外部210a下移除，尽管在其它实施例中，触点218可以保留在密封圈结构210的外部210a下。
图6B示出了第一钝化层226的蚀刻以形成前部孔252，和随后的沉积，和前部孔252中金属的蚀刻以形成第一金属焊盘或前部金属焊盘224。前部孔252邻近密封圈结构的外部210a的顶部金属层，并且前部金属焊盘224直接与密封圈外部210a的顶部金属层连接。
图6C示出了第二前部钝化层222形成在前部金属焊盘224和第一前部钝化层226上。
图6D示出了背部加工工艺，包括接合载具晶圆220和第二前部钝化层222，和蚀刻基板230a以减薄基板层。
图6E示出了第一背部钝化层230随后形成在密封圈结构下面。在一个实施例中，通过高纵横比工艺(HARP)和/或高密度等离子体(HDP)CVD工艺沉积氧掺杂或沉积钝化层从而形成第一背部钝化层230。在一个实施例中，第一背部钝化层包括电介质(ILD或IMD)并且其为氧化物。
图6F示出了第二钝化层230的蚀刻以形成背部孔250，和随后的沉积，和第二孔250中金属的蚀刻以形成第二金属焊盘或背部金属焊盘232。第二孔250邻近密封圈结构的外部210a的底部金属层，并且背部金属焊盘232直接与外部210a的底部金属层连接。图6F还示出了钝化层233和234形成在背部金属焊盘232和第二钝化层230的下面。
在一个实例中，通过CVD、PVD或其它合适的工艺沉积金属焊盘224和232在各自的孔中，随后图案化，例如使用标准光刻图案化和蚀刻技术。在另一个实例中，金属焊盘224和232由铝组成，尽管也可以使用其它金属，如钛、钨、铜。
本公开提供了许多不同的实施例，并且本公开的方法、技术和结构可以被应用在CMOS图像感应器(CIS)背部照明(BSI)产品中，和应用在需要晶圆接合工艺的产品中，如微机电系统(MEMS)产品。另外，半导体器件可以被形成为具有与密封圈结构连接的前部金属焊盘、与密封圈结构连接的背部金属焊盘、或与密封圈结构连接的这两个金属焊盘。
本公开的其中一个宽泛形式是涉及半导体器件。半导体器件包括基板，其具有密封圈区域和电路区域，位于密封圈区域上的密封圈结构，位于密封圈结构上的第一前部钝化层，和位于第一前部钝化层中的前部金属焊盘，与密封圈结构的外部连接的前部金属焊盘。器件还包括位于前部金属焊盘上的第二前部钝化层，与第二前部钝化层接合的载具晶圆，位于密封圈结构下的第一背部钝化层。
本公开的另一个宽泛形式是涉及半导体器件，半导体器件包括含有密封圈区域和电路区域的基板，在密封圈区域中的密封圈结构，位于密封圈结构上的第一钝化层，和在第一钝化层中的第一金属焊盘，与密封圈结构的外部连接的第一金属焊盘。器件还包括位于密封圈结构下的第二钝化层，和在第二钝化层中的第二金属焊盘，与密封圈结构的外部连接的第二金属焊盘。
本公开的另一个宽泛形式是涉及制造半导体器件的方法。方法包括提供具有密封圈区域和电路区域的基板，在密封圈区域上形成密封圈结构，在密封圈结构上形成第一前部钝化层，在第一前部钝化层中蚀刻邻近密封圈结构的外部的前部孔，和在前部孔中形成前部金属焊盘以连接前部金属焊盘和密封圈结构的外部。方法还包括在密封圈结构下形成第一背部钝化层，在第一背部钝化层中蚀刻邻近密封圈结构的外部的背部孔，和在背部孔中形成背部金属焊盘以连接背部金属焊盘和密封圈结构的外部。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
基板，所述基板具有密封圈区域和电路区域；
密封圈结构，位于所述密封圈区域上；
第一前部钝化层，位于所述密封圈结构上；
前部金属焊盘，在所述第一前部钝化层中，所述前部金属焊盘与所述密封圈结构的外部连接；
第二前部钝化层，位于所述前部金属焊盘上；
载具晶圆，与所述第二前部钝化层接合；和
第一背部钝化层，位于所述密封圈结构下面。
2.根据权利要求1所述的半导体器件，其中所述密封圈结构由围绕所述电路区域布置的金属层堆叠组成。
3.根据权利要求1所述的半导体器件，其中所述前部金属焊盘由铝组成。
4.根据权利要求1所述的半导体器件，其中所述第一前部钝化层和所述第一背部钝化层由氧化硅组成。
5.根据权利要求1所述的半导体器件，其中所述第二前部钝化层由氧化硅和/或氮化硅组成。
6.根据权利要求1所述的半导体器件，其中所述前部金属焊盘直接与所述密封圈结构的顶部金属层连接。
7.根据权利要求1所述的半导体器件，其中所述第一前部钝化层和所述第二前部钝化层由相同的材料或不同的材料组成。
8.根据权利要求1所述的半导体器件，还包括：
背部金属焊盘，位于所述第一背部钝化层中，所述背部金属焊盘与所述密封圈结构的外部连接；和
第二背部钝化层，位于所述背部金属焊盘下。
9.一种半导体器件，包括：
基板，具有密封圈区域和电路区域；
密封圈结构，位于所述密封圈区域中；
第一前部钝化层，位于所述密封圈结构上；
第一背部钝化层，位于所述密封圈结构下；
背部金属焊盘，在所述第一背部钝化层中，所述背部金属焊盘与所述密封圈结构的外部连接；和
第二背部钝化层，位于所述背部金属焊盘下面。
10.一种制造半导体器件的方法，所述方法包括：
提供具有密封圈区域和电路区域的基板；
形成在所述密封圈区域上的密封圈结构；
形成在所述密封圈结构上的第一前部钝化层；
蚀刻邻近所述密封圈结构的外部的所述第一前部钝化层中的前部孔；
形成在所述前部孔中的前部金属焊盘以连接所述前部金属焊盘和所述密封圈结构的外部；
形成在所述密封圈结构下的第一背部钝化层；
蚀刻邻近所述密封圈结构的外部的所述第一背部钝化层中的背部孔；和
形成在所述背部孔中的背部金属焊盘以连接所述背部金属焊盘和所述密封圈结构的外部。
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