CN102376594B - Electronic package structure and package method thereof - Google Patents
Electronic package structure and package method thereof Download PDFInfo
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- CN102376594B CN102376594B CN201010265449.2A CN201010265449A CN102376594B CN 102376594 B CN102376594 B CN 102376594B CN 201010265449 A CN201010265449 A CN 201010265449A CN 102376594 B CN102376594 B CN 102376594B
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- circuit substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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Abstract
The invention discloses a package method of an electronic package structure. The package method comprises the following steps of: providing a substrate; providing an inductance module; joining the inductance module to the substrate so as to define a space between the inductance module and the substrate; and filling a plastic material in the space defined by the inductance module and the substrate so as to form a package layer.
Description
Technical field
The present invention relates to a kind of electron package structure and method for packing thereof, especially about a kind of electron package structure and the method for packing thereof that can reduce its volume.
Background technology
Fig. 1 shows the DC to DC converter encapsulating structure of a prior art.As shown in Figure 1, this structure is United States Patent (USP) 6, the DC to DC converter encapsulating structure (DC-to-DC converter package) disclosed by 212, No. 086.DC to DC converter encapsulating structure 100 comprises the electronic component of system circuit board 120, copper base material 110 and majority.System circuit board 120 is placed in above copper base material 110, and therefore copper base material 110 can provide uniform heat sinking function in the bottom of this device.Those electronic components include main transformer 130, outputting inductance 140, synchronous rectifier 150, output capacitor 160 and input capacitor 170, these electronic components placement on system circuit board 120, and are coupled mutually by the circuit layout of system circuit board 120 inside.One independently out connector be located on the right of system circuit board 120, be couple to system circuit board 120 via flexible circuit board.
Summary of the invention
The object of one embodiment of the invention is to provide a kind of electron package structure and the method for packing thereof that can reduce its volume.The object of another embodiment is to provide a kind of electron package structure and the method for packing thereof that do not need to use mould.
According to one embodiment of the invention, provide a kind of method for packing of electron package structure its comprise following steps.One substrate is provided.One inductor module is provided.Inductor module is engaged in substrate, uses and make between inductor module and substrate, to define a space.One glue material is filled in space that inductor module and substrate define, to form an encapsulated layer.In one embodiment, aforementioned encapsulation method more comprises following steps.A chip module in order to be electrically connected with a circuit of substrate is engaged on the body of substrate.And the step of aforementioned formation one encapsulated layer comprises and makes glue material coating chip module.
In one embodiment, the aforementioned step of a substrate that provides comprises: the body forming substrate; And at least side of body, form at least one first connecting portion of substrate.The aforementioned step of an inductor module that provides comprises: the inductance element forming inductor module; In at least side of inductance element, form at least side alar part, and make at least one flank section protrude from inductance element one surface.Aforementioned step inductor module being engaged in substrate comprises: make this at least one first connecting portion be engaged in this at least one flank section, so that inductor module is located on substrate, uses and make to define this space between the body of the inductance element of inductor module and this at least one flank section and substrate.
In one embodiment, the aforementioned step of a substrate that provides comprises: the body forming substrate; And at least side of body, form at least one flank section of substrate, and this at least one flank section is made to protrude from body one surface.The aforementioned step of an inductor module that provides comprises: the inductance element forming inductor module; In at least side of inductance element, form at least one first connecting portion.Aforementioned step inductor module being engaged in substrate comprises: make this at least one first connecting portion be engaged in this at least one flank section, so that inductor module is located on substrate, uses and make to define this space between the inductance element of inductor module and the body of substrate and this at least one flank section.
According to one embodiment of the invention, an electron package structure is provided to comprise substrate one inductor module and an encapsulated layer.Substrate comprises the circuit that electron package structure is operated.Inductor module makes electron package structure operate in order to coordinate with substrate to use, and and defines a space between substrate.Encapsulated layer is positioned at this space.Encapsulated layer formed by being filled in by a glue material in this space that inductor module and substrate define.In one embodiment, electron package structure more comprises a chip module, to be located on substrate and in order to be electrically connected with the circuit of substrate.Encapsulated layer coating chip module.In one embodiment, contact with encapsulated layer respectively in substrate and inductor module, and in the contact area of substrate and inductor module, encapsulated layer fills up in fact the coarse structure in this contact area of substrate and inductor module.
In one embodiment, substrate comprises a body and at least one first connecting portion.Chip module is located on body.At least one first connecting portion is located at least side of body.Inductor module comprises an inductance element and at least one flank section.Outstanding inductance element one surface is opened at least side that at least one flank section is located at inductance element.At least one flank section self-inductance element extends towards the direction of substrate, engages the first connecting portion to make at least one flank section.
In one embodiment, substrate comprises a body and at least one flank section.Chip module is located on body.At least one flank section is located at least side of body, and outstanding inductance element one surface.Inductor module comprises inductance element and at least one first connecting portion.At least one first connecting portion is located at least side of inductance element.This at least one flank section extends towards the direction of inductor module from body, engages the first connecting portion to make flank section.
In one embodiment, electron package structure is suitable for being arranged on a circuit board, and chip module or inductor module system are electrically connected with substrate through circuit board.
According to one embodiment of the invention, provide a kind of electron package structure its comprise an inductor module and an encapsulated layer.Inductor module comprises an inductance element, one first flank section, the second flank section and an encapsulated layer.First flank section is located at the side of inductance element and outstanding inductance element one is surperficial.Second flank section is located at the opposite side of inductance element and outstanding inductance element surface, use make this table and, the first flank section and the second flank section form a space.Encapsulated layer is positioned at this space.The width of encapsulated layer can equal in fact the distance between the first flank section and the second flank section.
In one embodiment, electron package structure more comprises a substrate.Substrate comprises the circuit that electron package structure is operated.Inductor module coordinates with substrate to use makes electron package structure operate, and the surface of inductor module, the first flank section and the second flank section; And define this space between substrate.In one embodiment, encapsulated layer formed by being filled in this space by a glue material.
In one embodiment, isolate inductor module through encapsulated layer and be provided with chip and wire, and making substrate be electrically connected inductor module, forming stacked arrangement.Compared to the mode that the general element of prior art is directly connected with base plan, the present embodiment more effectively can utilize space, can reduce the volume of electron package structure.In one embodiment, utilize between inductor module and substrate and define a space as die cavity, to form encapsulated layer, can not additional mold be needed, reduce the cost manufactured, and easily carry out design for change.In addition in one embodiment, inductor module can cover chip, therefore has electromagnetic interference (EMI) inhibit feature.
Accompanying drawing explanation
Fig. 1 shows the DC to DC converter encapsulating structure of a prior art;
Fig. 2 A ~ 2F shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention;
Fig. 3 A ~ 3E shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention;
Fig. 3 F shows the schematic perspective view according to one embodiment of the invention electron package structure;
Fig. 4 A is the vertical view of the substrate of one embodiment of the invention;
Fig. 4 B is the end view of the inductor module of one embodiment of the invention;
Fig. 5 A shows the generalized section according to one embodiment of the invention electron package structure;
Fig. 5 B is the enlarged diagram of the region S of Fig. 5 A;
Fig. 5 C is in embodiment substrate and inductor module engaged again after forming encapsulated layer with a mould, the enlarged diagram of a contact area of inductor module and encapsulated layer;
Fig. 6 shows cuing open and schematic diagram according to one embodiment of the invention electron package structure;
Fig. 7 shows the schematic diagram of an electronic combination device.
Drawing reference numeral:
100 DC to DC converter encapsulating structures
110 copper base materials
120 system circuit boards
130 heat sinking functions
140 outputting inductances
150 synchronous rectifiers
160 output capacitors
170 input capacitors
300 electron package structures
310 substrates
311 first flank section
312 second flank section
313 bodies
321 chips
322 wires
323 knitting layers
330 encapsulated layers
340 inductor modules
341 first pins
342 second pins
343 choke coils
400 electron package structures
410 substrates
411 first connecting portions
412 second connecting portions
413 bodies
440 inductor modules
441 first flank section
442 second flank section
443 choke coils
44a the 3rd connecting portion
44b the 4th connecting portion
Embodiment
Other objects of the present invention and advantage can be further understood from the technical characteristic disclosed by the present invention.For above and other object of the present invention, feature and advantage can be become apparent, special embodiment below also coordinates accompanying drawing, is described in detail below.
Fig. 2 A ~ 2F shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention.As shown in Fig. 2 A ~ 2D, according to the method for packing of one embodiment of the invention electron package structure, comprise following steps.
As shown in Figure 2 A, step S02 a: substrate 310 is provided.In one embodiment, step S02 comprises: the body 313 forming substrate 310; And at least side of body 313, form at least one flank section of substrate 310, and this at least one flank section is made to protrude from body 313 1 surface.More specifically, substrate 310 comprises a body 313 and is located at one first flank section 311 and one second flank section 312 of body 313 both sides.In this manual, substrate refers to the support plate that electron package structure can be made to operate in a system, a circuit that electron package structure can be made to operate can be included in a substrate, and the term of " an element electrical connection substrate " refers to that this element is electrically connected the circuit of substrate directly or indirectly, operate in a system to enable this electron package structure.The manufacture of substrate and the design of base on-board circuitry, be have in this area usually to know that the knowledgeable can be completed, therefore no longer describe in detail at this specification.The present invention is not particularly limited the material of substrate, the substrate of unlike material can be used according to different products, the material of substrate can be lead frame (lead-frame), printed circuit board (PCB) (PCB) or pottery (ceramic), or the combination etc. of said elements.When substrate is lead frame, be that this forms a circuit as a conductor, and when substrate be a printed circuit board (PCB) or ceramic time, in this substrate, be more provided with a circuit layout.In Fig. 2 A embodiment, substrate 310 is a lead frame.
As shown in Figure 2 B, step S04 a: chip module 321 is engaged in (die bond) on the body 313 of substrate 310, chip module 321 is in order to be electrically connected with substrate 310.A knitting layer 314 is utilized to be engaged on the body 313 of substrate 310 by chip module 321 in one embodiment.In one embodiment, step S04 more can also comprise and makes at least one wire 322 be electrically connected (wire bond) between chip module 321 and substrate 310.
As shown in Figure 2 C, step S06: bend the first flank section 311 and the second flank section 312, first flank section 311 and the second flank section 312 are extended toward the direction away from a surface of body 313 respectively, uses and make chip module 321 between the first flank section 311 and the second flank section 312.
As shown in Figure 2 D, step S08 a: inductor module 340 is provided.Inductor module 340 can be primary antibodie stream circle (choke) module, and it defines one first groove 351 and one second groove 352 and the first pin 341 and the second pin 342 comprising a choke coil (choke) 343 and be located at choke coil 343 both sides.Preferably, the position of the first groove 351 and the second groove 352, the respectively position of corresponding first flank section 311 and the second flank section 312.In addition inductor module 340 can also include other in order to coordinate the electronic component making electron package structure 300 operate with substrate 310, and inductor module 340 is electrically connected with the first pin 341 and the second pin 342 through those electronic components.Being designed to have in this area of inductor module 340 knows that the knowledgeable can complete usually, therefore no longer describes in detail at this specification.
As shown in Figure 2 E, step S10: inductor module 340 is engaged in substrate 310, uses and makes inductor module 340 and substrate 310 define a space (or being called die cavity).In the present embodiment, the first flank section 311 and the second flank section 312 is made to be engaged in the first groove 351 and one second groove 352 respectively.In one embodiment, shape and the size of the shape of the first flank section 311 and size and the first groove 351 are worked in coordination, and use and are positioned on substrate 310 by inductor module 340.In one embodiment, the shape of the second flank section 312 and size can also be worked in coordination with the shape of the second groove 352 and size.Will be appreciated that inductor module 340 is not limited to above-described embodiment with the juncture of substrate 310, in one embodiment, first flank section 311 and the second flank section 312 can also be respectively a syndeton, and the first groove 351 and one second groove 352 can also be respectively another syndeton, this syndeton and this another syndeton can be worked in coordination, and use and inductor module 340 is engaged in substrate 310.Those syndetons are that this area has and usually knows that the knowledgeable can complete, and therefore no longer describe in detail at this specification.
As shown in Figure 2 F, step S12: plastic rubber material is filled in die cavity that inductor module 340 and substrate 310 define, and is toasted, form an encapsulated layer 330, chip module 321 and wire 322 to be encapsulated.The last cutting supervisor that carries out more again forms single electron package structure 300.
As shown in Figure 2 F, according to one embodiment of the invention, electron package structure 300 comprises substrate 310, chip module 321, at least one wire 322, encapsulated layer 330 and an inductor module 340.Substrate 310 comprises a body 313 and is located at one first flank section 311 and one second flank section 312 of body 313 both sides.Chip module 321 is located on the body 313 of substrate 310, and those wires 322 are electrically connected between chip module 321 and substrate 310.The body 313 that encapsulated layer 330 is located at substrate 310 covers chip module 321 and wire 322.Encapsulated layer 330 is positioned at the space that inductor module 340 and substrate 310 define.And encapsulated layer 330 to be filled in space that inductor module 340 and substrate 310 define by the plastic rubber material be thermally melted one and to be cooled formed.Inductor module 340 defines one first groove 351 and one second groove 352 and comprises a choke coil 343 and be located at the first pin 341 and the second pin 342 of choke coil 343 both sides.First flank section 311 and the second flank section 312 of substrate 310, extends to the first pin 341 and the second pin 342 of inductor module 340, and is electrically connected the first pin 341 and the second pin 342 respectively towards inductor module 340 direction.
In one embodiment, the body 313 of substrate 310 can be printed circuit board (PCB) or pottery, and the first flank section 311 and the second flank section 312 can for being located at the lead frame of body 313 both sides.According to this design, even if overcome using printed circuit board (PCB) or pottery as the problem that cannot bend during substrate.In an embodiment of the present invention, electron package structure 300 can be a DC to DC converter encapsulating structure.
According to the present embodiment, at least have the following advantages compared to prior art.
In the present embodiment, be electrically connected the first pin 341 and the second pin 342 of inductor module 340 through the first flank section 311 of substrate 310 and the second flank section 312, form stacked arrangement.The mode that the general element of prior art compared to Fig. 1 is directly connected with base plan, the present embodiment more effectively can utilize space, can reduce the volume of electron package structure 300.
Fig. 3 A ~ 3D shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention.As shown in Fig. 3 A ~ 3D, according to the method for packing of one embodiment of the invention electron package structure, comprise following steps.
As shown in Figure 3A, step S22 a: substrate 410 is provided.In one embodiment, step S22 comprises: the body 413 forming substrate 410; And at least side of body 413, form at least one connecting portion of substrate 410.Therefore, substrate 410 comprises a body 413 and is located at one first connecting portion 411 and one second connecting portion 412 of body 413 both sides.In one embodiment, a circuit that electron package structure can be made to operate is included in substrate 410.The present invention is not particularly limited the material of substrate, and the material of substrate can be lead frame (lead-frame), printed circuit board (PCB) (PCB) or pottery (ceramic) etc.Fig. 4 A is the vertical view of the substrate of one embodiment of the invention.As shown in Figure 4 A, in one embodiment, the opening that the first connecting portion 411 and the second connecting portion 412 can go out for substrate 410 boundaries or a breach, and its shape is not limited, and can also be a projection (not shown) in addition in one embodiment.More specifically, in one embodiment, substrate 410 is a lead frame, and step S22 comprises following steps.Step S202: to lead frame (lead-frame) half-etching.Step S204: silver-plated to lead frame one side.
As shown in Figure 3 B, step S24 a: chip module 321 is engaged in (die bond) on the body 413 of substrate 410, chip module 321 is in order to be electrically connected with substrate 410.In one embodiment, step S24 more comprises at least one wire 322 is electrically connected between chip module 321 and substrate 410 (wirebond).More specifically, in one embodiment, step S24 comprises following steps.Step S402: some glue, be also applied on substrate 410 by knitting layer 414, knitting layer 414 can be conducting resinl or non-conductive adhesive.Step S404: upper slice (Die Bond), is also located on knitting layer 414 by chip module 321.Step S406: routing, even if also wire 322 chip module connection 321 and lead frame (Au WireBond).
As shown in Figure 3 C, step S26 a: inductor module 440 is provided.In one embodiment, step S26 comprises: the inductance element forming inductor module 400; And at least side of inductance element, form at least side alar part, and this at least one flank section is made to protrude from this inductance element one surface.More specifically, inductor module 440 can be primary antibodie stream circle (choke) module, and it comprises choke coil (choke) 443 and one first flank section 441 and one second flank section 442 that one is inductance element.First flank section 441 and the second flank section 442 are located at the both sides of choke coil 443 respectively, protrude from choke coil 443 lower surface and extend towards away from choke coil 443 bottom direction, and its free end forms one the 3rd connecting portion 44a and the 4th connecting portion 44b.The shape of the 3rd connecting portion 44a and the shape of the first connecting portion 411 are worked in coordination, the shape of the 4th connecting portion 44b and the shape of the second connecting portion 412 are worked in coordination, use and make the 3rd connecting portion 44a possess the function engaged with the first connecting portion 411, the 4th connecting portion 44b possesses the function engaged with the second connecting portion 412.Fig. 4 B is the end view of the inductor module 440 of one embodiment of the invention.As shown in Figure 4 B, in the present embodiment, the 3rd connecting portion 44a (and the 4th connecting portion 44b) can be a projection, and it can also be an opening or a breach in one embodiment.In addition inductor module 440 can also include other in order to coordinate the electronic component making electron package structure 400 operate with substrate 410, and inductor module 440 is electrically connected with substrate 410 through those electronic components, uses and electron package structure 400 can be operated.Being designed to have in this area of inductor module 440 knows that the knowledgeable can complete usually, therefore no longer describes in detail at this specification.
As shown in Figure 3 D, step S28: make the 3rd connecting portion 44a be engaged in the first connecting portion 411 and engage, 4th connecting portion 44b is engaged in the second connecting portion 412, so that inductor module 440 is located on substrate 410, define a space between inductor module 440 and substrate 410, more specifically choke coil (choke) 443, first flank section 441, second flank section 442 and body 413 define this space (or being called die cavity).In addition, can more additional melted material, utilize metal welding mode, by the joint welding in addition of the 3rd connecting portion 44a and the first connecting portion 411, by the joint welding in addition of the 4th connecting portion 44b and the second connecting portion 412, further to strengthen the bond strength between the 3rd and four connecting portion 44a and 44b and first and two connecting portions 411 and 412, inductor module 440 is made can be firmly electrically connected on substrate 410.Melted material can be added with auxiliary material again, and auxiliary dead-wood material can be conductor or non-conductor.
As shown in FIGURE 3 E, step S30: a glue material is filled in space that inductor module 440 and substrate 410 define, to form an encapsulated layer 330.In one embodiment, the plastic rubber material be thermally melted is filled in the die cavity that inductor module 440 and substrate 410 define, and is toasted and cool, and forms an encapsulated layer 330, chip module 321 and wire 322 to be encapsulated.The last cutting supervisor that carries out more again forms single electron package structure 300.In the present embodiment, (will be described later) as illustrated in Figure 3 F, the first flank section 441 and the second flank section 442 form a plane respectively, or form a face wall.After inductor module 440 is positioned substrate 410, a space can be defined by choke coil (choke) 443, first flank section 441 of inductor module 440 and the second flank section 442 with substrate 410, be formed with opening at these two ends, space.Plastic rubber material can inject in this space from opening by point glue equipment.Because the first flank section 441 and the second flank section 442 can block the flowing of plastic rubber material, after plastic rubber material cure package layer 330 is formed, the width of encapsulated layer 330 can equal in fact the distance between the first flank section 441 and the second flank section 442.
Fig. 3 F shows the schematic perspective view according to one embodiment of the invention electron package structure.For knowing the internal structure of electron package structure and not shown encapsulated layer in Fig. 3 F.As shown in Fig. 3 E and 3F, according to one embodiment of the invention, electron package structure 400 comprises substrate 410, chip module 321, at least one wire 322, encapsulated layer 330 and an inductor module 440.Substrate 410 comprises a body 413 and is located at one first connecting portion 411 and one second connecting portion 412 of body 413 both sides.In the present embodiment, the first connecting portion 411 and the second connecting portion 412 opening that can go out for substrate 410 boundaries or a breach.Chip module 321 is located on the body 413 of substrate 410, and those wires 322 are electrically connected between chip module 321 and substrate 410.Inductor module 440 can be primary antibodie stream circle (choke) module, and it comprises a choke coil (choke) 443 and one first flank section 441 and one second flank section 442.First flank section 441 and the second flank section 442 are located at the both sides of choke coil 443 respectively, to protrude from bottom choke coil 443 and to extend towards substrate 410 direction, and its free end forms one the 3rd connecting portion 44a and the 4th connecting portion 44b.Utilize metal welding mode, make the 3rd connecting portion 44a be fused to the first connecting portion the 411, four connecting portion 44b and be fused to the second connecting portion 412, to be located on substrate 410 by inductor module 440, between inductor module 440 and substrate 410, define a space.Encapsulated layer 330 is located at the space that defines between inductor module 440 and substrate 410 and is covered chip module 321 and wire 322.And encapsulated layer 330 to be filled in the space that inductor module 440 and substrate 410 define by the plastic rubber material be thermally melted one and to be cooled and formed.
According to the present embodiment, at least to have the following advantages one compared to above-described embodiment:
1, as shown in FIGURE 3 E, because the first flank section 441 and the second flank section 442 extend to the body 413 of substrate 410 from choke coil 443, inductor module 440 can cover chip module 321, therefore, it is possible to have electromagnetic interference (EMI) inhibit feature.
2, the heat that produces of chip module 321, except from substrate 410 backside heat, can conducting to choke coil 443 from substrate 410 through the first flank section 441 and the second flank section 442, and dispel the heat from inductor module 440, have preferably radiating effect.
3, utilize between inductor module 440 and substrate 410 and define a die cavity, therefore do not need additional mold, reduce the cost manufactured, and easily carry out design for change.
In addition, in one embodiment, the electron package structure 300 of Fig. 2 F and Fig. 3 E can also have following advantage.In the embodiment again substrate and inductor module engaged after forming encapsulated layer with a mould, because of the manufacturing process distance H be limited between wire to encapsulated layer need reserve one enough place the distance of mould and place mould time required error distance, and need to carry out accurate contraposition to mould.But according to the embodiment of Fig. 2 F, the shape of the shape of the first flank section 311 and size and the first groove 351 and size is worked in coordination and/or the shape of the second flank section 312 and size can also be worked in coordination with the shape of the second groove 352 and size; According to the embodiment of Fig. 3 E, because the shape of the 3rd connecting portion 44a and the shape of the first connecting portion 411 are worked in coordination, the shape of the 4th connecting portion 44b and the shape of the second connecting portion 412 are worked in coordination, after the 3rd and four connecting portion 44a and 44b engage each other between connecting portion 411 and 412 with first and two, can positioning function be reached, therefore simplify the program needing precise positioning when using mould.The distance H between wire to encapsulated layer can also be reduced, therefore, it is possible to further reduce the volume of electron package structure.
Fig. 5 A shows the generalized section according to one embodiment of the invention electron package structure.Fig. 5 A embodiment electron package structure 400a is similar in appearance to Fig. 3 E embodiment electron package structure 400, and therefore identical element uses identical symbol, and description is omitted.In one embodiment, body 413, except being provided with a chip module 321, can also arrange other electronic component, has various different function in order to make electron package structure 400a.As shown in Figure 5A, body 413 is also provided with resistance 325, one electric capacity 326 and a MOS transistor 327.
, in the present embodiment, and encapsulated layer 330 to be filled in space that inductor module 440 and substrate 410 define by the plastic rubber material be thermally melted one and to be cooled formed in addition.And to contact with encapsulated layer 330 respectively and in contact area at substrate 410 and inductor module 440, encapsulated layer 330 fills up in fact the coarse structure in this contact area of substrate 410 and inductor module 440 in substrate 410 and inductor module 440.Region S as shown in Figure 5A, region S are the contact area between the side wing 442 of inductor module 440 and encapsulated layer 330.Fig. 5 B is the enlarged diagram of the region S of Fig. 5 A.Under microcosmic, in the contact area S between the side wing 442 of inductor module 440 and encapsulated layer 330, the surface of side wing 442 can be formed with a coarse structure.When encapsulated layer 330 be filled in by the plastic rubber material be thermally melted in space that inductor module 440 and substrate 410 define and cooled formed time, encapsulated layer 330 can fill up in fact the coarse structure in contact area S.Fig. 5 C is in embodiment substrate and inductor module engaged again after forming encapsulated layer with a mould, the enlarged diagram of a contact area of inductor module and encapsulated layer.As shown in Figure 5 C, according to be formed after encapsulated layer again by embodiment that substrate and inductor module are engaged with a mould, under microcosmic, in contact area A between inductor module 440 and encapsulated layer 330, the border L of encapsulated layer 330, only can contact the coarse structure in the contact area A of meeting inductor module, and the coarse structure in contact area A can not be filled up.
Fig. 6 display is according to the generalized section of one embodiment of the invention electron package structure.Fig. 6 embodiment electron package structure 400b is similar in appearance to Fig. 5 embodiment electron package structure 400a, and therefore identical element uses identical symbol, and description is omitted.As discussed previously, the present invention does not limit the material of substrate 410, and the material of substrate 410 can be lead frame (1ead-frame), printed circuit board (PCB) (PCB) or pottery (ceramic) etc.In the present embodiment, substrate 410 adopts the material of compound, and its body 413 includes printed circuit board (PCB) 31,1 first lead frame 32,1 second lead frame 33, privates frame 34.More complicated circuit can be arranged at printed circuit board (PCB) 31, and make printed circuit board (PCB) 31 produce more pin in order to be electrically connected with chip module 321, finally printed circuit board (PCB) 31 is arranged on the first lead frame 32.The heat sinking function of the first lead frame 32 is better than printed circuit board (PCB) 31, therefore according to the design of electron package structure 400b, can comprise more complicated circuit, can also have preferably radiating effect simultaneously.
Fig. 7 shows the schematic diagram of an electronic combination device (electrical assembly), this electronic combination device include be installed on a circuit board according to one embodiment of the invention electron package structure.As shown in Figure 7, electronic combination device 500 comprises the electron package structure 400 of a circuit board 510 and Fig. 3 E embodiment.Circuit board 510 includes a circuit.Electron package structure 400 is located on circuit board 510, to form the electronic combination device of another form.In the present embodiment, chip module 321 or inductor module 440 can not directly be electrically connected to substrate 410, and the circuit being through circuit board 510 is electrically connected substrate 410 more indirectly.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the right person of defining.In addition, any embodiment of the present invention or claim must not reach whole object disclosed by the present invention or advantage or feature.In addition, summary part and title are only used to the use of auxiliary patent document search, are not used for limiting interest field of the present invention.
Claims (23)
1. a method for packing for electron package structure, is characterized in that, described method for packing comprises:
One circuit substrate is provided;
One chip module is engaged on described circuit substrate, and described chip module is electrically connected with described circuit substrate one circuit;
One inductor module is provided;
Described inductor module is engaged in described circuit substrate, use and make to define a space between the flank section of the both sides of described inductor module, described circuit substrate and described inductor module and described circuit substrate one, and be formed with an opening at least one end in described space, wherein said chip module is positioned at described space, and described flank section has thermal conducting function;
When not using mould, from described opening, one glue material is filled in described space, make the coated described chip module of described glue material, described glue material is made to contact described inductor module, described circuit substrate and described flank section, to form an encapsulated layer, and in the contact area of described circuit substrate and described inductor module, described encapsulated layer fills up in fact the coarse structure in the described contact area of described circuit substrate and described inductor module.
2. method for packing as claimed in claim 1, it is characterized in that, described inductor module has suppression electromagnetic interference function.
3. method for packing as claimed in claim 1, is characterized in that,
The described step of a circuit substrate that provides comprises:
Form a body of described circuit substrate; And
In the both sides of described body, form two the first connecting portions of described circuit substrate respectively,
The described step of an inductor module that provides comprises:
Form an inductance element of described inductor module;
In the both sides of described inductance element, form described flank section, and make described flank section protrude from described inductance element one surface,
The described step described inductor module being engaged in described circuit substrate comprises:
Make described first connecting portion be engaged in described flank section, so that described inductor module is located on described circuit substrate, uses and make to define described space between the described body of the described inductance element of described inductor module and described flank section and described circuit substrate.
4. method for packing as claimed in claim 3, is characterized in that,
The free end that the step of described formation flank section is included in described flank section forms two the second connecting portions respectively, and
The described step making described first connecting portion be engaged in described flank section comprises makes described first connecting portion be engaged in described second connecting portion,
The heat of wherein said flank section in order to be produced by described chip module, conducts to described inductor module from described circuit substrate by described flank section, and dispels the heat from described inductor module.
5. method for packing as claimed in claim 4, it is characterized in that, the shape of described first connecting portion and the shape of described second connecting portion are worked in coordination, and use and make described inductance element be located in described circuit substrate.
6. method for packing as claimed in claim 5, is characterized in that, described in make described first connecting portion be engaged in the step of described second connecting portion, more comprise and utilize the second connecting portion and described first connecting portion described in the further welding of metal welding mode.
7. method for packing as claimed in claim 1, is characterized in that,
The described step of a circuit substrate that provides comprises:
Form a body of described circuit substrate; And
In the both sides of described body, form the described flank section of described circuit substrate, and make described flank section protrude from described body one surface,
The described step of an inductor module that provides comprises:
Form an inductance element of described inductor module;
In the both sides of described inductance element, form two the first connecting portions,
The described step described inductor module being engaged in described circuit substrate comprises:
Make described first connecting portion be engaged in described flank section, so that described inductor module is located on described circuit substrate, uses and make to define described space between the described inductance element of described inductor module and the described body of described circuit substrate and described flank section.
8. method for packing as claimed in claim 7, is characterized in that, the free end that the step of described formation flank section is included in described flank section forms two the second connecting portions, and
The described step making described first connecting portion be engaged in described flank section comprises makes described first connecting portion be engaged in described second connecting portion,
Wherein, the heat of described flank section in order to be produced by described chip module, conducts to described inductor module from described circuit substrate by described flank section, and dispels the heat from described inductor module.
9. the method for packing as described in any one of claim 1 to 8, is characterized in that, described inductor module is a choke coil module, and described inductance element is a choke coil.
10. an electron package structure, is characterized in that, described electron package structure comprises:
One circuit substrate, comprises the circuit that described electron package structure is operated;
One chip module, is located on described circuit substrate and with the described circuit of described circuit substrate and is electrically connected;
One inductor module, in order to coordinate with described circuit substrate to use, described electron package structure is operated, and and define a space between the flank section of the both sides of described circuit substrate and described inductor module and described circuit substrate one, and be formed with an opening at least one end in described space, wherein said chip module is positioned at described space, and described flank section has thermal conducting function;
One encapsulated layer, is positioned at described space and coated described chip module,
Wherein said encapsulated layer is by when not using mould, to be filled in described space by one glue material to be formed from described opening, and,
Described circuit substrate and described inductor module contact with described encapsulated layer respectively, and in the contact area of described circuit substrate and described inductor module, described encapsulated layer fills up in fact the coarse structure in the described contact area of described circuit substrate and described inductor module.
11. electron package structures as claimed in claim 10, it is characterized in that, described inductor module has suppression electromagnetic interference function.
12. electron package structures as claimed in claim 10, it is characterized in that, the back side of described circuit substrate has heat sinking function.
13. electron package structures as claimed in claim 11, is characterized in that,
Described circuit substrate comprises:
One body, described chip module is located on described body; And
Two the first connecting portions, are located at the both sides of described body respectively,
Described inductor module comprises:
One inductance element; And
Described flank section, is located at the both sides of described inductance element and outstanding described inductance element one is surperficial,
Wherein said flank section extends towards the direction of described circuit substrate from described inductance element, engages described first connecting portion to make described flank section.
14. electron package structures as claimed in claim 13, is characterized in that,
The free end of described flank section forms two the second connecting portions, and described second connecting portion engages described first connecting portion,
And the heat of described flank section in order to described chip module is produced, conduct to described inductor module from described circuit substrate by described flank section, and dispel the heat from described inductor module.
15. electron package structures as claimed in claim 14, is characterized in that,
Described second connecting portion has conductivity,
Described first connecting portion is electrically connected to the described circuit of described circuit substrate, and
Described second connecting portion and described first connecting portion utilize metal welding mode to be engaged, and use and make described inductor module be electrically connected described circuit substrate.
16. electron package structures as claimed in claim 14, is characterized in that, the shape of described first connecting portion and the shape of described second connecting portion are worked in coordination, and use and make described inductance element be located in described circuit substrate.
17. electron package structures as claimed in claim 16, is characterized in that, described first connecting portion is the opening that defined by this circuit substrate or a breach, and described second connecting portion is a projection.
18. electron package structures as claimed in claim 17, is characterized in that, described second connecting portion and described first connecting portion utilize metal welding mode to be engaged.
19. electron package structures as claimed in claim 10, is characterized in that, described circuit substrate is a lead frame, a printed circuit board (PCB) or a pottery; Or be the combination of in described lead frame, described printed circuit board (PCB) or described pottery wantonly more than two.
20. electron package structures as claimed in claim 10, is characterized in that, described inductor module is a choke coil module.
21. electron package structures as claimed in claim 10, it is characterized in that, described electron package structure more comprises at least one electronic component, and wherein said electronic component is arranged on described circuit substrate.
22. electron package structures as claimed in claim 10, is characterized in that,
Described circuit substrate comprises:
One body, described chip module is located on described body; And
Two flank section, are located at the both sides of described body,
Described inductor module comprises:
One inductance element, wherein said two flank section give prominence to a surface of described inductance element; And
Two the first connecting portions, are located at the both sides of described inductance element,
Wherein said flank section extends towards the direction of described inductor module from described body, engages described first connecting portion to make described flank section.
23. electron package structures as described in any one of claim 10 to 22, it is characterized in that, described electron package structure is suitable for being arranged on a circuit board, and described chip module or described inductor module are electrically connected with described circuit board through described circuit substrate.
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| CN201510168652.0A CN104934188B (en) | 2010-08-26 | 2010-08-26 | Electron package structure and its method for packing |
| CN201510168662.4A CN104952854B (en) | 2010-08-26 | 2010-08-26 | Electron package structure and its packaging method |
| CN201010265449.2A CN102376594B (en) | 2010-08-26 | 2010-08-26 | Electronic package structure and package method thereof |
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| EP3364429B1 (en) * | 2017-02-16 | 2019-08-14 | Mitsubishi Electric R&D Centre Europe B.V. | Inductive assembly |
| CN107808879A (en) | 2017-11-20 | 2018-03-16 | 深圳顺络电子股份有限公司 | A kind of Switching Power Supply module and its method for packing |
| CN112990413B (en) * | 2021-03-09 | 2023-07-25 | 深圳源明杰科技股份有限公司 | Coil dispensing method, device, equipment and computer readable storage medium |
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| US6048755A (en) * | 1998-11-12 | 2000-04-11 | Micron Technology, Inc. | Method for fabricating BGA package using substrate with patterned solder mask open in die attach area |
| JP3873145B2 (en) * | 1999-05-27 | 2007-01-24 | 京セラ株式会社 | Package for storing semiconductor elements |
| CN2459755Y (en) * | 2001-01-17 | 2001-11-14 | 邱雯雯 | Structure of IC chip |
| US6509530B2 (en) * | 2001-06-22 | 2003-01-21 | Intel Corporation | Via intersect pad for electronic components and methods of manufacture |
| TW567601B (en) * | 2002-10-18 | 2003-12-21 | Siliconware Precision Industries Co Ltd | Module device of stacked semiconductor package and method for fabricating the same |
| US6861288B2 (en) * | 2003-01-23 | 2005-03-01 | St Assembly Test Services, Ltd. | Stacked semiconductor packages and method for the fabrication thereof |
| JP4134893B2 (en) * | 2003-12-05 | 2008-08-20 | 松下電器産業株式会社 | Electronic device package |
| JP4186972B2 (en) * | 2005-09-28 | 2008-11-26 | 松下電器産業株式会社 | Sheet-like device for connection between substrates and connection structure |
| JP4354472B2 (en) * | 2006-08-31 | 2009-10-28 | Ｔｄｋ株式会社 | Electronic component module |
| CN101330075B (en) * | 2007-06-20 | 2010-06-02 | 乾坤科技股份有限公司 | Stereo encapsulation structure |
| CN101483381B (en) * | 2008-01-07 | 2012-11-07 | 台达电子工业股份有限公司 | Combined structure |
| CN101527292B (en) * | 2008-03-04 | 2012-09-26 | 南茂科技股份有限公司 | Chip packaging structure |
| US20100110656A1 (en) * | 2008-10-31 | 2010-05-06 | Advanced Semiconductor Engineering, Inc. | Chip package and manufacturing method thereof |
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| CN104934188B (en) | 2018-04-10 |
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| CN104934188A (en) | 2015-09-23 |
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