CN102376594A - Electronic package structure and package method thereof - Google Patents
Electronic package structure and package method thereof Download PDFInfo
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- CN102376594A CN102376594A CN2010102654492A CN201010265449A CN102376594A CN 102376594 A CN102376594 A CN 102376594A CN 2010102654492 A CN2010102654492 A CN 2010102654492A CN 201010265449 A CN201010265449 A CN 201010265449A CN 102376594 A CN102376594 A CN 102376594A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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Abstract
The invention discloses a package method of an electronic package structure. The package method comprises the following steps of: providing a substrate; providing an inductance module; joining the inductance module to the substrate so as to define a space between the inductance module and the substrate; and filling a plastic material in the space defined by the inductance module and the substrate so as to form a package layer.
Description
Technical field
The present invention relates to a kind of electron package structure and method for packing thereof, especially about a kind of electron package structure and method for packing thereof that can dwindle its volume.
Background technology
Fig. 1 shows the DC to DC converter encapsulating structure of a prior art.As shown in Figure 1, this structure is a United States Patent (USP) 6,212, a DC to DC converter encapsulating structure (DC-to-DC converter package) that is disclosed for No. 086.DC to DC converter encapsulating structure 100 comprises a system circuit board 120, a copper base material 110 and most electronic components.System circuit board 120 is placed in above the copper base material 110, so copper base material 110 can provide uniform heat sinking function in the bottom of this device.Those electronic components include main transformer 130, outputting inductance 140, synchronous rectifier 150, output capacitor 160 and input capacitor 170; These electronic components be placed on the system circuit board 120 and, and couple mutually through system circuit board 120 inner circuit layouts.One independently out connector be located at system circuit board 120 the right, be couple to system circuit board 120 via flexible circuit board.
Summary of the invention
The purpose of one embodiment of the invention is to provide a kind of electron package structure and method for packing thereof that can dwindle its volume.The purpose of another embodiment is to provide a kind of electron package structure and method for packing thereof that need not use mould.
According to one embodiment of the invention, provide a kind of electron package structure method for packing its comprise following steps.One substrate is provided.One inductance module is provided.The inductance module is engaged in substrate, uses to make defining a space between inductance module and substrate.One glue material is filled in the space that inductance module and substrate defined, to form an encapsulated layer.In one embodiment, aforementioned method for packing more comprises following steps.To be engaged on the body of substrate in order to a chip module that is electrically connected with a circuit of substrate.And the step of aforementioned formation one encapsulated layer comprises makes glue material coating chip module.
In one embodiment, the aforementioned step of a substrate that provides comprises: a body that forms substrate; And, form at least one first connecting portion of substrate at least one side of body.The aforementioned step of an inductance module that provides comprises: an inductance element that forms the inductance module; At least one side at inductance element forms at least one flank section, and makes at least one flank section protrude in inductance element one surface.The aforementioned step that the inductance module is engaged in substrate comprises: make this at least one first connecting portion be engaged in this at least one flank section; With the inductance module is located on the substrate, is used the inductance element that makes the inductance module and this at least one flank section, and the body of substrate between define this space.
In one embodiment, the aforementioned step of a substrate that provides comprises: a body that forms substrate; And, form at least one flank section of substrate, and make this at least one flank section protrude in body one surface at least one side of body.The aforementioned step of an inductance module that provides comprises: an inductance element that forms the inductance module; In at least one side of inductance element, form at least one first connecting portion.The aforementioned step that the inductance module is engaged in substrate comprises: make this at least one first connecting portion be engaged in this at least one flank section; With the inductance module is located on the substrate, is used the inductance element that makes the inductance module, and the body of substrate and this at least one flank section between define this space.
According to one embodiment of the invention, provide an electron package structure to comprise a substrate one inductance module and encapsulated layer.Substrate comprises to be used so that a circuit of electron package structure running.The inductance module makes electron package structure running in order to cooperate with substrate to use, and and substrate between define a space.Encapsulated layer is positioned at this space.Encapsulated layer by a glue material is filled in this space that inductance module and substrate define form.In one embodiment, electron package structure more comprises a chip module, is located on the substrate and in order to be electrically connected with the circuit of substrate.Encapsulated layer coating chip module.In one embodiment, contact with encapsulated layer respectively, and in the contact area of substrate and inductance module, encapsulated layer fills up the interior coarse structure of this contact area of substrate and inductance module in fact in substrate and inductance module.
In one embodiment, substrate comprises a body and at least one first connecting portion.Chip module is located on the body.At least one first connecting portion is located at least one side of body.The inductance module comprises an inductance element and at least one flank section.At least one flank section is located at least one side of inductance element and is opened outstanding inductance element one surface.At least one flank section self-inductance element extends towards the direction of substrate, so that at least one flank section engages first connecting portion.
In one embodiment, substrate comprises a body and at least one flank section.Chip module is located on the body.At least one flank section is located at least one side of body, and outstanding inductance element one surface.The inductance module comprises inductance element and at least one first connecting portion.At least one first connecting portion is located at least one side of inductance element.This at least one flank section is the extension of the direction towards the inductance module from body, so that flank section engages first connecting portion.
In one embodiment, electron package structure is suitable for being arranged on the circuit board, and chip module or inductance module system sees through circuit board and is electrically connected with substrate.
According to one embodiment of the invention, provide a kind of electron package structure its comprise an inductance module and an encapsulated layer.The inductance module comprises an inductance element, one first flank section, second flank section and an encapsulated layer.First flank section is located at a side and outstanding inductance element one surface of inductance element.Second flank section is located at the opposite side and the outstanding inductance element surface of inductance element, use make this table and, first flank section and second flank section form a space.Encapsulated layer is positioned at this space.The width of encapsulated layer can equal the distance between first flank section and second flank section in fact.
In one embodiment, electron package structure more comprises a substrate.Substrate comprises to be used so that a circuit of electron package structure running.The inductance module cooperates with substrate to use makes the electron package structure running, and the surface of inductance module, first flank section and second flank section; And define this space between substrate.In one embodiment, encapsulated layer forms by a glue material is filled in this space.
In one embodiment, see through encapsulated layer and isolate the inductance module and be provided with chip and lead, and make substrate be electrically connected the inductance module, form a stacked structure.Direct and the base plan ways of connecting compared to the general element of prior art, present embodiment more can effectively utilize the space, can dwindle the volume of electron package structure.In one embodiment, utilize to define a space between inductance module and substrate,, can not need additional mold, reduce the cost of making, and change design easily to form encapsulated layer as die cavity.In addition in one embodiment, the inductance module can cover chip, therefore has the electromagnetic interference (EMI) inhibit feature.
Description of drawings
Fig. 1 shows the DC to DC converter encapsulating structure of a prior art;
Fig. 2 A～2F shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention;
Fig. 3 A～3E shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention;
Fig. 3 F shows the schematic perspective view according to one embodiment of the invention electron package structure;
Fig. 4 A is the vertical view of the substrate of one embodiment of the invention;
Fig. 4 B is the end view of the inductance module of one embodiment of the invention;
Fig. 5 A shows the generalized section according to one embodiment of the invention electron package structure;
Fig. 5 B is the enlarged diagram of the region S of Fig. 5 A;
Fig. 5 C is for forming behind the encapsulated layer among the embodiment that substrate and inductance module are engaged the enlarged diagram of a contact area of inductance module and encapsulated layer again with a mould;
Fig. 6 shows cuing open and sketch map according to one embodiment of the invention electron package structure;
Fig. 7 shows the sketch map of an electronics composite set.
Drawing reference numeral:
100 DC to DC converter encapsulating structures
110 copper base materials
120 system circuit boards
130 heat sinking functions
140 outputting inductances
150 synchronous rectifiers
160 output capacitors
170 input capacitors
300 electron package structures
310 substrates
311 first flank section
312 second flank section
313 bodies
321 chips
322 leads
323 knitting layers
330 encapsulated layers
340 inductance modules
341 first pins
342 second pins
343 choke coils
400 electron package structures
410 substrates
411 first connecting portions
412 second connecting portions
413 bodies
440 inductance modules
441 first flank section
442 second flank section
443 choke coils
44a the 3rd connecting portion
44b the 4th connecting portion
Embodiment
Other purposes of the present invention and advantage can further be understood from the technical characterictic that the present invention disclosed.For let above-mentioned and other purposes of the present invention, feature and advantage can be more obviously understandable, special embodiment and the conjunction with figs. of lifting of hereinafter elaborates as follows.
Fig. 2 A～2F shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention.Shown in Fig. 2 A～2D, the method for packing according to one embodiment of the invention electron package structure comprises following steps.
Shown in Fig. 2 A, step S02 a: substrate 310 is provided.In one embodiment, step S02 comprises: a body 313 that forms substrate 310; And, form at least one flank section of substrate 310, and make this at least one flank section protrude in body 313 1 surfaces at least one side of body 313.More specifically, substrate 310 comprises a body 313 and is located at one first flank section 311 and one second flank section 312 of body 313 both sides.In this manual; Substrate is meant the support plate that electron package structure is operated in a system; In substrate, can include one can make electron package structure running a circuit; And the term of " element is electrically connected substrate " is meant that this element is electrically connected the circuit of substrate directly or indirectly, so that this electron package structure can operate in a system.The design of circuit on the manufacturing of substrate and the substrate is to have common knowledge the knowledgeable can accomplish in this area, therefore no longer specifies at this specification.The present invention is not particularly limited the material of substrate, can use the substrate of unlike material according to Different products, and the material of substrate can be lead frame (lead-frame), printed circuit board (PCB) (PCB) or pottery (ceramic), or the combination of said elements etc.When substrate is lead frame, is that this forms a circuit as a conductor, and when substrate is a printed circuit board (PCB) or pottery, in this substrate, more is provided with a circuit layout.In Fig. 2 A embodiment, substrate 310 is a lead frame.
Shown in Fig. 2 B, step S04: a chip module 321 is engaged on the body 313 of substrate 310 (die bond), chip module 321 is in order to be electrically connected with substrate 310.Utilize a knitting layer 314 that chip module 321 is engaged on the body 313 of substrate 310 in one embodiment.In one embodiment, step S04 can also more comprise at least one lead 322 is electrically connected between chip modules 321 and the substrate 310 (wire bond).
Shown in Fig. 2 C; Step S06: bend first flank section 311 and second flank section 312; Make first flank section 311 and second flank section 312 respectively toward extending, use making chip module 321 between first flank section 311 and second flank section 312 away from one of body 313 surperficial direction.
Shown in Fig. 2 D, step S08: an inductance module 340 is provided.Inductance module 340 can be a choke coil (choke) module, first pin 341 and second pin 342 that it defines one first groove 351 and one second groove 352 and comprises a choke coil (choke) 343 and be located at choke coil 343 both sides.Preferable situation is the position of first groove 351 and second groove 352, the position of corresponding first flank section 311 and second flank section 312 respectively.This external inductance module 340 can also include other in order to cooperating the electronic component that makes electron package structure 300 running with substrate 310, and inductance module 340 sees through those electronic components and is electrically connected with first pin 341 and second pin 342.Being designed to of inductance module 340 has common knowledge the knowledgeable in this area can accomplish, and therefore no longer specifies at this specification.
Shown in Fig. 2 E, step S10: inductance module 340 is engaged in substrate 310, uses making inductance module 340 and substrate 310 define a space (or being called die cavity).In the present embodiment, make first flank section 311 and second flank section 312 be engaged in first groove 351 and one second groove 352 respectively.In one embodiment, the shape and the size of the shape of first flank section 311 and the size and first groove 351 are worked in coordination, and use that inductance module 340 is positioned on the substrate 310.In one embodiment, the shape of second flank section 312 and size can also be worked in coordination with the shape and the size of second groove 352.Will be appreciated that the inductance module 340 and the juncture of substrate 310 are not limited to the foregoing description; In one embodiment; First flank section 311 and second flank section 312 can also be respectively a syndeton; And first groove 351 and one second groove 352 can also be respectively another syndeton, and this syndeton and this another syndeton can be worked in coordination, and use that inductance module 340 is engaged in substrate 310.Those syndetons are that this area has common knowledge the knowledgeable and can accomplish, and therefore no longer specify at this specification.
Shown in Fig. 2 F, step S12: plastic rubber material is filled in the die cavity that inductance module 340 and substrate 310 defined, and toasts, form an encapsulated layer 330, so that chip module 321 and lead 322 are encapsulated.At last cut supervisor more again and form single electron package structure 300.
Shown in Fig. 2 F, according to one embodiment of the invention, electron package structure 300 comprises a substrate 310, a chip module 321, at least one lead 322, an encapsulated layer 330 and an inductance module 340.Substrate 310 comprises a body 313 and is located at one first flank section 311 and one second flank section 312 of body 313 both sides.Chip module 321 is located on the body 313 of substrate 310, and those leads 322 are electrically connected between chip module 321 and the substrate 310.Encapsulated layer 330 is located on the body 313 of substrate 310 and is covered chip module 321 and lead 322.Encapsulated layer 330 is positioned at the space that inductance module 340 and substrate 310 are defined.And encapsulated layer 330 be by with one by the plastic rubber material of heat fusing be filled in the space that inductance module 340 and substrate 310 defined and cool off form.Inductance module 340 defines one first groove 351 and one second groove 352 and comprises a choke coil 343 and be located at first pin 341 and second pin 342 of choke coil 343 both sides.First flank section 311 of substrate 310 and second flank section 312 extend to first pin 341 and second pin 342 of inductance module 340 towards inductance module 340 directions, and are electrically connected first pin 341 and second pin 342 respectively.
In one embodiment, the body 313 of substrate 310 can be printed circuit board (PCB) or pottery, and first flank section 311 and second flank section 312 can be for being located at the lead frame of body 313 both sides.According to this design, even overcome the problem that can't bend during as substrate with printed circuit board (PCB) or pottery.In an embodiment of the present invention, electron package structure 300 can be a DC to DC converter encapsulating structure.
According to present embodiment, have the following advantages at least compared to prior art.
In the present embodiment, see through first flank section 311 of substrate 310 and first pin 341 and second pin 342 that second flank section 312 is electrically connected inductance module 340, form a stacked structure.Direct and the base plan ways of connecting compared to the general element of prior art of Fig. 1, present embodiment more can effectively utilize the space, can dwindle the volume of electron package structure 300.
Fig. 3 A～3D shows the generalized section according to electron package structure in each step of method for packing of one embodiment of the invention.Shown in Fig. 3 A～3D, the method for packing according to one embodiment of the invention electron package structure comprises following steps.
Shown in Fig. 3 A, step S22 a: substrate 410 is provided.In one embodiment, step S22 comprises: a body 413 that forms substrate 410; And, form at least one connecting portion of substrate 410 at least one side of body 413.Therefore, substrate 410 comprises a body 413 and is located at one first connecting portion 411 and one second connecting portion 412 of body 413 both sides.In one embodiment, include a circuit that can make the electron package structure running in the substrate 410.The present invention is not particularly limited the material of substrate, and the material of substrate can be lead frame (lead-frame), printed circuit board (PCB) (PCB) or pottery (ceramic) etc.Fig. 4 A is the vertical view of the substrate of one embodiment of the invention.Shown in Fig. 4 A, in one embodiment, an opening or a breach that first connecting portion 411 and second connecting portion 412 can go out for 410 boundaries of substrate, and its shape do not limit, and can also be a projection (not shown) in one embodiment in addition.More specifically, in one embodiment, substrate 410 is a lead frame, and step S22 comprises following steps.Step S202: (lead-frame) etches partially to lead frame.Step S204: silver-plated to the lead frame single face.
Shown in Fig. 3 B, step S24: a chip module 321 is engaged on the body 413 of substrate 410 (die bond), chip module 321 is in order to be electrically connected with substrate 410.In one embodiment, step S24 more comprises at least one lead 322 is electrically connected between chip modules 321 and the substrate 410 (wirebond).More specifically, in one embodiment, step S24 comprises following steps.Step S402: some glue, also be about to knitting layer 414 and be applied on the substrate 410, knitting layer 414 can be conducting resinl or non-conductive adhesive.Step S404: last slice (Die Bond) also is about to chip module 321 and is located on the knitting layer 414.Step S406: routing, even also lead 322 connects chip module 321 and lead frame (Au WireBond).
Shown in Fig. 3 C, step S26: an inductance module 440 is provided.In one embodiment, step S26 comprises: an inductance element that forms inductance module 400; And, form at least one flank section, and make this at least one flank section protrude in this inductance element one surface at least one side of inductance element.More specifically, inductance module 440 can be a choke coil (choke) module, and it comprises one and is the choke coil of inductance element (choke) 443 and one first flank section 441 and one second flank section 442.First flank section 441 and second flank section 442 are located at the both sides of choke coil 443 respectively, protrude in choke coil 443 lower surface and court away from the extension of choke coil 443 bottom direction, and form one the 3rd connecting portion 44a and one the 4th connecting portion 44b on its free end.The shape of the shape of the 3rd connecting portion 44a and first connecting portion 411 is worked in coordination; The shape of the shape of the 4th connecting portion 44b and second connecting portion 412 is worked in coordination; Use making the 3rd connecting portion 44a possess the function that engages with first connecting portion 411, the 4th connecting portion 44b possesses the function that engages with second connecting portion 412.Fig. 4 B is the end view of the inductance module 440 of one embodiment of the invention.Shown in Fig. 4 B, in the present embodiment, the 3rd connecting portion 44a (and the 4th connecting portion 44b) can be a projection, and it can also be an opening or a breach in one embodiment.This external inductance module 440 can also include other in order to cooperating the electronic component that makes electron package structure 400 running with substrate 410, and inductance module 440 sees through those electronic components and is electrically connected with substrate 410, uses that electron package structure 400 can be operated.Being designed to of inductance module 440 has common knowledge the knowledgeable in this area can accomplish, and therefore no longer specifies at this specification.
Shown in Fig. 3 D; Step S28: make the 3rd connecting portion 44a be engaged in first connecting portion 411 and engage; The 4th connecting portion 44b is engaged in second connecting portion 412; So that inductance module 440 is located on the substrate 410,410 of inductance module 440 and substrates define a space, and more specifically choke coil (choke) 443, first flank section 441, second flank section 442 and body 413 define this space (or being called die cavity).In addition; Can more add melted material; Utilize metal welding mode, with the joint welding in addition of the 3rd connecting portion 44a and first connecting portion 411, with the joint welding in addition of the 4th connecting portion 44b and second connecting portion 412; Further to strengthen the 3rd and four connecting portion 44a and 44b and first and two connecting portions 411 and 412 s' bond strength, make inductance module 440 can firmly be electrically connected on substrate 410.Melted material can be added with auxiliary material again, and auxilliary dead-wood material can be conductor or non-conductor.
Shown in Fig. 3 E, step S30: a glue material is filled in the space that inductance module 440 and substrate 410 defined, to form an encapsulated layer 330.In one embodiment, be filled in the die cavity that inductance module 440 and substrate 410 defined by the plastic rubber material of heat fusing, and toast and cool off, form an encapsulated layer 330, so that chip module 321 and lead 322 are encapsulated with one.At last cut supervisor more again and form single electron package structure 300.In the present embodiment, shown in Fig. 3 F (will in then state), first flank section 441 and second flank section 442 form a plane respectively, or form a face wall.After inductance module 440 is positioned substrate 410, can define a space with substrate 410, be formed with opening at these two ends, space by the choke coil (choke) 443 of inductance module 440, first flank section 441 and second flank section 442.Point glue equipment can inject plastic rubber material in this space from opening.Because first flank section 441 and second flank section 442 can be blocked flowing of plastic rubber material, after plastic rubber material cure package layer 330 formed, the width of encapsulated layer 330 can equal the distance of 442 of first flank section 441 and second flank section in fact.
Fig. 3 F shows the schematic perspective view according to one embodiment of the invention electron package structure.In Fig. 3 F, be the not shown encapsulated layer of the internal structure of knowing electron package structure.Shown in Fig. 3 E and 3F, according to one embodiment of the invention, electron package structure 400 comprises a substrate 410, a chip module 321, at least one lead 322, an encapsulated layer 330 and an inductance module 440.Substrate 410 comprises a body 413 and is located at one first connecting portion 411 and one second connecting portion 412 of body 413 both sides.In the present embodiment, first connecting portion 411 and second connecting portion 412 opening or a breach that can go out for 410 boundaries of substrate.Chip module 321 is located on the body 413 of substrate 410, and those leads 322 are electrically connected between chip module 321 and the substrate 410.Inductance module 440 can be a choke coil (choke) module, and it comprises a choke coil (choke) 443 and one first flank section 441 and one second flank section 442.First flank section 441 and second flank section 442 are located at the both sides of choke coil 443 respectively, protrude in choke coil 443 bottoms and extend towards substrate 410 directions, and form one the 3rd connecting portion 44a and one the 4th connecting portion 44b on its free end.Utilize metal welding mode, make the 3rd connecting portion 44a be fused to first connecting portion, 411, the four connecting portion 44b and be fused to second connecting portion 412, so that inductance module 440 is located on the substrate 410,410 of inductance module 440 and substrates define a space.Encapsulated layer 330 is located at inductance module 440 and 410 spaces that define of substrate and is covered chip module 321 and lead 322.And encapsulated layer 330 by with one by the plastic rubber material of heat fusing be filled in the space that inductance module 440 and substrate 410 defined and cool off form.
According to present embodiment, compared to the foregoing description one of which that has the following advantages at least:
1, shown in Fig. 3 E, because first flank section 441 and second flank section 442 are extended from the body 413 of choke coil 443 to substrate 410, inductance module 440 can cover chip module 321, therefore can have the electromagnetic interference (EMI) inhibit feature.
2, the heat that produced of chip module 321 except can be from substrate 410 backside heats, can also see through first flank section 441 and second flank section 442 conduct to choke coil 443 from substrate 410, and from 440 heat radiations of inductance module, have preferable radiating effect.
3, utilize 410 of inductance module 440 and substrates to define a die cavity, therefore do not need additional mold, reduce the cost of making, and change design easily.
In addition, in one embodiment, the electron package structure 300 of Fig. 2 F and Fig. 3 E can also have following advantage.Among the embodiment that after forming encapsulated layer, again substrate and inductance module is engaged with a mould; Need reserve a required error distance when enough placing the distance of mould and placing mould because of manufacturing process is limited to the distance H of lead between encapsulated layer, and need carry out accurate contraposition mould.Yet according to the embodiment of Fig. 2 F, the shape of the shape of first flank section 311 and the size and first groove 351 and size are worked in coordination and/or the shape and the size of second flank section 312 can also be worked in coordination with the shape and the size of second groove 352; Embodiment according to Fig. 3 E; Because the shape of the 3rd connecting portion 44a and the shape of first connecting portion 411 are worked in coordination; The shape of the shape of the 4th connecting portion 44b and second connecting portion 412 is worked in coordination; When the 3rd and four connecting portion 44a and 44b with after first and two connecting portions 411 and 412 engage one another, can reach positioning function, therefore simplifying needs the precisely program of location when using mould.Can also dwindle the distance H between lead to encapsulated layer, therefore can further dwindle the volume of electron package structure.
Fig. 5 A shows the generalized section according to one embodiment of the invention electron package structure.Fig. 5 A embodiment electron package structure 400a is similar in appearance to Fig. 3 E embodiment electron package structure 400, so the identical symbol of components identical use, and omits its detailed description.In one embodiment, body 413 can also be provided with other electronic component except being provided with a chip module 321, with so that electron package structure 400a has various function.Shown in Fig. 5 A, on body 413, also be provided with a resistance 325, an electric capacity 326 and a MOS transistor 327.
In addition, in the present embodiment, and encapsulated layer 330 be by with one by the plastic rubber material of heat fusing be filled in the space that inductance module 440 and substrate 410 defined and cool off form.And in substrate 410 and inductance module 440 contacts with encapsulated layer 330 respectively and in the contact area of substrate 410 and inductance module 440, encapsulated layer 330 fills up the coarse structure in this contact area of substrate 410 and inductance module 440 in fact.Region S shown in Fig. 5 A, region S are the contact area of 330 of side wing 442 and the encapsulated layers of inductance module 440.Fig. 5 B is the enlarged diagram of the region S of Fig. 5 A.Under microcosmic, in the contact area S that the side wing 442 of inductance module 440 and encapsulated layer are 330, the surface of side wing 442 can be formed with a coarse structure.When encapsulated layer 330 be by with one be filled in the space that inductance module 440 and substrate 410 defined by the plastic rubber material of heat fusing and cool off when forming, encapsulated layer 330 can fill up the interior coarse structure of contact area S in fact.Fig. 5 C is for forming behind the encapsulated layer among the embodiment that substrate and inductance module are engaged the enlarged diagram of a contact area of inductance module and encapsulated layer again with a mould.Shown in Fig. 5 C; According to form behind the encapsulated layer again the embodiment that substrate and inductance module are engaged with a mould; Under microcosmic, in the contact area A that inductance module 440 and encapsulated layer are 330, the border L of encapsulated layer 330; Only can contact the interior coarse structure of contact area A of meeting inductance module, and can not fill up the coarse structure in the contact area A.
Fig. 6 shows the generalized section according to one embodiment of the invention electron package structure.Fig. 6 embodiment electron package structure 400b is similar in appearance to Fig. 5 embodiment electron package structure 400a, so the identical symbol of components identical use, and omits its detailed description.As discussed previously, the present invention does not limit the material of substrate 410, and the material of substrate 410 can be lead frame (1ead-frame), printed circuit board (PCB) (PCB) or pottery (ceramic) etc.In the present embodiment, substrate 410 adopts compound material, and its body 413 includes a printed circuit board (PCB) 31, one first lead frame 32, one second lead frame 33, a privates frame 34.Can be with being arranged at printed circuit board (PCB) 31 than complicated circuitry, and make printed circuit board (PCB) 31 produce more pin in order to be electrically connected with chip module 321, at last printed circuit board (PCB) 31 is arranged on first lead frame 32.The heat sinking function of first lead frame 32 is superior to printed circuit board (PCB) 31, therefore according to the design of electron package structure 400b, can comprise than complicated circuitry, can also have preferable radiating effect simultaneously.
Fig. 7 shows the sketch map of an electronics composite set (electrical assembly), this electronics composite set include be installed on the circuit board according to one embodiment of the invention electron package structure.As shown in Figure 7, electronics composite set 500 comprises the electron package structure 400 of a circuit board 510 and Fig. 3 E embodiment.Circuit board 510 includes a circuit.Electron package structure 400 is located on the circuit board 510, to form the electronics composite set of another form.In the present embodiment, chip module 321 or inductance module 440 can directly not be electrically connected to substrate 410, but are electrically connected substrate 410 more indirectly through the circuit of circuit board 510.
Though the present invention discloses as above with preferred embodiment; Right its is not that any those skilled in the art are not breaking away from the spirit and scope of the present invention in order to qualification the present invention; When can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim scope person of defining.In addition, arbitrary embodiment of the present invention or claim must not reached whole purposes or advantage or the characteristics that the present invention discloses.In addition, summary part and title only are the usefulness that is used for assisting the patent document search, are not to be used for limiting interest field of the present invention.
Claims (26)
1. the method for packing of an electron package structure is characterized in that, said method for packing comprises:
One substrate is provided;
One inductance module is provided;
Said inductance module is engaged in said substrate, uses to make between said inductance module and said substrate defining a space;
One glue material is filled in the said space that said inductance module and said substrate defined, to form an encapsulated layer.
2. method for packing as claimed in claim 1 is characterized in that, said method for packing more comprises:
To be engaged in order to a chip module that is electrically connected with a circuit of said substrate on this body of said substrate,
The step of wherein said formation one encapsulated layer comprises: make said glue material coat said chip module.
3. method for packing as claimed in claim 1 is characterized in that,
The said step of a substrate that provides comprises:
Form a body of said substrate; And
In at least one side of said body, form at least one first connecting portion of said substrate,
The said step of an inductance module that provides comprises:
Form an inductance element of said inductance module;
At least one side at said inductance element forms at least one flank section, and makes said at least one flank section protrude in said inductance element one surface,
The said step that said inductance module is engaged in said substrate comprises:
Make said at least one first connecting portion be engaged in said at least one flank section; With said inductance module is located on the said substrate, is used the said inductance element that makes said inductance module and said at least one flank section, and the said body of said substrate between define said space.
4. method for packing as claimed in claim 3 is characterized in that,
The step of at least one flank section of said formation is included in and forms one second connecting portion on the free end of said at least one flank section, and
The said step that makes said at least one first connecting portion be engaged in said at least one flank section comprises makes said at least one first connecting portion be engaged in said second connecting portion.
5. method for packing as claimed in claim 4 is characterized in that, the shape of the shape of said first connecting portion and said second connecting portion is worked in coordination, and uses making said inductance element be located in said substrate.
6. method for packing as claimed in claim 5 is characterized in that, saidly makes said first connecting portion be engaged in the step of said second connecting portion, more comprises and utilizes said second connecting portion of the further welding of metal welding mode and said first connecting portion.
7. method for packing as claimed in claim 1 is characterized in that,
The said step of a substrate that provides comprises:
Form a body of said substrate; And
In at least one side of said body, form at least one flank section of said substrate, and make said at least one flank section protrude in said body one surface,
The said step of an inductance module that provides comprises:
Form an inductance element of said inductance module;
In at least one side of said inductance element, form at least one first connecting portion, the said step that said inductance module is engaged in said substrate comprises:
Make said at least one first connecting portion be engaged in said at least one flank section; With said inductance module is located on the said substrate, is used the said inductance element that makes said inductance module, and the said body of said substrate and said at least one flank section between define said space.
8. method for packing as claimed in claim 7 is characterized in that, the step of at least one flank section of said formation is included in and forms one second connecting portion on the free end of said at least one flank section, and
The said step that makes said at least one first connecting portion be engaged in said at least one flank section comprises makes said at least one first connecting portion be engaged in said second connecting portion.
9. like each described method for packing of claim 1 to 8, it is characterized in that said inductance module is a choke coil module, and said inductance element is a choke coil.
10. an electron package structure is characterized in that, said electron package structure comprises:
One substrate comprises and uses so that a circuit of said electron package structure running;
One inductance module makes the running of said electron package structure in order to cooperate with said substrate to use, and and said substrate between define a space,
One encapsulated layer is positioned at said space,
Wherein said encapsulated layer be by a glue material is filled in the said space that said inductance module and said substrate define form.
11. electron package structure as claimed in claim 10 is characterized in that, described electron package structure more comprises a chip module, be located on the said substrate and in order to being electrically connected with the said circuit of said substrate,
Wherein said encapsulated layer coats said chip module.
12. electron package structure as claimed in claim 10; It is characterized in that; Contact with said encapsulated layer respectively at said substrate and said inductance module; And in the contact area of said substrate and said inductance module, said encapsulated layer fills up the interior coarse structure of said contact area of said substrate and said inductance module in fact.
13. electron package structure as claimed in claim 11 is characterized in that,
Said substrate comprises:
One body, said chip module are located on the said body; And
At least one first connecting portion is located at least one side of said body,
Said inductance module comprises:
One inductance element; And
At least one flank section is located at least one side of said inductance element and is given prominence to said inductance element one surface,
Wherein said at least one flank section is the extension of the direction towards said substrate from said inductance element, so that said at least one flank section engages said first connecting portion.
14. electron package structure as claimed in claim 13 is characterized in that,
The free end of said at least one flank section forms one second connecting portion, and said second connecting portion engages said first connecting portion.
15. electron package structure as claimed in claim 14 is characterized in that,
Said second connecting portion has conductivity,
Said first connecting portion is electrically connected to the said circuit of said substrate, and
Said second connecting portion utilizes metal welding mode to engage with said first connecting portion, uses making said inductance module be electrically connected said substrate.
16. electron package structure as claimed in claim 14 is characterized in that, the shape of the shape of said first connecting portion and said second connecting portion is worked in coordination, and uses making said inductance element be located in said substrate.
17. electron package structure as claimed in claim 16 is characterized in that, said first connecting portion opening or the breach that this substrate defined of serving as reasons, and said second connecting portion is a projection.
18. electron package structure as claimed in claim 17 is characterized in that, said second connecting portion utilizes metal welding mode to engage with said first connecting portion.
19. electron package structure as claimed in claim 10 is characterized in that, said substrate is a lead frame, a printed circuit board (PCB) or a pottery; It perhaps is wantonly combination more than two in said lead frame, said printed circuit board (PCB) or the said pottery.
20. electron package structure as claimed in claim 10 is characterized in that, said inductance module is a choke coil module.
21. electron package structure as claimed in claim 10 is characterized in that, said electron package structure more comprises at least one electronic component, and wherein said electronic component is arranged on the said substrate.
22. electron package structure as claimed in claim 10 is characterized in that,
Said substrate comprises:
One body, said chip module are located on the said body; And
At least one flank section is located at least one side of said body, and gives prominence to said inductance element one surface,
Said inductance module comprises:
One inductance element; And
At least one first connecting portion is located at least one side of said inductance element,
Wherein said at least one flank section is the extension of the direction towards said inductance module from said body, so that said flank section engages said first connecting portion.
23. like each described electron package structure of claim 10 to 22, it is characterized in that said electron package structure is suitable for being arranged on the circuit board, and said chip module or said inductance module see through said circuit board and are electrically connected with said substrate.
24. an electron package structure is characterized in that, said electron package structure comprises:
One inductance module comprises:
One inductance element;
One first flank section is located at a side of said inductance element and is given prominence to said inductance element one surface; And
One second flank section is located at the opposite side of said inductance element and the said surface of giving prominence to said inductance element, uses making said surface, said first flank section and said second flank section form a space; And
One encapsulated layer is positioned at said space,
The width of wherein said encapsulated layer equals or is substantially equal to the distance between said first flank section and said second flank section.
25. electron package structure as claimed in claim 24 is characterized in that, said electron package structure more comprises a substrate, comprise with so that a circuit of said electron package structure running,
Wherein said inductance module cooperates with said substrate to use makes said electron package structure running, and the said surface of said inductance module, said first flank section and said second flank section; And define said space between said substrate.
26. electron package structure as claimed in claim 25 is characterized in that, said encapsulated layer forms by a glue material is filled in the said space.
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| CN201510168652.0A CN104934188B (en) | 2010-08-26 | 2010-08-26 | Electron package structure and its method for packing |
| CN201510168662.4A CN104952854B (en) | 2010-08-26 | 2010-08-26 | Electron package structure and its packaging method |
| CN201010265449.2A CN102376594B (en) | 2010-08-26 | 2010-08-26 | Electronic package structure and package method thereof |
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| CN107808879A (en) * | 2017-11-20 | 2018-03-16 | 深圳顺络电子股份有限公司 | A kind of Switching Power Supply module and its method for packing |
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| EP3364429B1 (en) * | 2017-02-16 | 2019-08-14 | Mitsubishi Electric R&D Centre Europe B.V. | Inductive assembly |
| CN112990413B (en) * | 2021-03-09 | 2023-07-25 | 深圳源明杰科技股份有限公司 | Coil dispensing method, device, equipment and computer readable storage medium |
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Also Published As
| Publication number | Publication date |
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| CN104952854A (en) | 2015-09-30 |
| CN104934188B (en) | 2018-04-10 |
| CN104952854B (en) | 2018-07-17 |
| CN102376594B (en) | 2015-05-20 |
| CN104934188A (en) | 2015-09-23 |
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