CN102368525A - Composite quantum well structure raising carrier composite efficiency and preparation method thereof - Google Patents
Composite quantum well structure raising carrier composite efficiency and preparation method thereof Download PDFInfo
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- CN102368525A CN102368525A CN201110330659XA CN201110330659A CN102368525A CN 102368525 A CN102368525 A CN 102368525A CN 201110330659X A CN201110330659X A CN 201110330659XA CN 201110330659 A CN201110330659 A CN 201110330659A CN 102368525 A CN102368525 A CN 102368525A
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Abstract
The invention discloses a composite quantum well structure raising carrier composite efficiency and a preparation method thereof. According to the structure, defect density of a quantum well zone can be effectively reduced, composite efficiency of an electron and a cavity in an illuminant quantum well zone are raised, simultaneously, a thickness of a well of a low temperature shallow well structure is smaller than a thickness of a well of the illuminant quantum well zone, superposition of two multi-quantum well luminous spectrums is prevented, a full width at half maximum is decreased, and luminance is raised. The invention also relates to a preparation method of a GaN based LED epitaxial wafer.
Description
Technical field
The present invention relates to semiconductor, improve the composite quantum well structure and the preparation method of charge carrier combined efficiency in especially a kind of light-emitting diode.
Background technology
Can luminescence phenomenon use from it is found that after the semi-conducting material energising to the LED lamp of now high brightness.LED lighting technology high speed development has brought huge transition to people's life.Along with the increase of brightness, the reduction of price, ultra-bright LED has obtained high speed development.As new and effective solid light source, LED has a high potential, and is the another leap after incandescent lamp, fluorescent lamp on the illumination history, has caused the revolution of throwing light on for the third time, and its economic benefit and social effect are huge.Application for white light LEDs; It is not only lamp for general lighting; Application comprises expand to that mobile phone uses backlight, keyboard back light, the photoflash lamp of camera, the head lamp that LCD TV (LCD-TV) is backlight, automobile is used, and so medical lamp or the like is increasingly extensive along with range of application; Produce the white light technology that is fit to different field, just becoming quite important also is the development trend that everybody was concerned about.
The develop rapidly of III – V nitride wide bandgap semiconductor aspect LED and application have obtained the approval of industry fully, through adjustment indium gallium nitrogen (In
aGa
1-aN) content of In in can be realized from the ultraviolet of gallium nitride (GaN) luminously to the full spectrum of ruddiness, and the realization that is embodied as LED display and the development of red-green-blue light-emitting diode provide assurance.In
aGa
1-aIn the N light-emitting diode, the combined efficiency of charge carrier becomes the key of light-emitting diode, though realized LED illumination and panchromatic demonstration, people are being to improve constantly a large amount of energy of luminous efficiency input also.Multi-quantum pit structure wherein is to realize efficient luminous key.
Summary of the invention
The object of the present invention is to provide a kind of composite quantum well structure that improves the charge carrier combined efficiency; This structure can effectively reduce the defect concentration of quantum well region; Improve electronics and the hole combined efficiency at the luminescent quantum well region, the thickness of the trap of the shallow quantum well structure of low temperature is littler than the thickness of the trap of luminescent quantum well structure simultaneously, can prevent the coincidence of two multi-quantum pit structure luminous spectrums; Reduce halfwidth, improve luminosity.Another object of the present invention provides the preparation method of this structure.
Technical scheme of the present invention is: 1, a kind of composite quantum well structure that improves the charge carrier combined efficiency, the structure of this LED epitaxial slice is followed successively by from bottom to top: substrate layer, gallium nitride low temperature buffer layer, unadulterated high-temperature ammonolysis gallium layer, Si doped n type gallium nitride layer, multi-quantum pit structure (MQW), p type aluminum gallium nitride electronic barrier layer, p type gallium nitride layer, p type gallium nitride contact layer, multi-quantum pit structure MQW comprise high temperature multi-quantum pit structure, the shallow quantum well structure of low temperature, chemiluminescence multi-quantum pit structure from the bottom up successively.
The shallow quantum well structure of high temperature comprises indium gallium nitrogen/gallium nitride (In in 2 to 8 cycles
xGa
1-xN/GaN, 0＜x＜0.5) MQW, the thickness of trap is between 2nm to 3nm, and the thickness at base is between 15 to 25nm, and wherein the growth temperature at trap and base is identical, between 820 ℃ to 920 ℃; Growth pressure is identical, between 100Torr to 500Torr.The shallow quantum well structure MQW of low temperature comprises the In in 2 to 15 cycles
yGa
1-yN/GaN (0＜y＜0.5) MQW; The thickness of trap is between 1nm to 3nm, and growth temperature is between 720 ℃ to 820 ℃; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃.The In in 2 to 15 cycles
yGa
1-yThe thickness of N 0＜y＜0.5 can be the same, also thickening or attenuation or thickness replace gradually gradually.Chemiluminescence multi-quantum pit structure MQW comprises the In in 1 to 10 cycle
yGa
1-yN/GaN 0＜y＜0.5 MQW is formed; The thickness of trap is between 2nm to 5nm, and growth temperature is between 720 ℃ to 820 ℃; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃; The In in 1 to 10 cycle
yGa
1-yThe thickness of N 0＜y＜0.5 can be the same, also thickening or attenuation or thickness replace gradually gradually.Trap In in the shallow quantum well structure of high temperature
xGa
1-xThe trap In of the shallow quantum well structure of growth temperature lower temperature of N layer
yGa
1-yIt is high that the growth temperature of N is wanted.
Trap In in the shallow quantum well structure of high temperature
xGa
1-xN layer x scope is 0＜x＜0.5, the trap In of the shallow quantum well structure of low temperature
yGa
1-yThe y scope is 0＜y＜0.5 among the N, and x＜y is arranged.In the chemiluminescence quantum well structure in the shallow quantum well structure of thickness lower temperature of each trap the thickness of any trap thick.
Improve the preparation method of the composite quantum well structure of charge carrier combined efficiency, its step: ⑴ at first annealed backing material 1-10 minute in hydrogen atmosphere, the clean substrate surface, and temperature is controlled between 1050 ℃ and 1180 ℃, carries out nitrogen treatment then.⑵ drop to temperature between 450 ℃ and 600 ℃, the thick low temperature GaN nucleating layer of growth 15 to 35 nm, and during this growth course, growth pressure is between 400 Torr to 600Torr, and V/III mol ratio is between 500 to 3000.⑶ behind the low temperature buffer layer growth ending, low temperature buffer layer is carried out annealing in process in position, annealing temperature is between 1000-1200 ℃, and the time is between 5 minutes to 10 minutes.⑷ after the annealing, between 1200 ℃, growth thickness is the u-GaN layer of 0.8 μ m to 5 μ m with adjustment to 1000 ℃, and during this growth course, growth pressure is between 100 Torr to 760 Torr, and V/III mol ratio is between 300 to 3000.⑸ behind u-GaN 3 growth endings, growth one deck Si doped n-GaN layer, thickness is between 1-5 μ m; Growth temperature is between 1000 ℃ to 1200 ℃; Growth pressure is between 50 Torr to 760 Torr, and V/III mol ratio is between 300 to 3000, and the Si doping content is 10
17Cm
-3-10
19Cm
-3Between.⑹ after n-GaN layer growth finishes, the high temperature multi-quantum pit structure MQW 501 that begins to grow, high temperature multi-quantum pit structure MQW 501 is by the In in 2 to 8 cycles
xGa
1-xN/GaN 0＜x＜0.5 MQW is formed.The thickness of trap is between 2nm to 3nm, and the thickness at base is between 15 to 25nm, and wherein the growth temperature at trap and base is identical, between 820 ℃ to 920 ℃; Growth pressure is identical, between 100Torr to 500Torr; V/III mol ratio is identical, between 300 to 5000.⑺ behind high temperature multi-quantum pit structure MQW 501 growth endings, the shallow quantum well structure MQW 502 of beginning growing low temperature, the shallow quantum well structure MQW of low temperature comprises the In in 2 to 15 cycles
yGa
1-yN/GaN 0＜y＜0.5 MQW.The thickness of trap is between 1nm to 3nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.⑻ behind the shallow quantum well structure MQW of the low temperature growth ending, beginning growing low temperature luminescent quantum well structure MQW, chemiluminescence multi-quantum pit structure MQW comprises the In in 1 to 10 cycle
yGa
1-yN/GaN 0＜y＜0.5 MQW is formed.The thickness of trap is between 2nm to 5nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.⑼ behind the chemiluminescence multi-quantum pit structure MQW growth ending, temperature is risen between 800 ℃ to 1080 ℃, between the growth pressure 50Torr to 200Torr, between V/III mol ratio 1000 to 20000, the p-Al between the growth thickness 10nm to 200nm
zGa
1-zN (0.1＜z＜0.5) electronic barrier layer.This layer energy gap can be controlled between 4eV and the 5.5eV greater than the energy gap of last barrier.⑽ p-Al
zGa
1-zBehind N (0.1＜z＜0.5) the electronic barrier layer growth ending, the p type gallium nitride layer of a layer thickness between 0.1 μ m to 0.8 μ m of growing, its growth temperature is between 850 ℃ to 1080 ℃, and growth air pressure is between 100 Torr-300 Torr.⑾ after p type gallium nitride layer finished, the layer thickness of growing was at the P type contact layer of 0.05-0.3 μ m, and its growth temperature is between 850 ℃ to 1050 ℃, and between the growth pressure 100Torr to 300Torr, V/III mol ratio is between 1000 to 20000.
Epitaxial growth is reduced to the temperature of reaction chamber between 650 to 850 ℃ after finishing, and annealing in process is 5 to 15 minutes in the pure nitrogen gas atmosphere, reduces to room temperature then, finishes epitaxial growth.
Epitaxial wafer to growth cleans then, semiconducter process such as deposition, photoetching and etching process single small size chip.
The invention has the advantages that: adopted compound multi-quantum pit structure, the high temperature multiquantum well region can effectively reduce the defect concentration of quantum well region, and the shallow quantum well region of low temperature can effectively be collected charge carrier once more; Special electronics; Improve electronics and the hole combined efficiency at the luminescent quantum well region, the thickness of the trap of the shallow quantum well structure of low temperature is littler than the thickness of the trap of luminescent quantum well region simultaneously, can prevent the coincidence of two multiple quantum well light emitting spectrums; Reduce halfwidth, improve luminosity.
Description of drawings
Fig. 1 is common LED structural representation;
Fig. 2 improves preparation method's structural representation of the composite quantum well structure of charge carrier combined efficiency for the present invention.
Embodiment
Below in conjunction with accompanying drawing and concrete embodiment to the present invention: the preparation method who improves the composite quantum well structure of charge carrier combined efficiency in a kind of light-emitting diode does further explanation.
As shown in Figure 2ly provided specific embodiment of the present invention:
(1) at first backing material 1 was annealed in hydrogen atmosphere 8 minutes, the clean substrate surface, temperature is controlled between 1050 ℃ and 1180 ℃, carries out nitrogen treatment then.
(2) temperature is dropped between 450 ℃ and 600 ℃, the thick low temperature GaN nucleating layer 2 of growth 15 to 35 nm, during this growth course, growth pressure is between 400 Torr to 600Torr, and V/III mol ratio is between 500 to 3000.
(3) behind low temperature buffer layer 2 growth endings, low temperature buffer layer 2 is carried out annealing in process in position, annealing temperature between 1000-1200 ℃, reasonable be temperature between 1050-1150 ℃, the time is between 5 minutes to 10 minutes.
(4) after the annealing, between 1100 ℃, growth thickness is the u-GaN layer 3 of 0.8 μ m to 5 μ m with adjustment to 1000 ℃, and during this growth course, growth pressure is between 100 Torr to 500 Torr, and V/III mol ratio is between 300 to 3000.
(5) behind u-GaN 3 growth endings, growth one deck Si doped n-GaN layer 4, thickness between 1-5 μ m, growth temperature between 1000 ℃-1200 ℃, growth pressure between 100Torr to 500Torr the Si doping content 10
18Cm
-3-10
19Cm
-3Between.
(6) behind n-GaN layer 4 growth ending, the In in 4 cycles that begin to grow
xGa
1-xN/GaN (0＜x＜0.5) MQW is formed.The thickness of trap is between 2nm to 3nm, and the thickness at base is between 15 to 25nm, and wherein the growth temperature at trap and base is identical, between 820 ℃ to 920 ℃; Growth pressure is identical, between 100Torr to 500Torr; V/III mol ratio is identical, between 300 to 5000.
(7) behind high temperature multi-quantum pit structure MQW 501 growth endings, the In in 6 cycles that begin to grow
yGa
1-yThe shallow SQW of N/GaN (0＜y＜0.5) is formed.The thickness of trap is between 1nm to 3nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.
(8) behind shallow quantum well structure MQW 502 growth endings of low temperature, the In in 4 cycles that begin to grow
yGa
1-yThe luminous MQW of N/GaN (0＜y＜0.5).The thickness of trap is between 2nm to 5nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of useful is this trap is thick than the thickness of the trap of step (7) growth.The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.
(9) behind chemiluminescence multi-quantum pit structure MQW 503 growth endings, temperature is risen between 800 ℃ to 1080 ℃, between the growth pressure 50Torr to 200Torr, between V/III mol ratio 1000 to 20000, the p-Al between the growth thickness 10nm to 200nm
zGa
1-zN (0.1＜z＜0.5) electronic barrier layer 6.This layer energy gap can be controlled between 4eV and the 5.5eV greater than the energy gap of last barrier.
(10) p-Al
zGa
1-zBehind N (0.1＜z＜0.5) electronic barrier layer 6 growth endings, the p type gallium nitride layer 7 of a layer thickness between 0.1 μ m to 0.8 μ m of growing, its growth temperature is between 850 ℃ to 1080 ℃, and growth air pressure is between 100 Torr-300 Torr.
(11) after p type gallium nitride layer 7 finishes; The P type contact layer 8 of a layer thickness of growing at 0.05-0.3 μ m; Its growth temperature is between 850 ℃ to 1050 ℃, and between the growth pressure 100Torr to 300Torr, V/III mol ratio is between 1000 to 20000.
Epitaxial growth is reduced to the temperature of reaction chamber between 650 ℃ to 850 ℃ after finishing, and annealing in process is 5 to 15 minutes in the pure nitrogen gas atmosphere, reduces to room temperature then, finishes epitaxial growth.
Epitaxial wafer to growth cleans then, semiconducter process such as deposition, photoetching and etching process the led chip that single size is 10 * 16 mil.Through the led chip test, measuring current 20mA, single little chip optical output power is 24.5 mW, operating voltage 3.05V, and adopt common multi-quantum pit structure growth pattern, and the operating voltage of single little chip of identical chips processing procedure is 2.8V, brightness has only 18mW.
(1) at first backing material 1 was annealed in hydrogen atmosphere 8 minutes, the clean substrate surface, temperature is controlled between 1050 ℃ and 1180 ℃, carries out nitrogen treatment then.
(2) temperature is dropped between 450 ℃ and 600 ℃, the thick low temperature GaN nucleating layer 2 of growth 15 to 35 nm, during this growth course, growth pressure is between 400 Torr to 600Torr, and V/III mol ratio is between 500 to 3000.
(3) behind low temperature buffer layer 2 growth endings, low temperature buffer layer 2 is carried out annealing in process in position, annealing temperature between 1000-1200 ℃, reasonable be temperature between 1050-1150 ℃, the time is between 5 minutes to 10 minutes.
(4) after the annealing, between 1100 ℃, growth thickness is the u-GaN layer 3 of 0.8 μ m to 5 μ m with adjustment to 1000 ℃, and during this growth course, growth pressure is between 100 Torr to 500 Torr, and V/III mol ratio is between 300 to 3000.
(5) behind u-GaN 3 growth endings, growth one deck Si doped n-GaN layer 4, thickness between 1-5 μ m, growth temperature between 1000 ℃-1200 ℃, growth pressure between 100Torr to 500Torr the Si doping content 10
18Cm
-3-10
19Cm
-3Between.
(6) behind n-GaN layer 4 growth ending, the In in 2 cycles that begin to grow
xGa
1-xN/GaN (0＜x＜0.5) MQW is formed.The thickness of trap is between 2nm to 3nm, and the thickness at base is between 15 to 25nm, and wherein the growth temperature at trap and base is identical, between 820 ℃ to 920 ℃; Growth pressure is identical, between 100Torr to 500Torr; V/III mol ratio is identical, between 300 to 5000.
(7) behind high temperature multi-quantum pit structure MQW 501 growth endings, the In in 10 cycles that begin to grow
yGa
1-yThe shallow SQW of N/GaN (0＜y＜0.5) is formed.The thickness of trap is between 1nm to 3nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.
(8) behind shallow quantum well structure MQW 502 growth endings of low temperature, the In in 8 cycles that begin to grow
yGa
1-yThe luminous MQW of N/GaN (0＜y＜0.5).The thickness of trap is between 2nm to 5nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of useful is this trap is thick than the thickness of the trap of step (7) growth.The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.
(9) behind chemiluminescence multi-quantum pit structure MQW 503 growth endings, temperature is risen between 800 ℃ to 1080 ℃, between the growth pressure 50Torr to 200Torr, between V/III mol ratio 1000 to 20000, the p-Al between the growth thickness 10nm to 200nm
zGa
1-zN (0.1＜z＜0.5) electronic barrier layer 6.This layer energy gap can be controlled between 4eV and the 5.5eV greater than the energy gap of last barrier.
(10) p-Al
zGa
1-zBehind N (0.1＜z＜0.5) electronic barrier layer 6 growth endings, the p type gallium nitride layer 7 of a layer thickness between 0.1 μ m to 0.8 μ m of growing, its growth temperature is between 850 ℃ to 1080 ℃, and growth air pressure is between 100 Torr-300 Torr.
(11) after p type gallium nitride layer 7 finishes; The P type contact layer 8 of a layer thickness of growing at 0.05-0.3 μ m; Its growth temperature is between 850 ℃ to 1050 ℃, and between the growth pressure 100Torr to 300Torr, V/III mol ratio is between 1000 to 20000.
Epitaxial growth is reduced to the temperature of reaction chamber between 650 ℃ to 850 ℃ after finishing, and annealing in process is 5 to 15 minutes in the pure nitrogen gas atmosphere, reduces to room temperature then, finishes epitaxial growth.
Epitaxial wafer to growth cleans then, semiconducter process such as deposition, photoetching and etching process the led chip that single size is 10 * 16 mil.Through the led chip test, measuring current 20mA, single little chip optical output power is 24.5 mW, operating voltage 3.05V, and adopt common multi-quantum pit structure growth pattern, and the operating voltage of single little chip of identical chips processing procedure is 2.8V, brightness has only 18mW.
(1) at first backing material 1 was annealed in hydrogen atmosphere 8 minutes, the clean substrate surface, temperature is controlled between 1050 ℃ and 1180 ℃, carries out nitrogen treatment then.
(2) temperature is dropped between 450 ℃ and 600 ℃, the thick low temperature GaN nucleating layer 2 of growth 15 to 35 nm, during this growth course, growth pressure is between 400 Torr to 600Torr, and V/III mol ratio is between 500 to 3000.
(3) behind low temperature buffer layer 2 growth endings, low temperature buffer layer 2 is carried out annealing in process in position, annealing temperature between 1000-1200 ℃, reasonable be temperature between 1050-1150 ℃, the time is between 5 minutes to 10 minutes.
(4) after the annealing, between 1100 ℃, growth thickness is the u-GaN layer 3 of 0.8 μ m to 5 μ m with adjustment to 1000 ℃, and during this growth course, growth pressure is between 100 Torr to 500 Torr, and V/III mol ratio is between 300 to 3000.
(5) behind u-GaN 3 growth endings, growth one deck Si doped n-GaN layer 4, thickness between 1-5 μ m, growth temperature between 1000 ℃-1200 ℃, growth pressure between 100Torr to 500Torr the Si doping content 10
18Cm
-3-10
19Cm
-3Between.
(6) behind n-GaN layer 4 growth ending, the In in 8 cycles that begin to grow
xGa
1-xN/GaN (0＜x＜0.5) MQW is formed.The thickness of trap is between 2nm to 3nm, and the thickness at base is between 15 to 25nm, and wherein the growth temperature at trap and base is identical, between 820 ℃ to 920 ℃; Growth pressure is identical, between 100Torr to 500Torr; V/III mol ratio is identical, between 300 to 5000.
(7) behind high temperature multi-quantum pit structure MQW 501 growth endings, the In in 15 cycles that begin to grow
yGa
1-yThe shallow SQW of N/GaN (0＜y＜0.5) is formed.The thickness of trap is between 1nm to 3nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.
(8) behind shallow quantum well structure MQW 502 growth endings of low temperature, the In in 10 cycles that begin to grow
yGa
1-yThe luminous MQW of N/GaN (0＜y＜0.5).The thickness of trap is between 2nm to 5nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of useful is this trap is thick than the thickness of the trap of step (7) growth.The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000.
(9) behind chemiluminescence multi-quantum pit structure MQW 503 growth endings, temperature is risen between 800 ℃ to 1080 ℃, between the growth pressure 50Torr to 200Torr, between V/III mol ratio 1000 to 20000, the p-Al between the growth thickness 10nm to 200nm
zGa
1-zN (0.1＜z＜0.5) electronic barrier layer 6.This layer energy gap can be controlled between 4eV and the 5.5eV greater than the energy gap of last barrier.
(10) p-Al
zGa
1-zBehind N (0.1＜z＜0.5) electronic barrier layer 6 growth endings, the p type gallium nitride layer 7 of a layer thickness between 0.1 μ m to 0.8 μ m of growing, its growth temperature is between 850 ℃ to 1080 ℃, and growth air pressure is between 100 Torr-300 Torr.
(11) after p type gallium nitride layer 7 finishes; The P type contact layer 8 of a layer thickness of growing at 0.05-0.3 μ m; Its growth temperature is between 850 ℃ to 1050 ℃, and between the growth pressure 100Torr to 300Torr, V/III mol ratio is between 1000 to 20000.
Epitaxial growth is reduced to the temperature of reaction chamber between 650 ℃ to 850 ℃ after finishing, and annealing in process is 5 to 15 minutes in the pure nitrogen gas atmosphere, reduces to room temperature then, finishes epitaxial growth.
Epitaxial wafer to growth cleans then, semiconducter process such as deposition, photoetching and etching process the led chip that single size is 10 * 16 mil.Through the led chip test, measuring current 20mA, single little chip optical output power is 24.5 mW, operating voltage 3.05V, and adopt common multi-quantum pit structure growth pattern, and the operating voltage of single little chip of identical chips processing procedure is 2.8V, brightness has only 18mW.
Although described specific embodiment of the present invention; But those skilled in the art should recognize; Under the prerequisite that does not deviate from principle that the present invention design limited and spirit; Can do change to the periodicity in the above-mentioned composite quantum well structure, comprise different quantum well structure periodicities are done and arrange and combination, can not influence the effect of being set forth in of the present invention.
Claims (8)
1. composite quantum well structure that improves the charge carrier combined efficiency; The structure of this LED epitaxial slice is followed successively by from bottom to top; Substrate layer, gallium nitride low temperature buffer layer, unadulterated high-temperature ammonolysis gallium layer, Si doped n type gallium nitride layer, multi-quantum pit structure MQW, p type aluminum gallium nitride electronic barrier layer, p type gallium nitride layer, p type gallium nitride contact layer is characterized in that: multi-quantum pit structure MQW comprises high temperature multi-quantum pit structure, the shallow quantum well structure of low temperature, chemiluminescence multi-quantum pit structure from the bottom up successively.
2. according to the composite quantum well structure of the said raising charge carrier of claim 1 combined efficiency, it is characterized in that: the shallow quantum well structure of high temperature comprises the In in 2 to 8 cycles
xGa
1-xN/GaN0＜x＜0.5 MQW, the thickness of trap are between 2nm to 3nm, and the thickness at base is between 15 to 25nm, and wherein the growth temperature at trap and base is identical, between 820 ℃ to 920 ℃; Growth pressure is identical, between 100Torr to 500Torr.
3. according to the composite quantum well structure of the said raising charge carrier of claim 1 combined efficiency, it is characterized in that: the shallow quantum well structure MQW of low temperature comprises the In in 2 to 15 cycles
yGa
1-yN/GaN 0＜y＜0.5 MQW; The thickness of trap is between 1nm to 3nm, and growth temperature is between 720 ℃ to 820 ℃; The thickness of building between 10 to 25nm, growth temperature between 820 ℃ to 920 ℃, the In in 2 to 15 cycles
yGa
1-yThe thickness of N 0＜y＜0.5 can be the same, also thickening or attenuation or thickness replace gradually gradually.
4. according to the composite quantum well structure of the said raising charge carrier of claim 1 combined efficiency, it is characterized in that: chemiluminescence multi-quantum pit structure MQW comprises the In in 1 to 10 cycle
yGa
1-yN/GaN 0＜y＜0.5 MQW is formed; The thickness of trap is between 2nm to 5nm, and growth temperature is between 720 ℃ to 820 ℃; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃; The In in 1 to 10 cycle
yGa
1-yThe thickness of N 0＜y＜0.5 can be the same, also thickening or attenuation or thickness replace gradually gradually.
5. according to the composite quantum well structure of claim 1 or 2 said raising charge carrier combined efficiencies, it is characterized in that: the trap In in the shallow quantum well structure of high temperature
xGa
1-xThe trap In of the shallow quantum well structure of growth temperature lower temperature of N layer
yGa
1-yIt is high that the growth temperature of N is wanted.
6. according to the composite quantum well structure of the said raising charge carrier of claim 1 combined efficiency, it is characterized in that: the trap In in the shallow quantum well structure of high temperature
xGa
1-xN layer x scope is 0＜x＜0.5, the trap In of the shallow quantum well structure of low temperature
yGa
1-yThe y scope is 0＜y＜0.5 among the N, and x＜y is arranged.
7. according to the preparation method of the composite quantum well structure of claim 1 or 4 said raising charge carrier combined efficiencies, it is characterized in that: in the chemiluminescence quantum well structure in the shallow quantum well structure of thickness lower temperature of each trap the thickness of any trap thick.
8. preparation method who improves the composite quantum well structure of charge carrier combined efficiency, its step:
⑴ at first annealed backing material 1-10 minute in hydrogen atmosphere, the clean substrate surface, and temperature is controlled between 1050 ℃ and 1180 ℃, carries out nitrogen treatment then;
⑵ drop to temperature between 450 ℃ and 600 ℃, the thick low temperature GaN nucleating layer of growth 15 to 35 nm, and during this growth course, growth pressure is between 400 Torr to 600Torr, and V/III mol ratio is between 500 to 3000;
⑶ behind the low temperature buffer layer growth ending, low temperature buffer layer is carried out annealing in process in position, annealing temperature is between 1000-1200 ℃, and the time is between 5 minutes to 10 minutes;
⑷ after the annealing, between 1200 ℃, growth thickness is the u-GaN layer of 0.8 μ m to 5 μ m with adjustment to 1000 ℃, and during this growth course, growth pressure is between 100 Torr to 760 Torr, and V/III mol ratio is between 300 to 3000;
⑸ behind u-GaN 3 growth endings, growth one deck Si doped n-GaN layer, thickness is between 1-5 μ m; Growth temperature is between 1000 ℃ to 1200 ℃; Growth pressure is between 50 Torr to 760 Torr, and V/III mol ratio is between 300 to 3000, and the Si doping content is 10
17Cm
-3-10
19Cm
-3Between;
⑹ after n-GaN layer growth finishes, the high temperature multi-quantum pit structure MQW 501 that begins to grow, high temperature multi-quantum pit structure MQW 501 is by the In in 2 to 8 cycles
xGa
1-xN/GaN 0＜x＜0.5 MQW is formed; The thickness of trap is between 2nm to 3nm, and the thickness at base is between 15 to 25nm, and wherein the growth temperature at trap and base is identical, between 820 ℃ to 920 ℃; Growth pressure is identical, between 100Torr to 500Torr; V/III mol ratio is identical, between 300 to 5000;
⑺ behind high temperature multi-quantum pit structure MQW 501 growth endings, the shallow quantum well structure MQW 502 of beginning growing low temperature, the shallow quantum well structure MQW of low temperature comprises the In in 2 to 15 cycles
yGa
1-yN/GaN 0＜y＜0.5 MQW; The thickness of trap is between 1nm to 3nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000;
⑻ behind the shallow quantum well structure MQW of the low temperature growth ending, beginning growing low temperature luminescent quantum well structure MQW, chemiluminescence multi-quantum pit structure MQW comprises the In in 1 to 10 cycle
yGa
1-yN/GaN 0＜y＜0.5 MQW is formed; The thickness of trap is between 2nm to 5nm, and growth temperature is between 720 ℃ to 820 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000; The thickness of building is between 10 to 25nm, and growth temperature is between 820 ℃ to 920 ℃, and growth pressure is between 100Torr to 500Torr, and V/III mol ratio is between 300 to 5000;
⑼ behind the chemiluminescence multi-quantum pit structure MQW growth ending, temperature is risen between 800 ℃ to 1080 ℃, between the growth pressure 50Torr to 200Torr, between V/III mol ratio 1000 to 20000, the p-Al between the growth thickness 10nm to 200nm
zGa
1-zN 0.1＜z＜0.5 electronic barrier layer; This layer energy gap can be controlled between 4eV and the 5.5eV greater than the energy gap of last barrier;
⑽ p-Al
zGa
1-zBehind N 0.1＜z＜0.5 electronic barrier layer growth ending, the p type gallium nitride layer of a layer thickness between 0.1 μ m to 0.8 μ m of growing, its growth temperature is between 850 ℃ to 1080 ℃, and growth air pressure is between 100 Torr-300 Torr;
⑾ after p type gallium nitride layer finished, the layer thickness of growing was at the P type contact layer of 0.05-0.3 μ m, and its growth temperature is between 850 ℃ to 1050 ℃, and between the growth pressure 100Torr to 300Torr, V/III mol ratio is between 1000 to 20000;
Epitaxial growth is reduced to the temperature of reaction chamber between 650 to 850 ℃ after finishing, and annealing in process is 5 to 15 minutes in the pure nitrogen gas atmosphere, reduces to room temperature then, finishes epitaxial growth; Epitaxial wafer to growth cleans then, semiconducter process such as deposition, photoetching and etching process single small size chip.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728472A (en) * | 2009-12-02 | 2010-06-09 | 中国科学院半导体研究所 | Multilayer LED chip structure and preparation method thereof |
| CN102122687A (en) * | 2011-01-14 | 2011-07-13 | 映瑞光电科技(上海)有限公司 | Multi-quantum well structure, manufacturing method thereof and light emitting diode |
| US20110187294A1 (en) * | 2010-02-03 | 2011-08-04 | Michael John Bergmann | Group iii nitride based light emitting diode structures with multiple quantum well structures having varying well thicknesses |
| US20110253974A1 (en) * | 2008-11-20 | 2011-10-20 | Mitsubishi Chemical Corporation | Nitride semiconductor |
-
2011
- 2011-10-27 CN CN201110330659XA patent/CN102368525A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110253974A1 (en) * | 2008-11-20 | 2011-10-20 | Mitsubishi Chemical Corporation | Nitride semiconductor |
| CN101728472A (en) * | 2009-12-02 | 2010-06-09 | 中国科学院半导体研究所 | Multilayer LED chip structure and preparation method thereof |
| US20110187294A1 (en) * | 2010-02-03 | 2011-08-04 | Michael John Bergmann | Group iii nitride based light emitting diode structures with multiple quantum well structures having varying well thicknesses |
| CN102122687A (en) * | 2011-01-14 | 2011-07-13 | 映瑞光电科技(上海)有限公司 | Multi-quantum well structure, manufacturing method thereof and light emitting diode |
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