CN102339869A - Semiconductor device with MIM capacitor and method for manufacturing the same - Google Patents

Semiconductor device with MIM capacitor and method for manufacturing the same Download PDF

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Publication number
CN102339869A
CN102339869A CN2011101939494A CN201110193949A CN102339869A CN 102339869 A CN102339869 A CN 102339869A CN 2011101939494 A CN2011101939494 A CN 2011101939494A CN 201110193949 A CN201110193949 A CN 201110193949A CN 102339869 A CN102339869 A CN 102339869A
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layer
separator
top electrode
hard mask
dielectric
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CN102339869B (en
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赵振衍
姜永守
具尚根
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Aisi Kaifang Semiconductor Co ltd
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MagnaChip Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/10—Metal-oxide dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1272—Semiconductive ceramic capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a lower electrode formed on a substrate, a dielectric layer including an etched dielectric region and an as-grown dielectric region formed on the lower electrode, an upper electrode formed on the as-grown dielectric region, a hardmask formed on the upper electrode, a spacer formed at a side surface of the hardmask and the upper electrode and over a surface of the etched dielectric region, and a buffer insulation layer formed on the hardmask and the spacer.

Description

Semiconductor device and manufacturing approach thereof with MIM capacitor
Technical field
Following description relates to a kind of semiconductor device and manufacturing approach thereof, more particularly, relates to a kind of metal-insulator-metal type (MIM) capacitor and manufacturing approach thereof with high-k.
Background technology
Usually, semiconductor device need need have high storage capacity in function aspects simultaneously in high speed operation.
For this purpose, develop the technology of making semiconductor device and improved integrated degree, response speed and reliability.In order to improve the charge characteristic of semiconductor device, the direct capacitance value that is included in the element such as capacitor in the semiconductor device should be high.
Yet in recent years, along with semiconductor device becomes highly integrated, unit cell area constantly reduces.Therefore, the unit static capacity of semiconductor device also reduces, and makes to be difficult to guarantee the required static capacity of device operation.
Usually, increase the electrostatic capacitance of capacitor through the thickness that increases area, improves the relative dielectric constant of the dielectric between the electrode and reduce dielectric to electrode.Therefore, the structure of capacitor is reduced the thickness of dielectric simultaneously by variation, to obtain suitable electrostatic capacitance.
On the other hand, carried out to use and have high dielectric constant materials and replace employed up to now silicon nitride dielectric layer to obtain the research of suitable static capacity.Have high dielectric constant materials and comprise hafnium oxide, aluminium oxide and tantalum oxide.
Yet, when (height-when k) material is used as the insulating barrier of MIM capacitor, its subsequent technique will be affected owing to remaining insulating barrier after the top electrode of etching MIM capacitor with high-k.
In addition since inadequate photoresist (PR) surplus, the metal-containing polymer that produces by remaining high-k insulating layer and in follow-up via etch process the remnants of through hole interior metal polymer, cause the profile deterioration of metal line.Because such problem, through hole resistance increases, thereby has reduced the reliability of capacitor.
In addition, cross etch target and remove remaining insulating barrier, the breakdown voltage characteristics deterioration then takes place if increase follow-up through hole.
Summary of the invention
Total aspect relates to a kind of metal-insulator-metal type (MIM) capacitor and a kind of method that is constructed to make MIM capacitor; In this MIM capacitor; Reliability improves; Influence to subsequent technique is minimized, and through MIM capacitor and external environment condition isolation have been prevented to cross the puncture voltage deterioration that etch target causes by through hole.
To achieve these goals, a kind of MIM capacitor according to the embodiment of the invention can comprise: bottom electrode and top electrode are formed on the substrate; Dielectric layer, have high-k and be formed on bottom electrode and top electrode between; First protective layer is around the side surface and the upper surface of top electrode; Second protective layer, around the side surface of dielectric layer and the side surface of first protective layer, wherein, the width of dielectric layer is greater than the width of top electrode, and first protective layer and second protective layer are processed by the etch-rate material different.
To achieve these goals, a kind of method of making MIM capacitor according to the embodiment of the invention can comprise: on substrate, form bottom electrode; On bottom electrode, form dielectric layer; On the zone of dielectric layer, form top electrode and hard mask; Form separator at the side surface of dielectric layer, the side surface of top electrode and the side surface of hard mask.
To achieve these goals, a kind of method of making MIM capacitor according to the embodiment of the invention can comprise: on substrate, form the first metal layer; Sequentially lamination dielectric layer, second metal level and hard mask insulator on the first metal layer; With the hard mask insulator and second metal layer patternization, to form hard mask and top electrode; On the whole base plate that comprises hard mask, top electrode and dielectric layer, form the separator insulator; The whole surface of etching separator insulator is to form separator at the side surface of hard mask, the side surface of top electrode and the side surface place of dielectric layer; On separator, hard mask and the first metal layer, form buffer insulation layer; With buffer insulation layer and the first metal layer patterning, to form bottom electrode.
One total aspect, a kind of semiconductor device is provided, this semiconductor device comprises: bottom electrode is formed on the substrate; Dielectric layer comprises etched dielectric regions that is formed on the bottom electrode and the dielectric regions of growing as usual; Top electrode is formed on the dielectric regions of growth as usual; Hard mask is formed on the top electrode; Separator is formed on the side surface place and the etched dielectric regions top of side surface and the top electrode of hard mask; Buffer insulation layer is formed on hard mask and the separator.
Said device also can provide: dielectric layer comprises the high k HfO of ald (ALD) 2/ Al 2O 3The membrane stack overlapping piece.
Said device also can provide: use same mask with hard mask and top electrode patterning, so that hard mask and top electrode are of similar shape.
Said device also can provide: separator is isolated the side surface of hard mask and the side surface of top electrode.
Said device also can provide: the dielectric regions of growth is separated bottom electrode and top electrode as usual.
Said device also can provide: the length of bottom electrode is greater than the length of top electrode.
Said device also can provide: bottom electrode comprises TiN/Ti, and top electrode comprises TiN.
Said device also can provide: etched dielectric regions is extended from the zone of growth as usual and is stopped about the end of separator greatly; The said end of separator is formed on a side of separator; A said side is relative with the side that the side surface with hard mask and top electrode of separator contacts, and the thickness of etched dielectric regions is less than the thickness of the dielectric regions of growing as usual.
Said device also can provide: the said end of separator is cushioned insulating barrier and etched dielectric regions limits.
Said device also can provide and be formed on the do as usual dielectric regions of growth and the dielectric regions of the bending between the etched dielectric regions.
Said device also can provide: separator is formed on crooked dielectric regions top.
Said device also can provide: etched dielectric regions is extended from the zone of bending and is stopped about the end of separator greatly; The said end of separator is formed on separator one side, and a said side is relative with the side that the side surface with hard mask and top electrode of separator contacts; Crooked dielectric regions is constructed to connect etched dielectric regions and the dielectric regions of growing as usual; The thickness of etched dielectric regions is less than the thickness of dielectric regions with the dielectric regions of bending of growth as usual.
Said device also can provide, and buffer insulation layer comprises SiON.
On the other hand, a kind of method of making semiconductor device is provided.Said method comprising the steps of: on substrate, form the first metal layer; Sequentially lamination dielectric layer, second metal level, hard mask insulator on the first metal layer; Optionally etch hard mask insulator, second metal level and dielectric layer are to form hard mask, top electrode and to have etched dielectric regions and the dielectric layer pattern of the dielectric regions of growth as usual; Formation separator insulator on the etched dielectric regions of the side surface of the upper surface of hard mask and side surface, top electrode and dielectric layer pattern; Etching separator insulator is to form separator on the etched dielectric regions of the side surface of the side surface of hard mask, top electrode and dielectric layer; On separator, hard mask and the first metal layer, form buffer insulation layer; With buffer insulation layer and the first metal layer patterning, to form bottom electrode.
Said method also can provide, and optionally the step of etch hard mask insulator, second metal level and dielectric layer comprises the part of the etched dielectric regions of etching second metal level below.
Said method also can provide, and the said part of etching is included between dielectric regions and the etched dielectric regions of as usual growth and forms crooked dielectric regions.
Said method also can provide: the dielectric regions of the lower surface contact etch of separator, and the side surface of separator contacts hard mask and top electrode, and the curved surface of separator contacts buffer insulation layer and crooked dielectric regions respectively.
Said method also can provide: the dielectric regions of the lower surface contact etch of separator, the side surface of separator contacts hard mask and top electrode.
Said method also can provide: the thickness of etched dielectric regions is less than the thickness of the dielectric regions of growing as usual.
Said method also can provide, and buffer insulation layer comprises SiON.
Total aspect can provide a kind of and keep apart and avoid the MIM capacitor of various defectives with external environment condition, thereby guarantees good leakage current characteristic.
In addition, total aspect can provide, and the SiON that is deposited on the top on the metal level cushions etch target in etching process, thereby prevents the breakdown voltage characteristics deterioration of MIM capacitor.
As a result, when using the technology of the MIM capacitor of making according to total aspect, excellent characteristic can aspect reliabilities such as puncture voltage, defect concentration, be had.
Other characteristics and aspect can be tangible from following detailed, accompanying drawing and claim.
Description of drawings
Figure 1A shows the schematic cross sectional views of the example of the semiconductor device that comprises interconnect area and MIM capacitor zone.
Figure 1B shows the schematic amplification view of example of near zone of the dielectric layer 107 of Figure 1A.
Fig. 2 A to Fig. 2 R shows the cutaway view of the example of making MIM capacitor.
Only if description is arranged in addition, otherwise at whole accompanying drawing with in describing in detail, identical drawing reference numeral will be understood that to represent components identical, characteristic and structure.For clear, explanation and convenient for the purpose of, can exaggerate the relative size and the description of these elements.
Embodiment
Provide following detailed to help the reader and obtain complete understanding method described here, equipment and/or system.Therefore, those of ordinary skills should expect various changes, modification and the equivalent of system described here, equipment and/or method.In addition, in order to improve clear and terse degree, can omit description to known function and structure.
It being understood that characteristic of the present disclosure can implement with different forms, and should not be interpreted as the example embodiment that is confined to here to be proposed.On the contrary, provide these embodiment to make that the disclosure will be thorough with completely, and will convey to those skilled in the art to four corner of the present disclosure.Accompanying drawing can not necessarily meet ratio, and in some instances, the ratio of can exaggerating is shown clearly in the characteristic of embodiment.When ground floor be known as " " on the second layer or " " substrate " on " time; Can refer to that not only ground floor is formed directly into the situation on the second layer or the substrate, but can also refer to the 3rd layer be present between the ground floor and the second layer or ground floor and substrate between situation.
Hereinafter, will describe the example of the structure of semiconductor device in detail with reference to accompanying drawing with MIM capacitor.
Figure 1A shows the schematic cross sectional views that comprises the interconnect area 200 and the example of the semiconductor device in MIM capacitor zone 300.In interconnect area 200, following interconnection layer can be by the interconnecting metal layer 103b and the cover layer 105b that interconnects down form down.Last interconnection layer can be arranged on down upperside interconnection layer, and between last interconnection layer and following interconnection layer, is provided with internallic insulating layers 131.Last interconnection layer can be formed by last interconnecting metal layer 139c and last interconnection cover layer 141c.Last interconnection layer can be electrically connected to down interconnection layer through metal closures 137c.
With reference to Figure 1A, can comprise according to MIM capacitor of the present invention: bottom electrode 105a is formed on the substrate 101; Dielectric layer 107 is formed on the bottom electrode 105a, has high-k and comprises the first area and dielectric layer ledge 107a, and dielectric layer ledge 107a is the second area outstanding from the first area; Top electrode 109a is formed on the first area of dielectric layer 107; Separator 121a is formed on the side surface place of the side surface and the top electrode 109a of dielectric layer 107.
Here, dielectric layer 107 can comprise with the stacked first area of top electrode 109a with from said first area and extending and outstanding dielectric layer ledge 107a.At this moment, the horizontal length of the dielectric layer of formation (or width) is longer than the horizontal length (or width) that is formed on the top electrode 109a on the dielectric layer 107.Can top electrode and bottom electrode be separated well through forming the dielectric layer more broader, thereby help to suppress the generation of leakage current than top electrode.If dielectric layer has identical width with top electrode, then the length between top electrode and the bottom electrode is short, therefore passes through probably along the electric field generation leakage current of the side surface of upper/lower electrode.On the contrary, if the width of dielectric layer is greater than the width of top electrode as stated, then can prevent such problem.
Following structure is formed on the substrate 101.Following structure can comprise pad, plug, conductive layer pattern, dielectric layer pattern, grid structure, transistor etc.In addition, substrate 101 can comprise semiconductor substrate or monocrystalline metal oxide substrate.For example, substrate 101 can comprise silicon substrate, germanium substrate, SOI substrate, GOI substrate, alumina single crystal substrate, titanium oxide monocrystal substrate etc.
In addition, the insulation system (not shown) places between substrate 101 and the capacitor.Insulation system can have the single layer structure of being processed by oxide skin(coating).For example, can utilize boron phosphorus silicate glass (BPSG), phosphosilicate glass (PSG), undoped silicate glass (USG), spin-on glasses (SOG), flowable oxide (FOX), tetraethyl orthosilicate (TEOS), plasma to strengthen (PE)-TEOS, high-density plasma-chemical vapour deposition (CVD) (HDP-CVD) oxide etc. and form the insulation system (not shown).On the other hand, the insulation system (not shown) can have the sandwich construction that is formed on the substrate 101, and said sandwich construction comprises at least one deck oxide skin(coating), one deck nitride layer and/or one deck oxynitride layer at least at least.Here, can use silica to form oxide skin(coating), can use silicon nitride to form nitride layer, can use silicon oxynitride to form oxynitride layer.
With reference to Figure 1A, the example of the MIM capacitor 400 in the MIM capacitor zone 300 comprises bottom electrode 105a, dielectric layer 107 and top electrode 109a on metal line 103a, the metal line 103a.Metal line 103a can be by processing with the material identical materials of following interconnecting metal layer 103b and forming by the manufacturing step identical with the manufacturing step of following interconnecting metal layer 103b.Bottom electrode 105a can be by processing with the material identical materials of the cover layer 105b that interconnects down and forming by the identical manufacturing step of manufacturing step with the cover layer 105b that interconnects down.
Metal line 103a can be by aluminium (Al), copper (Cu), and perhaps the combination of Al and Cu is formed.One total aspect, metal line 103a can be made up of AlCu.Can form bottom electrode 105a through using metal, alloy or conductive metallic compound.For example, bottom electrode 105a is selected from least a by in the group of Ru, Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu or their alloy composition, perhaps can use every kind in these materials with single mode or hybrid mode.One total aspect, bottom electrode 105a can be made up of TiN (top)/Ti (end) layer.Possibly need the Ti layer to improve the adhesion between TiN and the AlCu.
Can form the electric capacity that dielectric layer 107 improves MIM capacitor 400.One total aspect, dielectric layer 107 can be by comprising silicon nitride (SiN), tantalum oxide (Ta 2O 5), hafnium oxide (HfO 2), aluminium oxide (Al 2O 3) wait at any interior insulating material and form.Another total aspect, dielectric layer 107 can be by such as HfO 2/ Al 2O 3The stacked structure of layer (vice versa) forms.Another total aspect, dielectric layer 107 can be by high k HfO 2/ Al 2O 3The repetitive structure of membrane stack overlapping piece forms.In addition, HfO 2Layer can be effectively aspect the minimizing leakage current.One total aspect, can use the high k HfO of ald (ALD) 2/ Al 2O 3The repetitive structure of membrane stack overlapping piece shows 4fF/ μ m 2With 12fF/ μ m 2Between capacitance density.
Can use metal, alloy or conductive metallic compound to form top electrode 109a.For example, top electrode 109a is selected from least a by in the group of Ru, Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu or their alloy composition, perhaps can use every kind in these materials with single mode or hybrid mode.One total aspect, top electrode 109a can be made up of the TiN layer.Bottom electrode 105a can be made up of TiN (top)/Ti (end) layer.Therefore, top electrode 109a can comprise the material material different with bottom electrode 105a.
As mentioned above, the Ti layer of bottom electrode 105a can play the effect of the adhesive layer of the adhesion between the AlCu layer that improves bottom electrode and metal line 103a.Yet, because dielectric layer 107 is directly below bottom electrode 109a, so top electrode 109a need not use the Ti layer under the TiN layer.Do not need the Ti adhesive layer between top electrode 109a and the dielectric layer 107.
In addition, can on the upper surface of top electrode 109a, form hard mask 111a, with the sidewall spacers of the height of the abundance of the side that obtains to be formed on top electrode 109a.Only the height of top electrode 109a maybe be too little and can not limits the sidewall spacers of the side of top electrode 109a.Therefore, can need hard mask 111a to make sidewall spacers be formed on the side of hard mask 111a and top electrode 109a.
In addition, hard mask 111a has reduced the generation of polymer in the etching process of TiN layer of top electrode 109a.If replace hard mask to be used as mask, then producing a large amount of polymer on the sidewall of top electrode 109a and on the upper surface of crossing etching part of dielectric layer 107 with the photoresist pattern.Because the polymer that produces comprises the metallicity component of utmost point 109a transmission from power on, so the polymer that produces can show as electrode.The etching part excessively of dielectric layer 107 is thinner than the part (as-grown portion) of the growth as usual of dielectric layer 107.Therefore, the part generation leakage current of 107 attenuation from the metallicity polymer to dielectric layer, thus make the reliability deterioration of MIM capacitor.Yet, use the etch process of hard mask 111a can stop on the sidewall of top electrode 109a and produce polymer, and prevent the problems referred to above.
Can form hard mask 111a by the single layer structure of processing by oxide skin(coating).For example, hard mask 111a can be by forming such as silica based materials such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxides, perhaps by forming such as the silicon nitride-based material of SiN and SiON.Hard mask 111a can have the sandwich construction that comprises at least one oxide skin(coating), at least one nitride layer and/or at least one oxynitride layer.One total aspect, can use silica to form oxide skin(coating), can use silicon nitride to form nitride layer, can use silicon oxynitride to form oxynitride layer.The thickness of the hard mask 111a in about
Figure BSA00000536396900071
to
Figure BSA00000536396900072
range.
In addition, can form separator 121a by the single layer structure of processing by oxide skin(coating).For example, separator 121a can be by forming such as silica based materials such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxides, perhaps by forming such as the silicon nitride-based material of SiN and SiON.The material of separator 121a can be silica rather than silicon nitride, and this is because the silicon nitride ratio silicon oxide can cause the edge capacitance of not expecting more easily between top electrode 109a and bottom electrode 105a.
Buffer insulation layer 123 can be present in interconnect area 200 and the MIM capacitor zone 300.Buffer insulation layer 123 can cover the surface of exposure of side surface, the bottom electrode 105a of upper surface, the separator 121a of hard mask 111a.Because being separated part 121a, top electrode 109a centers on, so buffer insulation layer 123 does not contact with top electrode 109a with hard mask 111a.Buffer insulation layer 123 can be made up of the silicon oxide layer that contains nitrogen-atoms (that is silicon oxynitride (SiON)).Therefore, in follow-up metal pattern process, buffer insulation layer 123 can be carried out the effect of the anti-reflecting layer of the surplus that is constructed to increase photoetching process.
In addition, buffer insulation layer 123 can be carried out the effect of the resilient coating that is constructed to the through hole etch target is cushioned simultaneously.In addition, also can be with buffer insulation layer 123 as the hard mask that is constructed to etching metal wiring layer 103 and the first metal layer 105 (shown in Fig. 2 A to Fig. 2 E).For etching metal wiring layer 103 and the first metal layer 105, photoresist (PR) is used as mask.Yet the PR mask is not enough to etching metal wiring layer 103 and the first metal layer 105.One total aspect, the thickness of buffer insulation layer 123 can be at
Figure BSA00000536396900081
to the scope of
Figure BSA00000536396900082
.On the other hand, can use organic bottom antireflective coating (BARC) to replace inorganic SiON to form buffer insulation layer 123.
In addition, can above buffer insulation layer 123, form internallic insulating layers 131.Can above internallic insulating layers 131, form the first pad 139a and the second pad 139b and the first anti-reflecting layer 141a and the second anti-reflecting layer 141b.The first pad 139a can be electrically connected to bottom electrode 105a through the first plug 137a, and the second pad 139b can be electrically connected to top electrode 109a through the second plug 137b.The first plug 137a and the second plug 137b can comprise tungsten (W), copper etc.One total aspect, the first plug 137a and the second plug 137b can comprise tungsten (W).In addition, can between substrate 101 and metal line 103a, insert before the metal dielectric layer (not shown).
Figure 1B shows the schematic amplification view of example of near zone of the dielectric layer 107 of Figure 1A.Can dielectric layer 107 be divided into three zones.The first area can be etched dielectric regions 107a, and this regional etched thickness is less than the growth thickness as usual of the dielectric regions 107b of growth as usual.Etched dielectric regions 107a can extend from the dielectric regions 107b of growth as usual.Crooked (or stair-stepping) dielectric regions 107c can be at the adjacent part between the dielectric regions 107b of etched dielectric regions 107a and growth as usual.
The thickness of the dielectric regions 107b that the thickness of etched dielectric regions 107a can be grown less than doing as usual, thus electric capacity increased.That is to say, because the thickness of etched dielectric regions 107a reduces, so electric capacity increases.Therefore, can obtain this effect owing to the existence of etched dielectric regions 107a.
Because top electrode 109a and hard mask 111a differ from one another, so can realize crooked dielectric regions 107c.Can in MIM capacitor 400, form separator 121a and reduce the leakage current between top electrode 109a and the bottom electrode 105a.Separator 121a can cover the surface of exposure of side surface and the dielectric layer 107 of hard mask 111a, top electrode 109a.One total aspect, the surface of surface that the surface of the exposure of dielectric layer 107 can comprise etched dielectric regions 107a and crooked dielectric regions 107c.
The horizontal length of bottom electrode 105a (or width) can be greater than the horizontal length (or width) of top electrode 109a.Through forming dielectric layer 107, top electrode 109a can open with bottom electrode 105a branch well, thereby helps to suppress the generation of leakage current.If bottom electrode 105a has identical width with top electrode 109a, pass through probably along the electric field generation leakage current of their side surface.On the contrary, as stated, if the width of bottom electrode 105a, prevents then that such problem from being possible greater than the width of top electrode 109a.
As stated, use separator 121a and hard mask 111a, MIM capacitor 400 can separate with external environment condition and avoid various defectives, thereby obtains good leakage current characteristic.
To the method according to the manufacturing MIM capacitor of total aspect be described with reference to Fig. 2 A to Fig. 2 R.
Fig. 2 A to Fig. 2 R shows the cutaway view of the example of making MIM capacitor.
Although not shown in figures, at first can be under forming on the substrate 101 the structure (not shown), and preceding metal dielectric layer (not shown) is deposited on down on the structure.Although not shown in figures, structure can comprise pad, conductive pattern, wiring, grid structure, transistor etc. down.
Then, shown in Fig. 2 A, can be on preceding metal dielectric layer (not shown) sequentially plated metal wiring layer 103 and the first metal layer 105 that is used for bottom electrode.Rs that can be required according to Wiring technique (resistance) value changes the thickness of metal wiring layer 103.Metal wiring layer 103 can comprise aluminium (Al), copper etc.One total aspect, metal wiring layer 103 comprises AlCu.
The first metal layer 105 can comprise metal, alloy or conductive metallic compound.For example, the first metal layer 105 can be selected from the group be made up of Ti, TaN, WN, TiN, TiAlN or any their combination at least a.One total aspect, the first metal layer 105 comprises TiN (top)/Ti (end) layer.
Then, can be on the first metal layer 105 dielectric layer 107.Can use ald (ALD) technology, sputtering technology, pulse laser deposition process, electron beam deposition technology or chemical vapor deposition method to form dielectric layer 107.One total aspect, use ALD to form high k HfO 2/ Al 2O 3The repetitive structure of membrane stack overlapping piece.
Stay in the via regions on the first metal layer 105 if having the insulating material of high dielectric constant value, then in the etch process that forms through hole, can go wrong, this also will be explained hereinafter.Yet, for silicon nitride (SiN), just can not go wrong, this is because when the formation through hole, even when it continues to stay on the side of the first metal layer 105, silicon nitride also is easy to be etched.
The thickness that can reduce SiN increases the electric capacity of capacitor.If the thickness of SiN reduces, then can cause leakage current.Therefore, if thickness is identical, then preferably use material with high dielectric constant value.On the other hand, after forming dielectric layer 107, can carry out Technology for Heating Processing, ozone treatment technology, oxygen treatment process, plasma annealing technology etc. extraly, to improve the electrology characteristic of dielectric layer 107 to dielectric layer 107.
Dielectric layer 107 can comprise first area and second area.The first area can be etched zone, and the part of thickness is etched in subsequent technique in this zone.Second area can be the zone of growing as usual, and the dielectric that this zone is used as MIM capacitor is non-etching area simultaneously.
Next, can on dielectric layer 107, deposit second metal level 109 that will be used as top electrode.Can use metal, alloy or conductive metallic compound to form second metal level 109.For example, second metal level 109 can be selected from the group be made up of W, Al, Cu, Ti, TaN, WN, TiN, TiAlN or any their combination at least a.One total aspect, second metal level 109 comprises TiN.
Then, can be on second metal level 109 deposited hard mask insulator 111, with the sidewall spacers of the sufficient height that obtains to be formed on the top electrode side.Maybe be too little with the height of the top electrode that is formed and can not limit the sidewall spacers of top electrode side.Therefore, need hard mask insulator 111 to make sidewall spacers be formed on hard mask and with the side of the top electrode that is formed.Can be roughly
Figure BSA00000536396900101
to
Figure BSA00000536396900102
deposited to a thickness within the range of depositing a hard mask insulator 111.
Can utilize chemical vapor deposition (CVD) technology, low-pressure chemical vapor deposition (LPCVD) technology, plasma enhanced chemical vapor deposition (PECVD) technology or high density plasma CVD (HDP-CVD) technology to form hard mask insulator 111.Hard mask insulator 111 can have the single layer structure of being processed by oxide skin(coating).For example, hard mask insulator 111 can use such as silica based materials such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxides, perhaps can use the silicon nitride-based material such as SiN and SiON.In addition, hard mask insulator 111 can have and comprises at least one deck oxide skin(coating), one deck nitride layer and/or the sandwich construction of one deck oxynitride layer at least at least.Here, can use silica to form oxide skin(coating), can use silicon nitride to form nitride layer, can use silicon oxynitride to form oxynitride layer.
Next, shown in Fig. 2 B and Fig. 2 C, can on hard mask insulator 111, apply photoresist (PR) layer 113 and then photoresist layer 113 patterning that apply formed the first photoresist layer pattern 113a as a PR mask 113a.
Then, shown in Fig. 2 D, can use same mask to come the etch hard mask insulator 111 and second metal level 109, obtain hard mask 111a and top electrode 109a, can make them be of similar shape hard mask 111a and top electrode 109a patterning.Can stop etching at dielectric layer 107, the first metal layer 105 is not exposed to the outside.If the first metal layer 105 is exposed when the etch hard mask insulator layer 111 and second metal level 109, then produces metal-containing polymer, thereby cause leakage current.
Owing to can carry out etching and come etching second metal level 109; So can carry out etching to the part of etched dielectric regions 107a, make the thickness of the dielectric layer 107 among the etched dielectric regions 107a can form that the thickness according to the dielectric layer 107 among the dielectric regions 107b of normal growth is little at least.The thickness of remaining dielectric regions 107a after being etched of dielectric layer 107 for
Figure BSA00000536396900111
to
Figure BSA00000536396900112
at this, the thickness of remaining dielectric layer 107 can be at approximately
Figure BSA00000536396900113
to the scope of among the etched dielectric regions 107a.In addition, the thickness that can control dielectric layer 107 remaining among the etched dielectric regions 107a is to improve process allowance.When using the first photoresist layer pattern 113a to carry out etch process, can in etch hard mask insulator 111 processes, use CF as mask layer 4/ CH xF y/ O 2/ N 2Gases such as/Ar can use Cl in second metal level, 109 processes that etching is used for the top electrode of MIM capacitor 2/ BCl 3, and with N 2, Ar etc. is as the interpolation gas of etching outline control.After etching, can peel off the first photoresist layer pattern 113a through cineration technics.
Next, shown in Fig. 2 E, can separator insulator 121 be deposited as dielectric film, make it cover the surface of exposure of side surface and the dielectric layer 107 of upper surface and the side surface of hard mask 111a, top electrode 109a.Spacer insulator 121 may have about
Figure BSA00000536396900115
to
Figure BSA00000536396900116
deposited to a thickness within the range.Separator insulator 121 can use the deposition materials identical materials with hard mask insulator 111, and this gives between separator insulator 121 and the hard mask insulator 111 and leaves over down adhesion problems.
Can utilize chemical vapor deposition (CVD) technology, low-pressure chemical vapor deposition (LPCVD) technology, plasma enhanced chemical vapor deposition (PECVD) technology or high density plasma CVD (HDP-CVD) technology to form separator insulator 121.Separator insulator 121 can have the single layer structure of being processed by oxide skin(coating).For example, separator insulator 121 can use such as silica based materials such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxides, perhaps can use the silicon nitride-based material such as SiN and SiON.In addition, separator insulator 121 can have and comprises at least one deck oxide skin(coating), one deck nitride layer and/or the sandwich construction of one deck oxynitride layer at least at least.Here, can use silica to form oxide skin(coating), can use silicon nitride to form nitride layer, can use silicon oxynitride to form oxynitride layer.
Then, shown in Fig. 2 F, can the exposed portions etch-back of dielectric layer 107 and separator insulator 121 be exposed up to the first metal layer 105.In addition, can be on the surface of the surface of hard mask 111a and the side surface of top electrode 109a, etched dielectric regions 107a and crooked dielectric regions 107c formation separator 121a.Used etch process, can dielectric layer that stay via regions 107 be removed fully.If etched dielectric regions 107a is not removed fully, then the effect of etch stop is played by the remainder branch of etched dielectric regions 107a in being used to form the subsequent etch technology of through hole, thereby hinders the formation of through hole.
As a result, through forming the technology of separator 121a, can the horizontal length (or width) of dielectric layer 107 be formed greater than the horizontal length (or width) that is formed on the top electrode 109a on the dielectric layer 107.Through forming the dielectric layer 107 wideer, can well top electrode 109a be opened with bottom electrode 105a branch, thereby help to suppress the generation of leakage current than top electrode 109a.
On the other hand, hard mask 111a can loss a little in the technology of etching separator insulator 121.This possibly be identical the causing of material owing to material with the separator insulator 121 of hard mask 111a.The exposed upper branch of the first metal layer 105 is loss a little in the technology of etching separator insulator 121.This possibly be owing to the etching of crossing to the first metal layer 105 causes to guarantee the side surface that only keeps separator insulator 121.
When accomplishing the technology that forms separator 121a in this manner, MIM capacitor 400 can fully be kept apart with external environment condition.As a result, but the effect of separator 121a execute protection top electrode 109a and the side surface of hard mask 111a.Etched dielectric regions 107a can be present under the separator 121a, and the first metal layer 105 that is used for bottom electrode 105a can be present under the etched dielectric regions 107a.One total aspect, the thickness that is present in the etched dielectric regions 107a under the separator 121a can be less than the thickness of the dielectric regions 107b of growth as usual.Top electrode 109a, crooked dielectric regions 107c can contact with the side surface of separator 121a with hard mask 111a.
Then; Shown in Fig. 2 G; Can the buffer insulation layer 123 that have such as the silicon nitride-based material of SiON be deposited as anti-reflecting layer, make buffer insulation layer 123 cover the surface of exposure of side surface and the first metal layer 105 of the upper surface of hard mask 111a, the side surface of separator 121a, etched dielectric regions 107a.The etch-rate of buffer insulation layer 123 is different with the etch-rate of material in being used in separator insulator 121 or hard mask 111a.When forming through hole, buffer insulation layer 123 can induce etching for the first time to stop on the buffering insulator.
One total aspect, can form buffer insulation layer 123 through using SiON.SiON can carry out the effect of anti-reflecting layer, in follow-up metal pattern process, to increase the surplus of photoetching process.In addition, buffer insulation layer 123 can be carried out the effect of the resilient coating that is used for the through hole etch target is cushioned simultaneously.One total aspect, can the thickness of buffer insulation layer 123 be deposited on approximately
Figure BSA00000536396900131
to the scope of
Figure BSA00000536396900132
.
Owing to can on the whole surface of substrate 101, deposit buffer insulation layer 123, so buffer insulation layer 123 can directly contact with the first metal layer 105 of the bottom electrode 105a that is used to be exposed to the outside.Yet, center on hard mask 111a because the side surface of top electrode 109a and upper surface can be separated part 121a respectively, so buffer insulation layer 123 does not contact with top electrode 109a.The dielectric regions of the lower surface contact etch of separator.The side surface of separator contacts hard mask and top electrode.The curved surface of separator contacts buffer insulation layer and crooked dielectric regions respectively.
In addition, can use SiH 4/ N 2O gas deposits the SiON that is used for buffer insulation layer 123 in 350 ℃ to 420 ℃ temperature range.Consider the surplus of photoetching process, can the value of n (refractive index) be changed into 1.88-22, can the value of k (extinction coefficient) be changed into 0.30-0.45.Can be through control SiH 4/ N 2The gas ratio of O changes n value and k value.N value and k value can be along with SiH 4/ N 2The gas ratio of O reduces and increases, and increases N thereby play 2The effect of the share of O.
In addition, if reflectivity is high, then contiguous photoresist (PR) layer can be difficult to control the difficulty that (DI) critical dimension (CD) is checked in photodevelopment thereby cause owing to diffuse reflection is dissipated.Can replace SiON to be used for buffer insulation layer 123 organic BARC.
In addition; When through hole is crossed etch target less than about ; Can deposit SiON by low relatively thickness in about
Figure BSA00000536396900134
to
Figure BSA00000536396900135
scope, with the surplus of guaranteeing photoetching process and with SiON with the anti-reflecting layer that acts on fine patterning.
Yet; When through hole is crossed etch target greater than about
Figure BSA00000536396900136
, can deposit SiON by the thickness in about
Figure BSA00000536396900137
to
Figure BSA00000536396900138
scope.In addition, when etching when forming through hole, through using such as C 4F 8, C 5F 8, C 4F 6Gas Deng the chemical characteristic with high C/F ratio improves the etching selectivity of oxide layer to SiON.SiON carries out the function of the anti-reflecting layer that is used for fine patterning and carries out the effect of the resilient coating that the through hole etch target is cushioned simultaneously.
In addition, also can buffer insulation layer 123 usefulness be acted on the hard mask layer of etching metal wiring layer 103 and the first metal layer 105.Yet only the PR mask can not be enough to etching metal wiring layer 103 and the first metal layer 105.At this, the thickness of buffer insulation layer 123 can be at about
Figure BSA00000536396900139
to the scope of
Figure BSA000005363969001310
.
Next; Shown in Fig. 2 H and Fig. 2 I; Can on buffer insulation layer 123, apply the second photoresist layer 125, the second photoresist layer 125 is made public and develop, then its patterning formed the 2nd PR mask 125a through the photoetching process of using second mask 130.
Then, shown in Fig. 2 J, can use the 2nd PR mask 125a to come etch buffer insulating barrier 123.In addition, can be through using CHF with mode independent or that mix 3, CF 4And CH 2F 2Gas comes etch buffer insulating barrier 123.Can add such as N 2, O 2, gas such as Ar controls etch-rate or cross-sectional profiles.
Next, can on metal etch equipment, place substrate 101.Then; Utilize the 2nd PR mask 125a and buffering insulating barrier 123 to come sequentially etching the first metal layer 105 and metal wiring layer 103; Reach interconnection cover layer 105b down to form metal line 103a with following interconnecting metal layer 103b, bottom electrode 105a, thereby accomplish the technology that forms MIM capacitor 400.In addition, when etching the first metal layer 105 and metal wiring layer 103, can use Cl with independent mode 2Or BCl 3, and can use such as N 2, C 2H 4, CH 4, CHF 3, gas such as Ar realizes cross-sectional profiles.Subsequently, shown in Fig. 2 K, utilize oxygen (O 2) plasma removes the second photoresist layer pattern 125a.
Next, shown in Fig. 2 L, in order to fill the zone between metal line 103a and the following interconnecting metal layer 103b, can plated metal between insulating barrier 131.Can carry out chemical-mechanical planarization (CMP) technology and make internallic insulating layers 131 planarizations.
Subsequently, shown in Fig. 2 M, utilize the mask (not shown) the 3rd photoresist layer (not shown) to be made public and develop,, thereby form the 3rd photoresist layer pattern 133 then with the 3rd photoresist patterned through photoetching process.
Next, shown in Fig. 2 N, can form through hole 135a, 135b and 135c come to Connect Power respectively utmost point 109a and bottom electrode 105a simultaneously.Form the first opening 135a through etching interlayer insulating film 131 and buffering insulating barrier 123, form the second opening 135b through etching interlayer insulating film 131, buffer insulation layer 123 and hard mask 111a.If the etched dielectric regions 107a with high-k remains when formation is used for forming the through hole of bottom electrode 105a, then etched dielectric regions 107a can play the effect of etch part, causes opening to lose efficacy.Yet,, lost efficacy so can prevent opening owing to removed (for example, in Fig. 2 F) fully before the etched dielectric regions 107a.
Subsequently, shown in Fig. 2 O, deposition is used to fill the 3rd metal level 137 of the first opening 135a and the second opening 135b on interlayer insulating film 131.At this moment, can utilize sputtering technology, chemical vapor deposition method, ald (ALD) technology, electron beam deposition technology, pulsed laser deposition (PLD) technology to wait and form the 3rd metal level 137.In addition, can use tungsten (W), aluminium (Al), titanium, tantalum, copper, tungsten nitride, aluminium nitride, titanium nitride, TiAlN, tantalum nitride to wait and form the 3rd metal level 137.In this embodiment, utilize tungsten (W) to form the 3rd metal level 137.
Next, shown in Fig. 2 P, make 137 planarizations of the 3rd metal level, thereby in the first opening 135a, form the first plug 137a and in the second opening 135b, form the second plug 137b through CMP process.At this moment, the first plug 137a is connected to bottom electrode 105a, and the second plug 137b is connected to top electrode 109a.
Subsequently, shown in Fig. 2 Q, on the interlayer insulating film 131 that comprises the first plug 137a and the second plug 137b, sequentially deposit the 4th metal level 139 and anti-reflecting layer 141, on anti-reflecting layer 141, apply the 4th photoresist layer (not shown) then.
Next; Though do not have shown in the drawings; But utilize the mask (not shown) the 4th photoresist layer (not shown) to be made public and develop through photoetching process, and with the 4th photoresist patterned, thereby the 4th photoresist layer pattern 143 formed.Subsequently; Shown in Fig. 2 R; Utilize the 4th photoresist layer pattern 143 sequentially etching anti-reflecting layer 141 and the 4th metal level 139; Be connected to the second pad 139b and the second anti-reflecting layer pattern 141b of top electrode 109a to form to be connected to the first pad 139a and the first anti-reflecting layer pattern 141a of bottom electrode 105a and to form, form technology thereby accomplish wiring through the second plug 137b through the first plug 137a.Metal closures 137a is connected to that bottom electrode 105a, metal closures 137b are connected to top electrode 109a, metal closures 137c is connected to down interconnection cover layer 105b.One total aspect, can tungsten (W) be used for metal closures.Can the first pad 139a be formed on metal closures 137a top, can the second pad 139b be formed on metal closures 137b top, and can be formed on metal closures 137c top, form technology thereby accomplish wiring with going up interconnecting metal layer 139c.
As stated, MIM capacitor can be isolated with external environment condition and avoided various defectives, thereby guarantees good leakage current characteristic.In addition, in etching process, the SiON that is deposited on the metal level top can cushion etch target, thereby prevents the breakdown voltage characteristics deterioration of MIM capacitor.
In addition, the horizontal length of bottom electrode (or width) can be greater than the horizontal length (or width) of top electrode.Form longlyer than top electrode through the horizontal length that makes dielectric layer, top electrode can separate with bottom electrode well, thereby helps to suppress the generation of leakage current.Owing to realized making method, be possible so have excellent reliability according to puncture voltage, defect concentration etc. according to the MIM capacitor of aforementioned total aspect.
Comprise that the term such as " first ", " second " etc. can be used to describe various elements, but these elements should not receive the restriction of these terms.These terms only are used for an element and the difference of another element are come.For example, under the situation of the scope that does not break away from claim, first element can be called as second element, and similarly, second element can be called as first element.
It should be noted that term used herein is in order to describe total aspect, and be not intended to limit.What also will mention is that only if use clearly in addition, otherwise the statement of odd number also comprises plural.In this application; Term " comprises ", " comprising " etc.; Intention is expressed and is had said characteristic, numeral, step, operation, element, parts or their combination, does not exist or additional another feature, numeral, step, operation, element, parts or their combination but be not intended to get rid of.
Only if definition is arranged in addition, otherwise term used herein (comprising technical term or scientific terminology) has the meaning equivalent in meaning with those of ordinary skills institute common sense.The term that here uses not only should be explained based on the definition in any dictionary, also should be explained based on the meaning of using in the art.In addition, only if clearly definition is arranged, otherwise should too desirable or formally not explain the term that uses here.
Some examples have been described above.Yet, will be appreciated that and can carry out various modifications.For example; If said technology is carried out with different orders; If and/or the assembly in described system, system, device or the circuit makes up according to different modes and/or by other assemblies or their equivalent replacement or additional, then can obtain suitable result.Therefore, other execution modes within the scope of the claims.

Claims (36)

1. semiconductor device, said semiconductor device comprises:
Bottom electrode is formed on the substrate;
Dielectric layer comprises etched dielectric regions that is formed on the bottom electrode and the dielectric regions of growing as usual;
Top electrode is formed on the dielectric regions of growth as usual;
Hard mask is formed on the top electrode;
Separator is formed on the side surface place and the etched dielectric regions top of side surface and the top electrode of hard mask;
Buffer insulation layer is formed on hard mask and the separator.
2. semiconductor device as claimed in claim 1, wherein, said dielectric layer comprises ald high-k HfO 2/ Al 2O 3The membrane stack overlapping piece.
3. semiconductor device as claimed in claim 1 wherein, uses same mask with hard mask and top electrode patterning, so that hard mask and top electrode are of similar shape.
4. semiconductor device as claimed in claim 1, wherein, said separator is isolated the side surface of hard mask and the side surface of top electrode.
5. semiconductor device as claimed in claim 1, wherein, the said dielectric regions of growth is as usual separated bottom electrode and top electrode.
6. semiconductor device as claimed in claim 1, wherein, the length of said bottom electrode is greater than the length of top electrode.
7. semiconductor device as claimed in claim 6, wherein:
Bottom electrode comprises TiN/Ti;
Top electrode comprises TiN.
8. semiconductor device as claimed in claim 1, wherein,
Etched dielectric regions is extended from the zone of growth as usual and is stopped about the end of separator greatly; The said end of separator is formed on a side of separator, and a said side is relative with the side that side surface separator and side surface hard mask and top electrode contacts;
The thickness of etched dielectric regions is less than the thickness of the dielectric regions of growing as usual.
9. semiconductor device as claimed in claim 8, wherein, the said end of separator is cushioned insulating barrier and etched dielectric regions limits.
10. semiconductor device as claimed in claim 1, said semiconductor device also comprise the dielectric regions that being formed on as usual growth and the dielectric regions of the bending between the etched dielectric regions.
11. semiconductor device as claimed in claim 10, wherein, said separator is formed on crooked dielectric regions top.
12. semiconductor device as claimed in claim 10, wherein:
Etched dielectric regions is extended also greatly about the termination of the end of separator from the dielectric regions of bending; The said end of separator forms a side of separator, the side that a said side contacts with side surface separator and side surface hard mask and top electrode relative;
Crooked dielectric regions is constructed to connect etched dielectric regions and the dielectric regions of growing as usual;
The thickness of etched dielectric regions is less than the thickness of the dielectric regions of growing as usual and the thickness of the dielectric regions of bending.
13. semiconductor device as claimed in claim 1, wherein, said buffer insulation layer comprises SiON.
14. a method of making semiconductor device said method comprising the steps of:
On substrate, form the first metal layer;
Sequentially lamination dielectric layer, second metal level, hard mask insulator on the first metal layer;
Optionally etch hard mask insulator, second metal level and dielectric layer are to form hard mask, top electrode and to have etched dielectric regions and the dielectric layer of the dielectric regions of growth as usual;
Formation separator insulator on the etched dielectric regions of the side surface of the upper surface of hard mask and side surface, top electrode and dielectric layer pattern;
Etching separator insulator is to form separator at the side surface of hard mask, the side surface of top electrode and the etched dielectric regions place of dielectric layer;
On separator, hard mask and the first metal layer, form buffer insulation layer;
With buffer insulation layer and the first metal layer patterning, to form bottom electrode.
15. the method for manufacturing semiconductor device as claimed in claim 14, wherein, optionally the step of etch hard mask insulator, second metal level and dielectric layer comprises the part of the etched dielectric regions of etching second metal level below.
16. the method for manufacturing semiconductor device as claimed in claim 15, wherein, the said part of etching is included between dielectric regions and the etched dielectric regions of as usual growth and forms crooked dielectric regions.
17. the method for manufacturing semiconductor device as claimed in claim 16, wherein:
The dielectric regions of the lower surface contact etch of separator;
The side surface of separator contacts hard mask and top electrode;
The curved surface of separator contacts buffer insulation layer and crooked dielectric regions respectively.
18. the method for manufacturing semiconductor device as claimed in claim 14, wherein:
The dielectric regions of the lower surface contact etch of separator;
The side surface of separator contacts hard mask and top electrode.
19. the method for manufacturing semiconductor device as claimed in claim 18, wherein, the thickness of etched dielectric regions is less than the thickness of the dielectric regions of growing as usual.
20. the method for manufacturing semiconductor device as claimed in claim 14, wherein, said buffer insulation layer comprises SiON.
21. a MIM capacitor, said MIM capacitor comprises:
Bottom electrode is formed on the substrate;
Dielectric layer is formed on the bottom electrode, has different first area of thickness and second area;
Top electrode is formed on the second area of dielectric layer;
Hard mask is formed on the top electrode;
Separator is formed on the side surface of hard mask, the side surface of top electrode and the side surface place of dielectric layer.
22. MIM capacitor as claimed in claim 21, wherein, the thickness of the first area that is positioned at the separator bottom of dielectric layer is less than the thickness of the second area that is positioned at the top electrode below of dielectric layer.
23. MIM capacitor as claimed in claim 21, wherein, buffer insulation layer is formed on the upper surface of upper surface and dielectric layer of upper surface, top electrode of hard mask.
24. MIM capacitor as claimed in claim 21, wherein, the lower surface of separator contacts with the first area of dielectric layer, and the side surface of separator contacts with the second area of top electrode and dielectric layer.
25. a MIM capacitor, said MIM capacitor comprises:
Bottom electrode and top electrode are formed on the substrate;
Dielectric layer is formed between bottom electrode and the top electrode and has high-k;
First protective layer is around the side surface and the upper surface of top electrode;
Second protective layer, around the side surface of dielectric layer and the side surface of first protective layer,
Wherein, the width of dielectric layer is greater than the width of top electrode, and first protective layer and second protective layer are processed by the etch-rate material different.
26. MIM capacitor as claimed in claim 25, wherein, dielectric layer comprises by Al 2O 3, HfO 2And HfO 2/ Al 2O 3Layer structure and the HfO of repetition 2/ Al 2O 3In the insulating material group that the laminar structure of layer is formed any one.
27. a method of making MIM capacitor said method comprising the steps of:
On substrate, form bottom electrode;
On bottom electrode, form dielectric layer with the different first area of thickness and second area;
On the second area of dielectric layer, form top electrode and hard mask;
Form separator at the side surface of hard mask, the side surface of top electrode and the side surface of dielectric layer.
28. method as claimed in claim 27, wherein, said formation top electrode comprises with the step of hard mask:
On dielectric layer, sequentially form metal level and insulating barrier;
On insulating barrier, form the photoresist layer pattern;
Utilize the photoresist layer pattern as mask layer with insulating barrier and metal layer patternization, to form hard mask and top electrode.
29. method as claimed in claim 28, wherein, in said step with insulating barrier and metal layer patternization, the segment thickness of the first area that is positioned at metal level below of etching dielectric layer together.
30. method as claimed in claim 29; Wherein, the thickness of the remaining first area after being etched of dielectric layer for
Figure FSA00000536396800041
to
Figure FSA00000536396800042
31. method as claimed in claim 29, wherein, the step of said formation separator comprises:
On the exposed surface of the second area of the side surface of the first area of dielectric layer, hard mask and top electrode and dielectric layer, form the separator insulator;
The whole surface of etching separator insulator is to form separator at the side surface of hard mask, the side surface of top electrode and the side surface place of dielectric layer.
32. method as claimed in claim 31 wherein, in the step on the whole surface of said etching separator insulator, comes along the first area in the zone except separator of dielectric layer.
33. method as claimed in claim 31, wherein, the lower surface of separator contacts with the first area of dielectric layer, and the side surface of separator contacts with the second area of hard mask, top electrode and dielectric layer.
34. method as claimed in claim 33, wherein, the thickness that contacts with lower surface separator the first area of dielectric layer is less than the thickness of the second area that contacts with the top electrode below of dielectric layer.
35. method as claimed in claim 27, wherein, the step of said formation bottom electrode comprises:
On substrate, be formed for forming the metal level of bottom electrode;
On metal level, sequentially form dielectric layer, top electrode and hard mask;
Form separator at the side surface of dielectric layer, the side surface of top electrode and the side surface place of hard mask;
On metal level, separator and hard mask, form buffer insulation layer;
Optionally with buffer insulation layer and metal layer patternization, to form bottom electrode.
36. method as claimed in claim 27, wherein, dielectric layer comprises by SiN, SiO 2, Al 2O 3, HfO 2, Ta 2O 5And HfO 2/ Al 2O 3Layer structure and the HfO of repetition 2/ Al 2O 3In the insulating material group that the laminar structure of layer is formed any one.
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