KR20120008402A - Metal insulator metal capacitor and method for fabricating the same - Google Patents

Abstract

PURPOSE: A metal-insulator-metal(MIM) capacitor and a manufacturing method thereof are provided to completely separate the MIM capacitor from an external environment, thereby improving reliability and minimizing influences with respect to following processes. CONSTITUTION: A lower electrode(105a) is arranged on a substrate(101). A dielectric film(107) is arranged on the lower electrode. The dielectric film is comprised of a first region and a second region(107a) which have different thicknesses. An upper electrode(109a) is arranged on the second region of the dielectric film. A hard mask is arranged on the upper electrode. A spacer(121a) is arranged on a lateral surface of the dielectric film, upper electrode, and hard mask.

Description

MIM Capacitor and Manufacturing Method therefor {METAL INSULATOR METAL CAPACITOR AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a capacitor and a method for manufacturing the same, and more particularly, to a metal-insulator-metal (MIM) capacitor having a high dielectric constant and a method for manufacturing the same.

In general, the semiconductor device is required to operate at a high speed while having a high storage capacity in terms of its function.

To this end, manufacturing techniques have been developed for semiconductor devices to improve integration, response speed, and reliability. In order to improve the refresh characteristic of the semiconductor device, a capacitance value of a component such as a capacitor included in the semiconductor device must be large.

However, in recent years, as the semiconductor devices are highly integrated, the unit cell area continues to decrease. Accordingly, the cell capacitance of the semiconductor device is also reduced, making it difficult to secure the capacitance required for the operation of the device.

In general, the capacitance of the capacitor has an increased capacitance as the area of the counter electrode is larger, the dielectric constant of the dielectric between the electrodes is higher, and the thickness of the dielectric is thinner. Therefore, in order to obtain an appropriate capacitance, the structure of the capacitor is diversified while reducing the thickness of the dielectric.

Meanwhile, BST (Ba, Sr) TiO ₃ ) and strontium titanium oxide (perovskite) having a high dielectric constant instead of an oxide / nitride / oxide (ONO) dielectric layer used as a dielectric material of a capacitor until recently. research into applying a material having a high dielectric constant, such as SrTiO _3), barium titanium oxide (BaTiO ₃₎ to give the appropriate capacitance may in progress.

However, when a high-k material having such a high dielectric constant is used as an insulating film of an M capacitor, the subsequent insulating film affects the subsequent process due to the remaining insulating film after etching the upper electrode of the MM capacitor. Go crazy.

In addition, due to the remaining high dielectric constant insulating film (PR; photoresist) margin and the generation of metallic polymer (poor) the metal wiring profile is poor, and the hole (hole) in the subsequent via etching process The metallic polymer remains inside. Due to these problems, the via resistance is increased, thereby reducing the reliability of the capacitor.

In addition, when the subsequent via over etch target is increased to remove the remaining insulating layer, breakdown voltage characteristic degradation occurs.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, the object of the present invention is to completely isolate the IC capacitor from the external environment to improve the reliability and minimize the impact on the subsequent process, to the via transient etching target It is to provide an M capacitor and a method of manufacturing the same that can prevent the breakdown voltage degradation.

In order to achieve the above object, the M capacitor according to an embodiment of the present invention, the lower electrode formed on the substrate; A dielectric film formed on the lower electrode and configured of a first region and a second region having different thicknesses; An upper electrode formed on the second region of the dielectric layer; A hard mask formed on the upper electrode; And a spacer formed on the hard mask, the second region of the dielectric layer, and the side of the upper electrode.

MIM semiconductor device according to an embodiment of the present invention for achieving the above object, the lower electrode and the upper electrode formed on the substrate; A dielectric film having a high dielectric constant formed between the lower electrode and the upper electrode; A first passivation layer surrounding the upper electrode side surface and the upper surface; And a second passivation layer surrounding the sidewalls of the dielectric layer and the passivation layer, wherein the width of the dielectric layer is greater than the width of the upper electrode, and the first passivation layer and the second passivation layer are formed of materials having different etching rates. It is characterized by.

In order to achieve the above object, the M capacitor manufacturing method according to an embodiment of the present invention, forming a lower electrode on the substrate; Forming a dielectric film on the lower electrode; Forming an upper electrode and a hard mask on the dielectric layer; And forming a spacer on side surfaces of the dielectric layer, the upper electrode, and the hard mask.

In order to achieve the above object, the M capacitor manufacturing method according to an embodiment of the present invention, forming a first metal film on the substrate; Sequentially stacking a dielectric film, a second metal film, and a hard mask insulating film on the first metal film; Patterning the hard mask insulating layer and the second metal layer to form a hard mask and an upper electrode; Forming a spacer insulating film on an entire surface of the substrate including the hard mask, the upper electrode, and the dielectric film; Etching the entire spacer insulating film to form a spacer on side surfaces of the hard mask, the upper electrode, and the dielectric film; Forming a buffer insulating layer on the spacer, the hard mask, and the first metal layer; And patterning the buffer insulating film and the first metal film to form a lower electrode.

According to the present invention, the MIM capacitor is isolated from the external environment and protected from various defects, thereby ensuring good leakage current characteristics.

In addition, according to the present invention, it is possible to secure good via resistance since the insulating film remaining in the spacer etching step of the M capacitor is not affected by the subsequent process.

In addition, according to the present invention, the SiON deposited on the metal layer may prevent the deterioration of breakdown voltage characteristics of the M capacitor by buffering the etching target during the via etching.

Therefore, when the M capacitor manufacturing process according to the present invention is used, it has very excellent characteristics in terms of reliability, such as breakdown voltage and defect density.

1 is a schematic cross-sectional view for explaining an MIM capacitor according to the present invention.
2A to 2R are cross-sectional views illustrating a method of manufacturing an MIM capacitor according to the present invention.

Hereinafter, an M capacitor structure according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic cross-sectional view of an MI capacitor according to a preferred embodiment of the present invention.

Referring to FIG. 1, an M capacitor according to the present invention is formed on a lower electrode 105a formed on a substrate 101, on the lower electrode 105a, has a high dielectric constant value, and has a first region. And a dielectric film 107 including a dielectric film protrusion 107a which is a second region protruding from the first region, an upper electrode 109a and the dielectric film 107 formed on the first region of the dielectric film 107. It is configured to include a spacer (121a) formed on the side of the upper electrode (109a).

The dielectric layer 107 includes a first region overlapping the upper electrode 109a and a dielectric layer protrusion 107a which is a second region extending from the first region. In this case, the horizontal length (or width) of the dielectric layer is longer than the length (or width) of the upper electrode 109a formed on the dielectric layer 107. This is because the dielectric film is formed wider than the upper electrode, thereby separating the upper electrode and the lower electrode well, thereby helping to suppress the occurrence of leakage. If the dielectric film and the upper electrode have the same width, there is a possibility that leakage occurs due to the electric field along the side surface because the length between the upper electrode and the lower electrode is short. However, if the width of the dielectric film is larger than the upper electrode as in the present invention, such a problem can be prevented.

A lower structure is formed on the substrate 101. The lower structure may include a pad, a plug, a conductive layer pattern, an insulating layer pattern, a gate structure, a transistor, and the like. In addition, the substrate 101 may include a semiconductor substrate or a metal oxide single crystal substrate. For example, the substrate 101 may include a silicon substrate, a germanium substrate, an SOI substrate, a GOI substrate, an aluminum oxide single crystal substrate, a titanium oxide single crystal substrate, or the like.

In addition, an insulating structure (not shown) is interposed between the substrate 101 and the capacitor. The insulating structure may have a single film structure consisting of one oxide film. For example, the insulating structure (not shown) may be formed using BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, or the like. Meanwhile, the insulating structure (not shown) may have a multilayer film structure including at least one oxide film, at least one nitride film, and / or at least one oxynitride film formed on the substrate 101. Here, the oxide film, nitride film and oxynitride film may be formed using silicon nitride, silicon nitride and silicon oxynitride, respectively.

A metal wiring 103a is formed between the substrate 101 and the lower electrode 105a. The metal wire 103a may be made of aluminum (Al), tungsten, titanium, tantalum, copper, tungsten nitride, aluminum nitride, titanium nitride, titanium aluminum nitride, tantalum nitride, or the like, each of which may be used alone or mixed with each other. Can be. In the embodiment of the present invention, the metal wiring 103a is made of aluminum (Al).

In addition, the lower electrode 105a may be formed using a metal, an alloy, or a conductive metal compound. For example, the lower electrode 105a may be any one or more selected from the group consisting of Ru, SrRuO ₃ , Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu, or an alloy thereof. Each of these may be used alone or in combination with each other. In the embodiment of the present invention, the lower electrode 105a is formed of TiN.

In addition, the dielectric layer 107 may be formed of any one of an insulating material including SiN, Ta ₂ O ₅ , HfO ₂ , Al ₂ O _3, or the like having a high dielectric constant value, or may have a capacity of an MIM capacitor. For the purpose of increasing, a laminate structure such as HfO ₂ / Al ₂ O ₃ or a HfO ₂ / Al ₂ O ₃ layer may be formed in a laminate structure in which the layer is repeated. Here, the HfO ₂ layer is effective to reduce the leakage current (leakage current).

In addition, the upper electrode 109a may be formed using a metal, an alloy, or a conductive metal compound. For example, the upper electrode 109a is at least one selected from the group consisting of Ru, SrRuO ₃ , Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu, or an alloy thereof. Each of these may be used alone or mixed with each other. In the embodiment of the present invention, the upper electrode 109a is formed of TiN.

In addition, a hard mask 111a is formed on the upper electrode 109a. The hard mask 111a may have a single film structure including one oxide film. For example, the hard mask 111a may be formed of silicon oxide based such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD, or nitride based such as SiN and SiON. The hard mask 111a may have a multilayer film structure including at least one oxide film, at least one nitride film, and / or at least one oxynitride film. Here, the oxide film, nitride film and oxynitride film may be formed using silicon nitride, silicon nitride and silicon oxynitride, respectively. On the other hand, the thickness of the hard mask 111a is preferably about 100 ~ 4000Å.

The spacer 121a may have a single film structure including one oxide film. For example, the spacer 121a may be formed of silicon oxide based such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD, and nitride based such as SiN and SiON. In addition, the spacer 121a may have a multilayer film structure including at least one oxide film, at least one nitride film, and / or at least one oxynitride film. Here, the oxide film, nitride film and oxynitride film may be formed using silicon nitride, silicon nitride and silicon oxynitride, respectively. On the other hand, the thickness of the spacer 121a is preferably about 100 to 4000 mm.

A dielectric film protrusion 107a exists below the spacer 121a, and a lower electrode 105a exists below the dielectric film protrusion 107a. The thickness of the dielectric film protrusion 107a under the spacer 121a is thinner than the thickness of the dielectric film 107 between the upper electrode 109a and the lower electrode 105a. In addition, the upper electrode 109a, the dielectric layer 107, and the hard mask 111a are in contact with the side surface of the spacer 121a. Therefore, due to the spacer 121a, the MIM capacitor is isolated from the external environment and protected from various defects, thereby obtaining good leakage current characteristics.

In addition, a buffer insulating layer 123 is formed on the hard mask 111a including the spacer 121a and the lower electrode 105a. The buffer insulating film 123 is composed of SiON, a silicon oxynitride film containing nitrogen atoms, and the insulating film 123 composed of SiON serves as an anti-reflection film for margin improvement of a lithography process during subsequent metal patterning. In addition, the buffer insulating layer 123 also serves as a buffer layer for buffering the via etch target. In addition, the buffer insulating layer 123 may also be used as an etch stopper that serves as an etch stop when forming a via hole. Here, the thickness of the buffer insulating film 123 is preferably about 50 to 1000 GPa. The buffer insulating layer 123 may be formed using organic BARC instead of inorganic SiON.

In addition, an interlayer insulating film 131 is formed on the entire surface of the substrate including the metal wiring 103a, the lower electrode 105a, and the buffer insulating film 123, and the lower electrode 105a and the upper electrode 109a are formed therein. First and second openings 135a and 135b for exposing are formed.

First and second plugs 137a and 137b are formed in the first and second openings 135a and 135b, respectively. The first and second plugs 137a and 137b may be formed of tungsten (W), aluminum (Al), titanium, tantalum, copper, tungsten nitride, aluminum nitride, titanium nitride, titanium aluminum nitride, tantalum nitride, or the like. In the embodiment of the present invention, the first and second plugs 137a and 137b are formed using tungsten (W).

On the interlayer insulating film 131 including the first and second plugs 137a and 137b, the first and second electrodes 137a and 137b are connected to the lower electrode 105a and the upper electrode 109a, respectively. The second pads 139a and 139b and the first and second anti-reflection film patterns 141a and 141b are stacked.

As described above, according to the present invention, the MIM capacitor is isolated from the external environment and protected from various defects, thereby obtaining good leakage current characteristics.

On the other hand, it will be described with reference to Figures 2a to 2r with respect to the M capacitor manufacturing method according to the present invention.

2A to 2R are cross-sectional views illustrating a method of manufacturing an MIM capacitor according to the present invention.

Although not shown in the drawings, a lower structure (not shown) is first formed on the substrate 101, and then an interlayer insulating film (not shown) is deposited on the lower structure. In this case, the substrate 101 may include a semiconductor substrate or a metal oxide single crystal substrate. For example, the substrate 101 may include a silicon substrate, a germanium substrate, an SOI substrate, a GOI substrate, an aluminum oxide single crystal substrate, a titanium oxide single crystal substrate, or the like. Although not shown in the drawing, the lower structure may include a pad, a conductive pattern, a wiring, a gate structure, a transistor, and the like formed on the substrate 101.

In addition, the interlayer insulating film (not shown) may be a chemical vapor deposition (CVD) process, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a high density plasma chemical vapor deposition (HDP-CVD) process. It can form using. The interlayer insulating film may have a single film structure consisting of one oxide film. For example, the interlayer insulating film (not shown) may be formed using BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD oxide, or the like. Meanwhile, the interlayer insulating film (not shown) may have a multilayer film structure including at least one oxide film, at least one nitride film, and / or at least one oxynitride film formed on the substrate 101. Here, the oxide film, nitride film and oxynitride film may be formed using silicon nitride, silicon nitride and silicon oxynitride, respectively.

Next, as illustrated in FIG. 2A, a metal wiring layer 103 and a first metal layer 105 for use as a lower electrode are sequentially deposited on the interlayer insulating layer (not shown). In this case, the thickness of the metal wiring layer 103 may be changed according to the Rs (resistance) value required in the wiring process. In addition, the metal wiring layer 103 may be formed using a sputtering process, a chemical vapor deposition process, an atomic layer deposition (ALD) process, an electron beam deposition process, a pulsed laser deposition (PLD) process, or the like. In addition, the metal wiring layer 103 may be formed using aluminum (Al), tungsten, titanium, tantalum, copper, tungsten nitride, aluminum nitride, titanium nitride, titanium aluminum nitride, tantalum nitride, or the like. In the embodiment of the present invention, the metal wiring film 103 is formed by using aluminum (Al).

The first metal layer 105 may be formed using an atomic layer deposition process, a sputtering process, an electron beam deposition process, a chemical vapor deposition process, or a pulse laser deposition process. In addition, the first metal layer 105 may be formed using a metal, an alloy, or a conductive metal compound. For example, the first metal film 105 is any one selected from the group consisting of Ru, SrRuO ₃ , Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu, or an alloy thereof. As described above, each of them may be used alone or in combination with each other. In the embodiment of the present invention, the first metal film 105 is formed by using TiN.

On the other hand, after forming the first metal film 105, in order to improve the electrical characteristics of the first metal film 105 used as a lower electrode, a heat treatment process, ozone (O ₃ ) to the first metal film 105 ) Process, oxygen (O ₂ ) process, plasma heat treatment process may be added and performed.

Subsequently, a dielectric film 107 is deposited on the first metal film 105. In this case, the dielectric layer 107 may be formed using an atomic layer deposition process, a sputtering process, a pulse laser deposition process, an electron beam deposition process, or a chemical vapor deposition process. In addition, the dielectric layer 107 may use any one of an insulating material including SiN, Ta ₂ O ₅ , HfO ₂ , Al ₂ O _3, or the like having a high dielectric constant, or may have a capacity of an MIM capacitor. It is also possible to use a laminate structure such as HfO ₂ / Al ₂ O ₃ or a laminate structure in which the HfO ₂ / Al ₂ O ₃ layer is repeated for the purpose of increasing the number of layers. In addition, the HfO ₂ layer is effective to reduce leakage current.

In addition, since the insulating material having a high-k value such as Ta ₂ O ₅ , HfO ₂ , and Al ₂ O ₃ is difficult to etch, it is difficult to etch when the layer thickness is too thick. If too thin, a leakage current will occur, so it is necessary to deposit it at an appropriate thickness. As will be described later, if the insulating material having the high dielectric constant value is left long sideways on the lower metal film, there is a problem in the etching process for forming the via opening. However, in the case of SiN, even if it remains on the lower metal film sideways, it does not become a problem because it is easily etched during the formation of the via opening. However, in order to increase the capacitance of the capacitor, the thickness of SiN must be lowered. Since the thickness of SiN is thin, there is a leakage current problem. Therefore, if the thickness is the same, it is recommended to use a material having a high dielectric constant. desirable. Meanwhile, after the dielectric film 107 is formed, a heat treatment process, an ozone treatment process, an oxygen treatment process, a plasma heat treatment process, and the like are performed on the dielectric film 107 to improve the electrical characteristics of the dielectric film 107. can do. In this case, the dielectric layer 107 is defined as a first region and a second region, wherein the first region is a region where a part of thickness is etched in a subsequent process, and the second region is a region that is not etched and the dielectric of the M capacitor It means the area to use.

Next, a second metal film 109 is deposited on the dielectric film 107 for use as an upper electrode. In this case, the second metal layer 109 may be formed using an atomic layer deposition process, a sputtering process, an electron beam deposition process, a chemical vapor deposition process, or a pulsed laser deposition process. In addition, the second metal layer 109 may be formed using a metal, a sum, or a conductive metal compound. For example, the second metal film 109 is any one selected from the group consisting of Ru, SrRuO ₃ , Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, Cu, or an alloy thereof. As described above, each of them may be used alone or in combination with each other. In a preferred embodiment of the present invention, the second metal film 109 is formed using TiN. On the other hand, after forming the second metal film 109, in order to improve the electrical characteristics of the second metal film 109 used as the upper electrode, a heat treatment process, ozone (O ₃ ) to the second metal film 109 ) Process, oxygen (O ₂ ) process, plasma heat treatment process may be added and performed.

Subsequently, a hard mask insulator 111 is deposited on the second metal layer 109. In this case, the hard mask 111 may use a chemical vapor deposition (CVD) process, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a high density plasma chemical vapor deposition (HDP-CVD) process. Can be formed. The hard mask insulating layer 111 may have a single layer structure consisting of one oxide layer. For example, the hard mask insulating layer 111 may use both silicon oxide series such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD, and nitride series such as SiN and SiON. In addition, the hard mask insulating layer 111 may have a multilayer film structure including at least one oxide film, at least one nitride film and / or at least one oxynitride film. Here, the oxide film, nitride film and oxynitride film may be formed using silicon nitride, silicon nitride and silicon oxynitride, respectively. On the other hand, the deposition thickness of the hard mask insulating film 111 is preferably deposited to about 100 ~ 4000Å.

Next, as illustrated in FIGS. 2B and 2C, a first photoresist layer (etched) may be used to etch the hard mask insulating layer 111 and the second metal layer 109 on the hard mask insulating layer 111. 113 is applied, the first photoresist layer 113 is exposed and developed through a photolithography process using the first mask 120, and then patterned to form the first photoresist layer pattern 113a.

Subsequently, as shown in FIG. 2D, the first photoresist layer pattern 113a is used as a blocking layer, and the upper surface electrode is sequentially etched by using the hard mask insulating layer 111 and the second metal layer 109 for use as the upper electrode. 109a is formed. In this case, in order to prevent the first metal film 105 for use as the lower electrode from being exposed to the outside, the etching process may be stopped in the dielectric film 107. When the first metal layer 105 for the lower electrode is exposed during the etching of the hard mask insulating layer 111 and the second metal layer 109, a metal polymer is generated to cause leakage current. Because it becomes. Further, when the hard mask insulating layer 111 and the second metal layer 109 are etched, a part of the thickness of the first region (that is, the dielectric layer protrusion 107a) is formed among the first region and the second region of the dielectric layer 107. Is partially etched, which may be smaller than the initially deposited thickness, leaving the first region 107a of the dielectric film with a thickness thinner than the initial thickness because the metal polymer does not accumulate. In this case, the thickness of the remaining dielectric film protrusion 107a is preferably about 50 to about 100 GPa, and in order to improve the process margin, the thickness control of the remaining dielectric film protrusion 107a is controlled. On the other hand, when the etching process is performed using the first photoresist pattern 113a as a blocking film, the hard mask 111 may be etched using CF ₄ / CH _x F _y / O ₂ / N ₂ / Ar and the like. Using the gas of the upper part of the M capacitor Cl ₂ / BCl ₃ is used for etching the second metal film 109 for the pole, and N ₂ or Ar is used as an additive gas to control the etching profile.

Next, as shown in FIG. 2E, a spacer insulator 121 is deposited on the entire surface of the substrate including the selectively etched hard mask 111a, the upper electrode 109a, and the dielectric layer 107. In this case, the spacer insulating layer 121 may use a chemical vapor deposition (CVD) process, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a high density plasma chemical vapor deposition (HDP-CVD) process. Can be formed. The spacer insulating layer 121 may have a single layer structure formed of one oxide layer. For example, the spacer insulating layer 121 may use both a silicon oxide series such as BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD, and a nitride series such as SiN and SiON. In addition, the spacer insulating layer 121 may have a multilayer film structure including at least one oxide film, at least one nitride film, and / or at least one oxynitride film. Here, the oxide film, nitride film and oxynitride film may be formed using silicon nitride, silicon nitride and silicon oxynitride, respectively. On the other hand, the deposition thickness of the spacer insulating film 121 is preferably deposited to about 100 ~ 4000Å. The spacer insulating layer 121 may be made of the same material as the deposition material of the hard mask insulating layer 111. This is to improve adhesion between the spacer insulating layer 121 and the hard mask insulating layer 111.

Next, as shown in FIG. 2F, the spacer insulating layer 121 is etched to form the spacer 121a by performing a blanket etch process without a separate mask. At this time, the dielectric film protrusion 107a remaining on the upper portion of the first metal layer 105 to be used as the lower electrode by using an over etch process, that is, the region excluding the spacer 121a from the first region of the dielectric film. Remove the part remaining in That is, since the dielectric film protrusion 107a having the high dielectric constant value has a problem in that dry etching is not well performed, the dielectric film protrusion 107a should be completely removed during the etching process. This is because the remaining dielectric layer protrusion 107a serves as an etching stopper in the etching process for forming a subsequent via opening unless the dielectric layer protrusion 107a is completely removed, thereby preventing the formation of the via opening. Because you can.

As a result, the width (or width) of the dielectric film is formed to be longer than the length (or width) of the upper electrode formed on the dielectric film through the spacer insulating film forming process. Since the dielectric film is formed wider than the upper electrode, the dielectric film is well separated between the upper electrode and the lower electrode, thereby helping to prevent leakage. If the dielectric film and the upper electrode have the same width, there is a possibility that leakage occurs due to the electric field along the side surface because the length between the upper electrode and the lower electrode is short. However, if the width of the dielectric film is large, as in the present invention, such a problem can be prevented.

Meanwhile, in the process of etching the spacer insulating layer 121, the hard mask 111a may also be slightly lost. This is because the material of the hard mask 111a and the material of the spacer insulating layer 121 are the same. In the process of etching the spacer insulating layer 121, the exposed upper portion of the first metal layer 105 may be slightly lost. This is because the spacer insulating layer 121 is excessively etched so that only side surfaces remain.

When the formation process of the spacer 121a is completed, the MAM capacitor is completely isolated from the external environment. As a result, the spacer insulating film also serves to protect the upper electrode side and the upper surface together with the hard mask insulating film. In this case, a dielectric film protrusion 107a is present under the spacer 121a, and a first metal layer 105 for the lower electrode exists under the dielectric film protrusion 107a. Here, the thickness of the dielectric film protrusion 107a under the spacer 121a is thinner than the thickness of the dielectric film 107 under the upper electrode 109a. In the etching process, for example, the first photoresist layer pattern 113a is used as a blocking layer, a portion of the dielectric layer 107 may be etched along with the hard mask insulating layer 111 and the second metal layer 109. (loss) occurs. The upper electrode 109a, the dielectric layer 107, and the hard mask 111a are in contact with the side surface of the spacer 121a.

Subsequently, as illustrated in FIG. 2G, a nitride-based buffer insulating layer 123 such as SiON is deposited on the entire surface of the substrate including the spacer 121a. In this case, the buffer insulating film 123 may be an insulating film having an etching rate different from that of the spacer insulating film or the material used for the hard mask. This is to induce an etch stop primarily in the buffer insulating layer when the via hole is formed. Here, the buffer insulating layer 123 is formed using SiON, and the SiON serves as an anti-reflection film for margin improvement of the lithography process during subsequent metal patterning. In addition, the buffer insulating layer 123 also serves as a buffer layer for buffering the via etch target. Here, the thickness of the buffer insulating film 123 is deposited to about 50 ~ 1000Å. In this case, since the buffer insulating layer 123 is deposited on the entire surface of the substrate, the buffer insulating layer 123 is in direct contact with the first metal layer 105 for the lower electrode exposed to the outside. In addition, SiON used as the buffer insulating film 123 is deposited using a SiH ₄ / N ₂ O gas in the temperature range of about 350 ~ 420 ℃, n (refractive) in consideration of the photo-lithography process margin The values of index) and k (extinction coefficient) can be changed to 1.80 to 2.2 and 0.30 to 0.45, respectively. In this case, the n and k values can be changed by adjusting the SiH ₄ / N ₂ O ratio, the n and k values increase as the SiH ₄ / N ₂ O ratio decreases, that is, as the N ₂ O fraction increases. do. In addition, when the reflectance value is high, it is possible to melt the photosensitive film PR next to it due to diffuse reflection, making it difficult to control the photo DI threshold value CD. On the other hand, the buffer insulating film 123, instead of the inorganic (Siorganic) SiON can use a �œ� BARC.

In addition, when the via over etch target is less than about 5000 microns, the SiON is about 50 to 400 microns for use as an anti-reflection film for securing photolithography process margins and photoresist (PR) micro-patterning. Deposit relatively thin in the range of.

However, when the via over etch target is about 5000 GPa or more, the SiON thickness is deposited thickly in the range of 400 to 1000 GPa. In addition, when etching to form vias, an oxide selectivity to SiON is increased by using gas chemical properties having a high C / F ratio such as C ₄ F ₈ , C ₅ F ₈ , C ₄ F ₆ , and the like. Let's do it. In this case, SiON not only functions as an anti-reflection film for PR fine patterning but also serves as a buffer layer for buffering a via etch target. In addition, the buffer insulating layer 123 may also be used as an etch stopper which serves as an etch stopping function when forming via holes.

On the other hand, in the case of SiON, if the pitch in the subsequent patterning process is not fine and the via over etch target is small at 5000 GPa or less, no deposition is necessary. However, if the PR pattern is severely distorted by the bottom reflection, an antireflection film such as SiON should be used for fine patterning.

Next, as shown in FIGS. 2H and 2I, a second photosensitive film 125 is coated on the buffer insulating film 123, exposed and developed by a photolithography process using the second mask 130, and then patterned. The second photosensitive film pattern 125a is formed.

Subsequently, as shown in FIG. 2J, the buffer insulating layer 123 is etched using the second photoresist layer pattern 125a as a blocking layer. In this case, the buffer insulating film 123 is etched by the dielectric film etching equipment. In addition, the buffer insulating layer 123 is etched using a combination of CHF ₃ , CF ₄ , and CH ₂ F ₂ gas alone or in combination, and a gas such as N ₂ , O ₂ , Ar, etc. is added to control the etching rate or the cross-sectional profile. can do.

Then, the substrate is transferred to the metal etching equipment, and then the first metal film 105 and the metal wiring film 103 for the lower electrode are sequentially etched to form the lower electrode 105a and the metal wiring 103a. Complete the capacitor formation process. In this case, when the metal wiring layer 103 is etched without the second photoresist layer pattern 125a, sidewall etching may occur, and thus the metal wiring layer 103 is etched while the second photoresist layer pattern 125a is present. In addition, when etching the first metal film 105 and the metallization film 103, N ₂ , C ₂ H ₄ , CH ₄ , CHF ₃ , Ar, etc., to implement a single or cross-sectional profile of Cl ₂ , BCl ₃ . Gas can be used.

Subsequently, as shown in FIG. 2K, after the metal wiring layer 105 is etched, the second photoresist layer pattern 125a is removed in-situ from the metal etching equipment. In this case, the reason that the second photoresist layer pattern 125a is removed in-situ after etching the metal interconnection layer 103 and the first metal layer 105 may be exposed to the atmosphere without removing the photoresist layer. This is because corrosion of metal wiring occurs due to moisture in the air. To prevent this, oxygen (O ₂ ) plasma is used in situ to remove the remaining photoresist film and polymer.

Next, as shown in FIGS. 2L and 2M, in order to perform a conventional wiring forming process, first, an interlayer insulating film 131 is deposited on the entire surface of the substrate including the metal wiring 103a and the lower electrode 105a. A third photosensitive film (not shown) is applied thereon.

Subsequently, as illustrated in FIG. 2M, the third photoresist film (not shown) is exposed and developed by a photolithography process using a mask (not shown), and then patterned to form a third photoresist pattern 133.

Next, the interlayer insulating layer 131, the insulating layer 123, and the hard mask 111a are sequentially patterned using the third photoresist layer pattern 133 as a blocking layer, and the upper electrode 109a is formed as shown in FIG. 2N. First and second openings 135a and 135b for connecting the lower electrode 105a are formed at the same time. In this case, the first opening 135a is formed by etching the interlayer insulating film 131 and the q buffer insulating film 123, and the second opening 135b is formed of the interlayer insulating film 131, the buffer insulating film 123, and the like. The hard mask 111a is formed by etching. In this case, when the first opening 135a for forming the lower electrode 105a is formed, if the dielectric film protrusion 107a having the high dielectric constant remains, it serves as an etch barrier to open the defect. A failure may occur, but this opening defect is prevented because the dielectric film protrusion 107a is completely removed in the previous step, that is, FIG. 2F.

Subsequently, as shown in FIG. 2O, a third metal film 137 filling the first and second openings 135a and 135b is deposited on the interlayer insulating film 131. In this case, the third metal layer 137 may be formed using a sputtering process, a chemical vapor deposition process, an atomic layer deposition (ALD) process, an electron beam deposition process, a pulsed laser deposition (PLD) process, or the like. . In addition, the third metal layer 137 may be formed using tungsten (W), aluminum (Al), titanium, tantalum, copper, tungsten nitride, aluminum nitride, titanium nitride, titanium aluminum nitride, tantalum nitride, or the like. have. In the embodiment of the present invention, the third metal film 137 is formed by using tungsten (W).

Next, as shown in FIG. 2P, the third metal film 137 is planarized through a chemical mechanical polishing (CMP) process, thereby forming first and second holes in the first and second openings 135a and 135b. Plugs 137a and 137b are formed, respectively. In this case, each of the first and second plugs 137a and 137b is connected to the lower electrode 105a and the upper electrode 109a, respectively.

Subsequently, as illustrated in FIG. 2Q, a fourth metal film 139 and an antireflection film 141 are sequentially deposited on the interlayer insulating film 131 including the first and second plugs 137a and 137b, and then the reflection is performed. A fourth photosensitive film (not shown) is coated on the prevention film 141.

Next, although not shown in the drawing, the fourth photoresist film (not shown) is exposed and developed through a photolithography process using a mask (not shown), and then patterned to form a fourth photoresist pattern 143.

Subsequently, as shown in FIG. 2R, the anti-reflection film 141 and the fourth metal film 139 are sequentially etched using the fourth photoresist pattern 143 as a blocking film, so that the first and second plugs 137a, A wiring forming process is formed by forming first and second pads 139a and 139b and first and second anti-reflection film patterns 141a and 141b respectively connected to the lower electrode 105a and the upper electrode 109a through 137b. To complete.

As described above, according to the present invention, the MIM capacitor is isolated from the external environment and protected from various defects, thereby obtaining good leakage current characteristics.

In addition, according to the present invention, it is possible to secure good via resistance since the insulating film remaining in the spacer etching step of the M capacitor is not affected by the subsequent process.

In addition, according to the present invention, SiON deposited on the metal layer buffers an etch target at the time of via etching, thereby preventing degradation of breakdown voltage characteristics of the MM capacitor.

In addition, according to the present invention, the horizontal insulating film (or width) of the dielectric film is formed longer than the upper metal length (or width) formed on the dielectric film through the spacer insulating film forming process. This is because the width of the dielectric film is wider than that of the upper electrode, thereby separating the upper electrode and the lower electrode well, thereby helping to suppress leakage. If the dielectric film and the upper electrode have the same width, there is a possibility that leakage occurs due to an electric field along the side surface because the distance between the upper electrode and the lower electrode is short. However, if the width of the dielectric film is large, as in the present invention, such a problem can be prevented.

Therefore, when using the M capacitor manufacturing process according to the present invention, it has very excellent characteristics in terms of reliability, such as breakdown voltage and defect density.

As described above, the present invention is not limited or limited to the above embodiments, and those skilled in the art may implement the present invention in various other forms without departing from the technical spirit of the present invention. There will be. In other words, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, and embodiments of the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Does not. It is not to be limited by the embodiments described herein, it should be understood to include all modifications, equivalents, or substitutes included in the spirit and scope of the present invention.

In addition, terms such as first and second may be used to describe various components, but such components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from other components. However, for example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "include" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features It will be understood that it does not exclude in advance the possibility of the presence or addition of numbers, steps, operations, components, parts or combinations thereof.

  Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries are to be interpreted as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined in this application. .

100: MM capacitor 101: substrate
103: metal wiring film 103a: metal wiring
105: first metal film 105a: lower electrode
107: dielectric film 107a: dielectric film protrusion (first region)
109: second metal film 109a: upper electrode
111: hard mask insulating film 111a: hard mask
113: first photosensitive film 113a: first photosensitive film pattern
120: first mask 121: spacer insulating film
121a: spacer 123: buffer insulating film
125: second photosensitive film 125a: second photosensitive film pattern
130: second mask 131: interlayer insulating film
133: third photosensitive film pattern 135a, 135b: first and second openings
137: third metal film 137a, 137b: first, second plug
139: fourth metal film 139a, 139b: first and second pads
141: antireflection film 141a, 141b: first and second antireflection film pattern
143: fourth photosensitive film pattern

Claims (33)

A lower electrode formed on the substrate;
A dielectric film formed on the lower electrode and configured of a first region and a second region having different thicknesses;
An upper electrode formed on the second zero of the dielectric film;
A hard mask formed on the upper electrode; And
And a spacer formed on side surfaces of the hard mask, the upper electrode, and the dielectric layer. The M capacitor of claim 1, wherein the first region of the dielectric layer under the spacer has a thickness thinner than the second region of the dielectric layer under the upper electrode. The M capacitor of claim 1, wherein a buffer insulating layer is formed on upper surfaces of the hard mask, the spacer, and the lower electrode. The method of claim 1, wherein the dielectric layer is _{SiN, SiO 2, Al 2 O} 3, HfO, Ta 2 O 5, SrTiO 3, CaTiO 3, LaAlO 3, BaZrO 3, BaZrTiO 3, SrZrTiO 3, HfO 2 / Al 2 O _3. A M capacitor comprising at least one of an insulating material group including any one or more selected from the group consisting of a laminated structure of _{3 and} a laminate structure in which an HfO ₂ / Al ₂ O ₃ layer is repeated. The M capacitor of claim 1, wherein a bottom surface of the spacer is in contact with a first region of the dielectric layer, and a side surface of the spacer is in contact with the upper electrode and a second region of the dielectric layer. The M capacitor of claim 3, wherein the buffer insulating layer comprises at least one of a group consisting of an inorganic SiON and an organic BARC. The semiconductor device of claim 1, wherein the hard mask and the spacer comprise silicon oxide based on SiO ₂ , SiC, FSG, and USG; MN capacitor, characterized in that it comprises any one or more of the group consisting of nitride series containing SiN, SiON. A lower electrode and an upper electrode formed on the substrate;
A dielectric film having a high dielectric constant formed between the lower electrode and the upper electrode;
A first passivation layer surrounding the upper electrode side surface and the upper surface; And
And a second passivation layer surrounding the sidewalls of the dielectric layer and the passivation layer.
The width of the dielectric layer is greater than the width of the upper electrode,
The first protective layer and the second protective layer is MM capacitor, characterized in that made of a material having a different etching rate. The method of claim 8, wherein the dielectric layer is at least one of an insulating material group consisting of a laminate structure of Al ₂ O ₃ , HfO, HfO ₂ / Al ₂ O ₃ layer, a laminate structure of HfO ₂ / Al ₂ O ₃ layer is repeated. MCM capacitor comprising a. The method of claim 8, wherein the first protective layer comprises: a silicon oxide series including SiO ₂ , SiC, FSG, and USG; MN capacitor, characterized in that it comprises any one or more of the group consisting of nitride series containing SiN, SiON. The M capacitor of claim 8, wherein the second passivation layer comprises at least one of a group consisting of an inorganic SiON and an organic BARC. Forming a lower electrode on the substrate;
Forming a dielectric film having a first region and a second region having different thicknesses on the lower electrode;
Forming an upper electrode and a hard mask on the second region of the dielectric layer; And
Forming a spacer on the side of the hard mask, the upper electrode and the dielectric film; MAM capacitor manufacturing method comprising a. The method of claim 12, wherein the forming of the upper electrode and the hard mask comprises:
Sequentially forming a metal film and an insulating film on the dielectric film;
Forming a photoresist pattern on the insulating film;
And forming a hard mask and an upper electrode by patterning the insulating film and the metal film using the photoresist pattern as a blocking film. The method of claim 13, wherein in the patterning of the insulating film and the metal film, a portion of a thickness of the first region of the dielectric film under the metal film is also etched together. The method of claim 14, wherein the thickness of the first region of the etched and remaining dielectric film is 50 ~ 100 ～. The method of claim 14, wherein forming the spacer,
Forming a spacer insulating layer on a first region of the dielectric layer in which a portion of the thickness including the hard mask and the upper electrode is etched;
And etching the entire surface of the spacer insulating layer to form a spacer on side surfaces of the hard mask, the upper electrode, and the dielectric layer. The method of claim 16, wherein in the entire surface etching of the spacer insulating layer, the first region of the dielectric layer in the region excluding the spacer is also removed. The method of claim 16, wherein the lower surface of the spacer is in contact with the first region of the dielectric layer, and the side surface of the spacer is in contact with the second region of the hard mask, the upper electrode, and the dielectric layer. . 19. The method of claim 18, wherein the thickness of the first region of the dielectric film in contact with the lower surface of the spacer is thinner than the thickness of the second region of the dielectric film in contact with the upper electrode. The method of claim 12, wherein forming the lower electrode comprises:
Forming a metal film for forming a lower electrode on the substrate;
Sequentially forming a dielectric film, an upper electrode, and a hard mask on the metal film;
Forming spacers on side surfaces of the dielectric layer, the upper electrode, and the hard mask;
Forming a buffer insulating layer on the metal layer, the spacer, and the hard mask; And
And selectively patterning the buffer insulating layer and the metal layer to form a lower electrode. The method of claim 12, wherein the dielectric layer is _{SiN, SiO 2, Al 2 O} 3, HfO, Ta 2 O 5, SrTiO 3, CaTiO 3, LaAlO 3, BaZrO 3, BaZrTiO 3, SrZrTiO 3, HfO 2 / Al 2 O _3. A method of manufacturing an M capacitor comprising at least one of an insulating material group including a laminate structure of _{3 and} a laminate structure in which an HfO ₂ / Al ₂ O ₃ layer is repeated. The method of claim 12, wherein the hard mask and the spacer are selected from the group consisting of a silicon oxide series including BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, and HDP-CVD, and a nitride series including SiN and SiON. MCM capacitor manufacturing method comprising any one or more. The method of claim 20, wherein the buffer insulating layer comprises at least one of a group consisting of an inorganic SiON and an organic BARC. The method of claim 13, wherein the forming of the hard mask and the upper electrode by patterning the insulating film and the metal film comprises using a gas of CF ₄ / CH _x F _y / O ₂ / N ₂ / Ar for etching the hard mask. Cl ₂ / BCl ₃ is used for etching the metal film, and M 2 capacitor manufacturing method characterized in that using N ₂ or Ar as an additive gas for etching profile control. Forming a first metal film on the substrate;
Sequentially stacking a dielectric film, a second metal film, and a hard mask cutting film on the first metal film;
Selectively patterning the hard mask insulating layer, the second metal layer, and the dielectric layer to form a dielectric layer pattern including a hard mask, an upper electrode, and first and second regions having different thicknesses;
Forming a spacer insulating film on an entire surface of the substrate including the hard mask, the upper electrode, and the first region of the dielectric film;
Etching the entire spacer insulating film to form spacers on side surfaces of the first and second regions of the hard mask, the upper electrode, and the dielectric film;
Forming a buffer insulating layer on the spacer, the hard mask, and the first metal layer; And
And forming a lower electrode by patterning the buffer insulating layer and the first metal layer. The method of claim 25, wherein in the patterning of the hard mask insulating layer and the second metal layer, a portion of a thickness of the first region of the dielectric layer under the second metal layer is also etched. The method of claim 26, wherein the thickness of the first region of the etched and remaining dielectric film is 50 ~ 100 ～. 27. The method of claim 25, wherein in the entire surface etching step of the spacer insulating film, the first region of the dielectric film in the region excluding the spacer is also removed. 27. The M capacitor of claim 25, wherein a lower surface of the spacer contacts the first region of the dielectric layer, and a side surface of the spacer contacts the side surfaces of the hard mask, the upper electrode, and the second region of the dielectric layer. Manufacturing method. 30. The method of claim 29, wherein the thickness of the first region of the dielectric layer in contact with the lower surface of the spacer is thinner than the thickness of the second region of the dielectric layer in contact with the upper electrode. 27. The method of claim 25, wherein the hard mask insulating film and the spacer insulating film is made of a silicon oxide series including BPSG, PSG, USG, SOG, FOX, TEOS, PE-TEOS, HDP-CVD, a nitride series including SiN and SiON MM capacitor manufacturing method comprising any one or more of the group. 27. The method of claim 25, wherein the buffer insulating film comprises at least one of the group consisting of SiON and organic BARC. The method of claim 25, wherein the hard mask insulating layer and the second metal layer are patterned to form a hard mask and an upper electrode. The hard mask etching method includes CF ₄ / CH _x F _y / O ₂ / N ₂ / Ar gas. And using Cl ₂ / BCl ₃ to etch the second metal film, and using N ₂ or Ar as an additive gas to control the etching profile.

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