CN103346081B - A kind of method of the undercutting of eliminating metal level-insulating barrier-metal level - Google Patents

A kind of method of the undercutting of eliminating metal level-insulating barrier-metal level Download PDF

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CN103346081B
CN103346081B CN201310217290.0A CN201310217290A CN103346081B CN 103346081 B CN103346081 B CN 103346081B CN 201310217290 A CN201310217290 A CN 201310217290A CN 103346081 B CN103346081 B CN 103346081B
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metallic plate
insulating barrier
metal level
etching
upper metallic
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CN103346081A (en
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胡友存
姬峰
李磊
陈玉文
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Shanghai Huali Microelectronics Corp
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Shanghai Huali Microelectronics Corp
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Abstract

A method of eliminating the undercutting of metal level-insulating barrier-metal level, comprising: deposit etching barrier layer; Metallic plate, insulating barrier under deposit, and upper metallic plate; Described upper metallic plate, insulating barrier, lower metallic plate are carried out to photoetching, etching, cleaning; To the further photoetching of described upper metallic plate, etching, cleaning; Described upper metallic plate is further carried out to high selectivity wet etching; Realize copper-connection. The present invention is in described wet etching, described upper metallic plate and described insulating barrier are had to high selectivity, can make the size of described upper metallic plate be equal to or slightly less than the size of described insulating barrier by the adjustment of time, the groove that the undercutting structure of eliminating insulation with this forms, prevent the electric leakage between upper metallic plate and lower metallic plate, increase breakdown voltage, and then improved the reliability between upper metallic plate and lower metallic plate.

Description

A kind of method of the undercutting of eliminating metal level-insulating barrier-metal level
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of eliminate metal level-insulating barrier-metal level itThe method of undercutting.
Background technology
Along with the continuous progress of semiconductor integrated circuit manufacturing technology, when constantly promoting, performance also followsDevice miniaturization, microminiaturized process. More and more advanced processing procedure, requires in as far as possible little regionInside realize device as much as possible, obtain high as far as possible performance. Capacitor is important in integrated circuitComponent units, is widely used in memory, microwave, and radio frequency, smart card, in the chips such as high pressure and filtering.
The most frequently used capacitance structure is the capacity plate antenna model of single-layer capacitor metal-insulator-metal at present.For example, a kind of at present typical capacitor arrangement is by three of copper metal layer-silicon nitride medium layer-Tan metal levelMingzhi's structure. The selection of metal level has multiple material optional, as copper, and aluminium, tantalum, titanium and alloy thereof etc.And dielectric insulation layer also has the material of multiple differing dielectric constant optional.
Significantly, in order to obtain higher unit area capacitance density, certainly will bring metal by traditional handicraftThe undercutting of insulating barrier in layer-insulating barrier-metal level, causes reliability of technology to reduce.
Therefore the problem existing for prior art, this case designer relies on the industry experience for many years of being engaged in,Active research improvement, so there has been the side of a kind of undercutting of eliminating metal level-insulating barrier-metal level of the present inventionMethod.
Summary of the invention
The present invention be directed in prior art, traditional handicraft certainly will be brought in metal level-insulating barrier-metal level exhaustedThe undercutting of edge layer, causes the defects such as reliability of technology reduction that a kind of metal level-insulating barrier-metal level of eliminating is providedThe method of undercutting.
In order to address the above problem, the invention provides a kind of undercutting of eliminating metal level-insulating barrier-metal levelMethod, described method comprises:
Execution step S1: carry out cmp to thering is surface on the substrate that described metallic copper fills,And there is deposit etching barrier layer in surface on the substrate that described metallic copper fills described;
Execution step S2: metal under the side that differs from described substrate of described etching barrier layer successively depositPlate, insulating barrier, and upper metallic plate;
Execution step S3: described upper metallic plate, insulating barrier, lower metallic plate are carried out to photoetching, etching, clearWash, until expose described etching barrier layer;
Execution step S4: to the further photoetching of described upper metallic plate, etching, cleaning;
Execution step S5: described upper metallic plate is further carried out to wet etching, right in described wet etchingDescribed upper metallic plate and described insulating barrier have high selectivity, after described wet etching, and described upper goldThe size that belongs to plate is equal to or less than the size of described insulating barrier;
Execution step S6: realize described metallic copper, upper metallic plate, the follow-up copper-connection of lower metallic plate.
Alternatively, described etching barrier layer is one of them of silicon nitride or carborundum.
Alternatively, described upper metallic plate, insulating barrier and described lower metallic plate are Spatial Overlap.
In sum, the present invention eliminates the method for the undercutting of metal level-insulating barrier-metal level, in described wet methodIn etching, described upper metallic plate and described insulating barrier are had to high selectivity, can by the adjustment of timeMake the size of described upper metallic plate to be equal to or slightly less than the size of described insulating barrier, eliminate insulation with thisThe groove that undercutting structure forms, has prevented the electric leakage between upper metallic plate and lower metallic plate, has increased and has puncturedVoltage, and then improve the reliability between upper metallic plate and lower metallic plate.
Brief description of the drawings
Figure 1 shows that the present invention eliminates the flow chart of the method for the undercutting of metal level-insulating barrier-metal level;
Fig. 2~Figure 7 shows that the present invention eliminates the technique of the method for the undercutting of metal level-insulating barrier-metal levelSchematic flow sheet.
Detailed description of the invention
By describe in detail the invention technology contents, structural feature, reached object and effect, underFace is in connection with embodiment and coordinate accompanying drawing to be described in detail.
Refer to Fig. 1, Figure 1 shows that the present invention a kind of undercutting of eliminating metal level-insulating barrier-metal levelThe flow chart of method. The method of the undercutting of described elimination metal level-insulating barrier-metal level comprises the following steps,
Execution step S1: carry out cmp to thering is surface on the substrate that described metallic copper fills,And there is deposit etching barrier layer in surface on the substrate that described metallic copper fills described;
Execution step S2: metal under the side that differs from described substrate of described etching barrier layer successively depositPlate, insulating barrier, and upper metallic plate;
Execution step S3: described upper metallic plate, insulating barrier, lower metallic plate are carried out to photoetching, etching, clearWash, until expose described etching barrier layer;
Execution step S4: to the further photoetching of described upper metallic plate, etching, cleaning;
Execution step S5: described upper metallic plate is further carried out to wet etching, right in described wet etchingDescribed upper metallic plate and described insulating barrier have high selectivity, after described wet etching, and described upper goldThe size that belongs to plate is equal to or slightly less than the size of described insulating barrier;
Execution step S6: realize described metallic copper, upper metallic plate, the follow-up copper-connection of lower metallic plate.
Refer to Fig. 2~Fig. 7, a kind of metal level-insulating barrier-Jin that eliminates of Fig. 2~Figure 7 shows that the present inventionBelong to the process flow diagram of the method for the undercutting of layer. The undercutting of described elimination metal level-insulating barrier-metal levelMethod, comprising:
Execution step S1: carry out chemical machine to thering is surface 21 on the substrate 2 that described metallic copper 1 fillsTool grinds, and has surperficial 21 place's deposit etchings resistances on the substrate 2 that described metallic copper 1 fills describedGear layer 3; Nonrestrictive enumerating, described etching barrier layer 3 is one of them of silicon nitride or carborundum.
Execution step S2: under a side of the described substrate 2 of differing from of described etching barrier layer 3 successively depositMetallic plate 4, insulating barrier 5, and upper metallic plate 6; Described upper metallic plate 6, insulating barrier 5 and described underMetallic plate 7 is Spatial Overlap;
Execution step S3: to described upper metallic plate 6, insulating barrier 5, lower metallic plate 4 carry out photoetching, etching,Clean, until expose described etching barrier layer 3;
Execution step S4: to the further photoetching of described upper metallic plate 6, etching, cleaning; To on describedIn the photoetching of metallic plate 6, etching process, on described between metallic plate 6 and described lower metallic plate 4Insulating barrier 5 be undercutting structure 51;
Execution step S5: described upper metallic plate 6 is further carried out to wet etching, in described wet etchingDescribed upper metallic plate 6 and described insulating barrier 5 are had to high selectivity, particularly, carve through described wet methodAfter erosion, the lateral dimensions of described upper metallic plate 6 diminishes, and the size of insulating barrier 5 is substantially constant.
As those skilled in the art, hold intelligibly, in described wet etching, by the timeAdjustment can make the size of described upper metallic plate 6 be equal to or slightly less than the size of described insulating barrier 5, withThis eliminates the groove that insulation undercutting structure 51 of 5 forms, prevented upper metallic plate 6 and lower metallic plate 4 itBetween electric leakage, increased breakdown voltage, and then improved reliable between upper metallic plate 6 and lower metallic plate 4Property.
Execution step S6: realize described metallic copper 1, upper metallic plate 6, the follow-up copper-connection of lower metallic plate 4.
In sum, the present invention eliminates the method for the undercutting of metal level-insulating barrier-metal level, in described wet methodIn etching, described upper metallic plate and described insulating barrier are had to high selectivity, can by the adjustment of timeMake the size of described upper metallic plate to be equal to or slightly less than the size of described insulating barrier, eliminate insulation with thisThe groove that undercutting structure forms, has prevented the electric leakage between upper metallic plate and lower metallic plate, has increased and has puncturedVoltage, and then improve the reliability between upper metallic plate and lower metallic plate.

Claims (3)

1. a method of eliminating the undercutting of metal level-insulating barrier-metal level, is characterized in that, described method bagDraw together:
Execution step S1: to have metallic copper fill substrate on surface carry out cmp, andDeposit etching barrier layer in surface on the described substrate with described metallic copper filling;
Execution step S2: under the side that differs from described substrate of described etching barrier layer successively deposit metallic plate,Insulating barrier, and upper metallic plate;
Execution step S3: described upper metallic plate, insulating barrier, lower metallic plate are carried out to photoetching, etching, cleaning,Until expose described etching barrier layer;
Execution step S4: to the further photoetching of described upper metallic plate, etching, cleaning;
Execution step S5: described upper metallic plate is further carried out to wet etching, in described wet etching to instituteState metallic plate and described insulating barrier has high selectivity, after described wet etching, described upper metallic plateSize be equal to or less than the size of described insulating barrier;
Execution step S6: realize described metallic copper, upper metallic plate, the follow-up copper-connection of lower metallic plate.
2. the method for the undercutting of elimination metal level-insulating barrier-metal level as claimed in claim 1, its feature existsIn, described etching barrier layer is one of them of silicon nitride or carborundum.
3. the method for the undercutting of elimination metal level-insulating barrier-metal level as claimed in claim 1, its feature existsIn, described upper metallic plate, insulating barrier and described lower metallic plate are Spatial Overlap.
CN201310217290.0A 2013-06-03 2013-06-03 A kind of method of the undercutting of eliminating metal level-insulating barrier-metal level Active CN103346081B (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339869A (en) * 2010-07-16 2012-02-01 美格纳半导体有限公司 Semiconductor device with MIM capacitor and method for manufacturing the same
CN102420104A (en) * 2011-06-07 2012-04-18 上海华力微电子有限公司 Manufacturing method of MIM (Metal-Insulator-Metal) capacitor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4947849B2 (en) * 2001-05-30 2012-06-06 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6576526B2 (en) * 2001-07-09 2003-06-10 Chartered Semiconductor Manufacturing Ltd. Darc layer for MIM process integration

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102339869A (en) * 2010-07-16 2012-02-01 美格纳半导体有限公司 Semiconductor device with MIM capacitor and method for manufacturing the same
CN102420104A (en) * 2011-06-07 2012-04-18 上海华力微电子有限公司 Manufacturing method of MIM (Metal-Insulator-Metal) capacitor

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