WO2014161461A1 - Method for improving dielectric laying in semiconductor wafer capacitor manufacturing process - Google Patents
Method for improving dielectric laying in semiconductor wafer capacitor manufacturing process Download PDFInfo
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- WO2014161461A1 WO2014161461A1 PCT/CN2014/074494 CN2014074494W WO2014161461A1 WO 2014161461 A1 WO2014161461 A1 WO 2014161461A1 CN 2014074494 W CN2014074494 W CN 2014074494W WO 2014161461 A1 WO2014161461 A1 WO 2014161461A1
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- titanium nitride
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- semiconductor wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer
Definitions
- the invention relates to the field of semi-conductive processes, in particular to an improved semiconductor wafer capacitor process The method of media layering.
- Capacitance is often used in an integrated circuit, but in the production process of a semiconductor wafer. Forming a capacitor on a bulk silicon wafer usually requires a capacitor for the upper electrode plate, the lower electrode plate, and the upper electrode plate. The dielectric layer between the lower electrode plate and the lower electrode plate. If the bond between the lower electrode plate of the capacitor and the medium is not tight, Even the stratification situation, which will be fatal to the function of the capacitor and the overall chip yield. Killing can even lead to the failure of components.
- the stratification of the capacitor often occurs, and the capacitor layer is previously generated.
- the main suspect is a washing process behind the ALCU process, which is suspected to be caused by water residue.
- the quality and the lower electrode plate are layered, but after the piece test, it is confirmed that even if it is not washed, stratification will occur. happening.
- the present invention provides a method for improving dielectric layering in a semiconductor wafer capacitor process.
- the method comprises the steps of: depositing a capacitor under the silicon plate on the silicon wafer, and then under the capacitor Depositing a dielectric layer on the electrode plate, depositing a titanium nitride buffer layer on the dielectric layer of the capacitor, and finally depositing nitrogen A capacitor upper electrode plate is deposited on the titanium buffer layer.
- the structure of the metal layer of the upper electrode plate of the capacitor is aluminum, copper and gold superposed on each other from bottom to top.
- a genus layer and a titanium nitride layer the metal layer of the capacitor lower electrode plate is a titanium alloy stacked on top of each other a genus layer, a titanium nitride layer, an aluminum-copper metal layer, a titanium metal layer, a titanium nitride layer, and the dielectric layer is a silicon nitride layer.
- the titanium nitride buffer layer is formed on the dielectric layer by a physical vapor deposition process.
- the gas used in the process of physically vapor-depositing titanium nitride is argon and nitrogen.
- the target of the physical vapor deposition titanium nitride is a titanium metal target.
- the physical vapor deposition titanium nitride process temperature is 300 degrees Celsius.
- the pressure of the physical vapor deposition titanium nitride process is 4200-4800 megatorr.
- the titanium nitride buffer layer is deposited to have a thickness of 285-315 angstroms.
- the method for solving the dielectric layering in the semiconductor wafer capacitor process of the present invention is in the gold of the capacitor upper electrode plate A layer of titanium nitride buffer layer is deposited between the genus layer and the dielectric layer as a stress buffer layer, so that the dielectric layer is applied up and down The balance of forces can essentially improve the stratification of the capacitor.
- FIG. 1 is a schematic diagram showing the stress distribution of a dielectric layer of a conventional capacitor.
- FIG 3 is a schematic illustration of the stress distribution of a dielectric layer of a capacitor fabricated by the method of the present invention.
- one embodiment or “an embodiment” as used herein refers to at least one of the embodiments of the present invention. A particular feature, structure, or characteristic in the present mode. In a different place in this manual, "in a real The examples are not all referring to the same embodiment, nor are they individually or selectively interact with other embodiments. Examples of rejection.
- Capacitor structures are often referred to as MIM structures in semiconductor manufacturing processes:
- metal layer 1 that is, the lower electrode plate of the capacitor, which is usually constructed by The structure of Ti+TiN+AlCu+Ti+TiN, that is, when forming a capacitor on the lower electrode plate on a silicon wafer, is actually Forming a titanium metal layer, a titanium nitride layer, an aluminum-copper metal layer, a titanium metal layer, and nitrogen from bottom to top on the silicon wafer
- the titanium layer, that is, the lower electrode plate of the capacitor is actually formed by stacking multiple layers, specifically for each layer. The thickness varies according to the actual production process.
- Insulator a dielectric layer of a capacitor, which is usually made of an insulating material such as silicon nitride or silicon oxide. Medium layer.
- M Metal 2, metal layer 2, that is, the upper electrode plate of the capacitor, which usually adopts the structure of AlCu+TiN, That is, the upper electrode plate of the capacitor is formed by superposing an aluminum-copper metal layer and a titanium nitride layer in this order from bottom to top.
- the layering of the capacitor does not occur after the formation of the lower electrode plate and the dielectric layer of the capacitor, and the layering of the capacitor It is often the case that the upper electrode plate of the capacitor is grown after the metal is completed, and the TEM is used. (Transmission electron microscope) analysis of the capacitor layered sample, found that the layering Is the aluminum-copper metal layer that occurs in the dielectric layer itself, and the dielectric layer and the capacitor upper electrode plate, and the medium The adhesion between the layer and the titanium nitride layer of the lower electrode plate of the capacitor is good. As shown in Figure 1, after analysis, it was discovered by In the existing capacitor structure, the aluminum-copper metal layer above the dielectric layer is a normal stress and is located under the dielectric layer. The square titanium nitride is a negative stress, and the dielectric layer sandwiched between is a negative stress, and the dielectric layer sandwiched in the middle Layering is caused by the difference in stress in the opposite direction between the upper and lower layers.
- the present invention proposes between the dielectric layer and the metal layer of the upper electrode.
- FIG. 3 there is shown a flow chart for fabricating a capacitor in accordance with the method of the present invention.
- Technicians should be aware that every layer of material formed on a silicon wafer in a semiconductor process may undergo oxidation, Conventional steps such as photolithography, etching, cleaning, etc., to highlight the substantial steps of the present invention, in the semiconductor process Conventional steps of oxidation, photolithography, etching, cleaning, etc.
- the present invention is omitted in the following steps, but not The present invention does not have these steps.
- Step S1 depositing a capacitor lower electrode plate on the silicon wafer.
- the structure of the lower electrode plate is Ti+TiN+AlCu+Ti+TiN is produced by sequentially depositing a titanium metal layer and a titanium nitride layer on the silicon wafer.
- Physical vapor deposition can be used for the deposition of metal layers. The method is formed, and the present invention will not be described in detail for each step of deposition.
- Step S2 depositing a dielectric layer on the lower electrode plate of the capacitor.
- the dielectric layer is silicon nitride. Medium layer It is formed by chemical vapor deposition.
- the magnetically controlled direct current in the chamber of the physical vapor deposition dissociates the Ar in the cavity into Ar+, bombards the titanium nitride target, and removes the atom from the target.
- the atom reaches the surface of the silicon wafer by gravity, and is deposited according to the film growth mechanism. Film formation.
- the physical vapor deposition titanium nitride process temperature is 300 degrees Celsius.
- the pressure of the physical vapor deposition titanium nitride process is 4200-4800 megatorometers (MT).
- the thickness of the finally formed titanium nitride buffer layer is 285-315 angstroms .
- the silicon wafer starts from the bottom to the top (Ti+TiN+AlCu+Ti+TiN)+SiN+TiN+(AlCu+TiN) Structure, that is, the entire capacitor from bottom to top is titanium metal layer, titanium nitride layer, aluminum copper metal layer, titanium metal a layer, a titanium nitride layer, a silicon nitride layer, a titanium nitride layer, an aluminum-copper metal layer, and a titanium nitride layer.
- test 1 is that the existing lower electrode plate is (Ti + TiN + AlCu + Ti + TiN) structure, The dielectric layer is SiN and the upper electrode is a capacitor of (AlCu+TiN) structure.
- Test 2 is a method using the present invention
- the capacitance that is, the structure of the capacitor, is such that the lower electrode is (Ti+TiN+AlCu+Ti+TiN) and the dielectric layer is SiN.
- the upper electrode is of an (AlCu+TiN) structure, and a TiN buffer layer is disposed between the dielectric layer and the upper electrode.
- Test 3 is a structure in which the lower electrode plate is (Ti+TiN+AlCu+Ti+TiN), the dielectric layer is SiN, and the upper electrode is The capacitance of the (AlCu+TiN) structure, but the stress reduction treatment of the dielectric layer.
- the test results are as follows:
- test 1 and test 3 still have stratification. None of the wafers produced by the method of the present invention have delamination, demonstrating that the method of the present invention is very good Solve the problem of media stratification in the semiconductor wafer capacitor process.
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Abstract
Provided in the present invention is a method for improving dielectric layering in a semiconductor wafer capacitor manufacturing process, the method comprising: depositing a lower electrode plate of a capacitor on a silicon chip at first, then depositing a dielectric layer on the lower electrode plate of the capacitor, depositing a titanium nitride buffer layer on the dielectric layer of the capacitor, and finally, depositing an upper electrode plate of the capacitor on the titanium nitride buffer layer. According to the method of the present invention, the titanium nitride buffer layer serving as a stress buffer layer is deposited between a metal layer of the upper electrode plate and the dielectric layer on the capacitor, thus the upper and lower stresses of the dielectric layer are balanced, and the condition of dielectric layering can be substantially improved.
Description
本发明是关于半导制程领域，特别是关于一种改善半导体晶圆电容制程中
介质分层的方法。
The invention relates to the field of semi-conductive processes, in particular to an improved semiconductor wafer capacitor process
The method of media layering.
通常一个集成电路中经常会用到电容，而在半导体晶圆的生产过程中在一
块硅片上形成电容通常需要制作电容的上电极板、下电极板以及位于上电极板
和下电极板之间的介质层。如果在电容的下电极板和介质之间产生粘合不紧密，
甚至产生分层的情况，这对电容器的功能以及整体芯片的良率将会产生致命的
杀伤，甚至可以直接导致元器件的失效。
Capacitance is often used in an integrated circuit, but in the production process of a semiconductor wafer.
Forming a capacitor on a bulk silicon wafer usually requires a capacitor for the upper electrode plate, the lower electrode plate, and the upper electrode plate.
The dielectric layer between the lower electrode plate and the lower electrode plate. If the bond between the lower electrode plate of the capacitor and the medium is not tight,
Even the stratification situation, which will be fatal to the function of the capacitor and the overall chip yield.
Killing can even lead to the failure of components.
现有的电容的制造中，经常会发生电容的分层的情况，之前在发生电容层
次分层时，主要怀疑是ALCU工艺后面的一道水洗工艺，怀疑为水残留导致的介
质和下电极板分层，但经过分片试验后确认，即使不做水洗，也会出现分层的
情况。
In the manufacture of existing capacitors, the stratification of the capacitor often occurs, and the capacitor layer is previously generated.
In the case of sub-stratification, the main suspect is a washing process behind the ALCU process, which is suspected to be caused by water residue.
The quality and the lower electrode plate are layered, but after the piece test, it is confirmed that even if it is not washed, stratification will occur.
Happening.
后来也怀疑是电容的下电极板制作工艺和介质制作时有油污掉落在圆片表
面导致的分层，但是没有共同机台，并且检查机台后未发现异常。所以电容分
层的问题形成现有技术的长期困扰。
Later, it was suspected that the lower electrode plate fabrication process of the capacitor and the oil were dropped on the wafer table during the fabrication of the medium.
The delamination caused by the surface, but there is no common machine, and no abnormalities are found after checking the machine. So the capacitance is divided
The problem of layers forms a long-standing problem with the prior art.
【发明内容】
[Summary of the Invention]
本发明的目的在于提供一种解决半导体晶圆电容制程中介质分层的方法。
It is an object of the present invention to provide a method of addressing dielectric stratification in a semiconductor wafer capacitor process.
为达成前述目的，本发明一种改善半导体晶圆电容制程中介质分层的方法，
其在制造电容时包括如下步骤：先在硅片上沉积电容下电极板、然后在电容下
电极板上沉积介质层，再在电容的介质层上沉积一层氮化钛缓冲层、最后在氮
化钛缓冲层上沉积电容上电极板。
In order to achieve the foregoing object, the present invention provides a method for improving dielectric layering in a semiconductor wafer capacitor process.
When manufacturing the capacitor, the method comprises the steps of: depositing a capacitor under the silicon plate on the silicon wafer, and then under the capacitor
Depositing a dielectric layer on the electrode plate, depositing a titanium nitride buffer layer on the dielectric layer of the capacitor, and finally depositing nitrogen
A capacitor upper electrode plate is deposited on the titanium buffer layer.
进一步地，所述电容上电极板金属层的结构为自下而上相互叠加的铝铜金
属层和氮化钛层，所述电容下电极板金属层的结构为自下而上相互叠加的钛金
属层、氮化钛层、铝铜金属层、钛金属层、氮化钛层，所述介质层为氮化硅层。
Further, the structure of the metal layer of the upper electrode plate of the capacitor is aluminum, copper and gold superposed on each other from bottom to top.
a genus layer and a titanium nitride layer, the metal layer of the capacitor lower electrode plate is a titanium alloy stacked on top of each other
a genus layer, a titanium nitride layer, an aluminum-copper metal layer, a titanium metal layer, a titanium nitride layer, and the dielectric layer is a silicon nitride layer.
进一步地，所述氮化钛缓冲层是通过物理气相沉积工艺形成于介质层上。
Further, the titanium nitride buffer layer is formed on the dielectric layer by a physical vapor deposition process.
进一步地，所述物理气相沉积氮化钛的工艺采用的气体为氩和氮气。
Further, the gas used in the process of physically vapor-depositing titanium nitride is argon and nitrogen.
进一步地，所述物理气相沉积氮化钛的靶材为钛金属靶材。
Further, the target of the physical vapor deposition titanium nitride is a titanium metal target.
进一步地，所述物理气相沉积氮化钛工艺温度为300摄氏度。
Further, the physical vapor deposition titanium nitride process temperature is 300 degrees Celsius.
进一步地，所述物理气相沉积氮化钛工艺的压力为4200—4800兆托。
Further, the pressure of the physical vapor deposition titanium nitride process is 4200-4800 megatorr.
进一步地，所述氮化钛缓冲层沉积的厚度为285—315埃。
Further, the titanium nitride buffer layer is deposited to have a thickness of 285-315 angstroms.
本发明的解决半导体晶圆电容制程中介质分层的方法在电容上电极板的金
属层与介质层之间沉积一层氮化钛缓冲层作为应力缓冲层，使得介质层上下应
力达到平衡，能够从本质上改善电容分层的情况。
The method for solving the dielectric layering in the semiconductor wafer capacitor process of the present invention is in the gold of the capacitor upper electrode plate
A layer of titanium nitride buffer layer is deposited between the genus layer and the dielectric layer as a stress buffer layer, so that the dielectric layer is applied up and down
The balance of forces can essentially improve the stratification of the capacitor.
图1为现有的电容的介质层的应力分布示意图。
FIG. 1 is a schematic diagram showing the stress distribution of a dielectric layer of a conventional capacitor.
图2是本发明的方法的流程图。
2 is a flow chart of the method of the present invention.
图3是本发明的方法制造的电容的介质层的应力分布示意图。
3 is a schematic illustration of the stress distribution of a dielectric layer of a capacitor fabricated by the method of the present invention.
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实
现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实
施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相
排斥的实施例。
The term "one embodiment" or "an embodiment" as used herein refers to at least one of the embodiments of the present invention.
A particular feature, structure, or characteristic in the present mode. In a different place in this manual, "in a real
The examples are not all referring to the same embodiment, nor are they individually or selectively interact with other embodiments.
Examples of rejection.
电容结构在半导体生产流程中经常称之为MIM结构：
Capacitor structures are often referred to as MIM structures in semiconductor manufacturing processes:
M：Metal1，金属层1，即电容的下电极板，其通常采用的结构为
Ti+TiN+AlCu+Ti+TiN的结构，即在硅片上形成电容的下电极板上时，实际上是
在硅片上自下而上依次形成钛金属层、氮化钛层、铝铜金属层、钛金属层和氮
化钛层，也就是电容的下电极板实际上也是由多层叠加形成的，具体每一层的
厚度根据实际生产流程有所不同。
M: Metal1, metal layer 1, that is, the lower electrode plate of the capacitor, which is usually constructed by
The structure of Ti+TiN+AlCu+Ti+TiN, that is, when forming a capacitor on the lower electrode plate on a silicon wafer, is actually
Forming a titanium metal layer, a titanium nitride layer, an aluminum-copper metal layer, a titanium metal layer, and nitrogen from bottom to top on the silicon wafer
The titanium layer, that is, the lower electrode plate of the capacitor, is actually formed by stacking multiple layers, specifically for each layer.
The thickness varies according to the actual production process.
I：Insulator,电容的介质层，其通常采用氮化硅、氧化硅等绝缘材料作为
介质层。
I: Insulator, a dielectric layer of a capacitor, which is usually made of an insulating material such as silicon nitride or silicon oxide.
Medium layer.
M：Metal2，金属层2，即电容的上电极板，其通常采用AlCu+TiN的结构，
即电容的上电极板自下而上依次由铝铜金属层和氮化钛层叠加形成。
M: Metal 2, metal layer 2, that is, the upper electrode plate of the capacitor, which usually adopts the structure of AlCu+TiN,
That is, the upper electrode plate of the capacitor is formed by superposing an aluminum-copper metal layer and a titanium nitride layer in this order from bottom to top.
也就是整个电容实际上从硅片开始，由下而上依次是
（Ti+TiN+AlCu+Ti+TiN）+SiN+（AlCu+TiN）的结构。
That is, the entire capacitor actually starts from the silicon wafer, from bottom to top.
(Ti+TiN+AlCu+Ti+TiN)+SiN+(AlCu+TiN) structure.
在形成电容的下电极板和介质层之后并不会出现电容的分层，电容的分层
经常是电容的上电极板金属生长完成之后才出现分层，经过使用TEM
（Transmission electron microscope）分析电容分层的样本，发现该分层实
际上是发生在介质层本身，而介质层与电容上电极板的铝铜金属层，以及介质
层与电容下电极板的氮化钛层粘附性都很好。如图1所示，经过分析发现是由
于现有的电容结构中位于介质层上方的铝铜金属层是正应力，而位于介质层下
方的钛化氮是负应力，而夹在中间的介质层为负应力，夹在中间的介质层由于
受到上下两层反方向的应力差，所以才会出现分层。
The layering of the capacitor does not occur after the formation of the lower electrode plate and the dielectric layer of the capacitor, and the layering of the capacitor
It is often the case that the upper electrode plate of the capacitor is grown after the metal is completed, and the TEM is used.
(Transmission electron microscope) analysis of the capacitor layered sample, found that the layering
Is the aluminum-copper metal layer that occurs in the dielectric layer itself, and the dielectric layer and the capacitor upper electrode plate, and the medium
The adhesion between the layer and the titanium nitride layer of the lower electrode plate of the capacitor is good. As shown in Figure 1, after analysis, it was discovered by
In the existing capacitor structure, the aluminum-copper metal layer above the dielectric layer is a normal stress and is located under the dielectric layer.
The square titanium nitride is a negative stress, and the dielectric layer sandwiched between is a negative stress, and the dielectric layer sandwiched in the middle
Layering is caused by the difference in stress in the opposite direction between the upper and lower layers.
根据以上分析，如图2所示，本发明提出在介质层与上电极的金属层之间
设置一层负应力层，这样介质层上下两层的应力是相同方向的，就不会出现介
质层分层的情况。
According to the above analysis, as shown in FIG. 2, the present invention proposes between the dielectric layer and the metal layer of the upper electrode.
Set a layer of negative stress so that the stresses in the upper and lower layers of the dielectric layer are in the same direction.
The case of stratification of the layers.
请参阅图3所示，其显示根据本发明的方法制造电容的流程图。本领域的
技术人员应当知道，半导体制程中在硅片上每形成一层物质可能都会经历氧化、
光刻、蚀刻、清洗等常规步骤，为突出本发明的实质步骤，关于半导体制程中
的氧化、光刻、蚀刻、清洗等常规步骤本发明在下面的步骤中省略，但并不代
表本发明不具备这些步骤。
Referring to Figure 3, there is shown a flow chart for fabricating a capacitor in accordance with the method of the present invention. In the field
Technicians should be aware that every layer of material formed on a silicon wafer in a semiconductor process may undergo oxidation,
Conventional steps such as photolithography, etching, cleaning, etc., to highlight the substantial steps of the present invention, in the semiconductor process
Conventional steps of oxidation, photolithography, etching, cleaning, etc. The present invention is omitted in the following steps, but not
The present invention does not have these steps.
如图3所示，本发明的电容的制造方法包括：
As shown in FIG. 3, the manufacturing method of the capacitor of the present invention includes:
步骤S1：在硅片上沉积电容下电极板。其中下电极板的结构为
Ti+TiN+AlCu+Ti+TiN，其制造方法为在硅片上依次沉积钛金属层、氮化钛层、
铝铜金属层、钛金属层、氮化钛层。其中金属层的沉积可以采用物理气相沉积
的方法形成，本发明不再对沉积的每一步骤详细说明。
Step S1: depositing a capacitor lower electrode plate on the silicon wafer. The structure of the lower electrode plate is
Ti+TiN+AlCu+Ti+TiN is produced by sequentially depositing a titanium metal layer and a titanium nitride layer on the silicon wafer.
Aluminum-copper metal layer, titanium metal layer, titanium nitride layer. Physical vapor deposition can be used for the deposition of metal layers.
The method is formed, and the present invention will not be described in detail for each step of deposition.
步骤S2：在电容下电极板上沉积介质层。其中介质层为氮化硅。介质层可
以通过化学气相沉积的方式形成。
Step S2: depositing a dielectric layer on the lower electrode plate of the capacitor. The dielectric layer is silicon nitride. Medium layer
It is formed by chemical vapor deposition.
步骤S3：在电容的介质层上沉积一层氮化钛缓冲层。所述氮化钛缓冲层是
通过物理气相沉积工艺形成于电容上电极板金属层上。所谓物理气相沉积即利
用等离子体中的离子，对被溅镀物体电极（即：靶材）轰击，使靶面原子脱离
靶材运动到圆片表面沉积成膜。在本发明的实施例中所述物理气相沉积氮化钛
的工艺采用的气体为氩（Ar）和氮气。所述物理气相沉积氮化钛的靶材为钛金
属靶材。在进行物理气相沉积的设备腔体内磁控直流使腔体内的Ar离解为Ar+,
轰击氮化钛靶材,使原子脱离靶材,原子在重力作用下到达硅片表面,按照膜成
长机构淀积成膜。其中本发明的一个实施例中所述物理气相沉积氮化钛工艺温
度为300摄氏度。所述物理气相沉积氮化钛工艺的压力为4200—4800兆托（MT）。
最终形成的氮化钛缓冲层的厚度为285—315埃
。
Step S3: depositing a titanium nitride buffer layer on the dielectric layer of the capacitor. The titanium nitride buffer layer is formed on the metal layer of the upper electrode plate by a physical vapor deposition process. The so-called physical vapor deposition uses the ions in the plasma to bombard the electrode of the object to be sputtered (ie, the target), and the target surface atoms are separated from the target and moved to the surface of the wafer to deposit a film. The process for physically vapor-depositing titanium nitride in the embodiment of the present invention employs a gas of argon (Ar) and nitrogen. The target of the physical vapor deposition titanium nitride is a titanium metal target. The magnetically controlled direct current in the chamber of the physical vapor deposition dissociates the Ar in the cavity into Ar+, bombards the titanium nitride target, and removes the atom from the target. The atom reaches the surface of the silicon wafer by gravity, and is deposited according to the film growth mechanism. Film formation. In one embodiment of the invention, the physical vapor deposition titanium nitride process temperature is 300 degrees Celsius. The pressure of the physical vapor deposition titanium nitride process is 4200-4800 megatorometers (MT). The thickness of the finally formed titanium nitride buffer layer is 285-315 angstroms .
步骤S4：在氮化钛缓冲层上沉积电容上电极板。其中上电极的结构为
AlCu+TiN，即在前述氮化钛缓冲层上依次沉积铝铜金属层和氮化钛层。
Step S4: depositing a capacitor upper electrode plate on the titanium nitride buffer layer. The structure of the upper electrode is
AlCu+TiN, that is, an aluminum-copper metal layer and a titanium nitride layer are sequentially deposited on the aforementioned titanium nitride buffer layer.
至此，根据本发明的方法制造的电容即完成，等于本发明的电容的结构从
硅片开始，由下而上依次是（Ti+TiN+AlCu+Ti+TiN）+SiN+TiN+（AlCu+TiN）的
结构，即整个电容从下而上依次是钛金属层、氮化钛层、铝铜金属层、钛金属
层、氮化钛层、氮化硅层、氮化钛层、铝铜金属层、氮化钛层。
So far, the capacitor manufactured according to the method of the present invention is completed, which is equal to the structure of the capacitor of the present invention.
The silicon wafer starts from the bottom to the top (Ti+TiN+AlCu+Ti+TiN)+SiN+TiN+(AlCu+TiN)
Structure, that is, the entire capacitor from bottom to top is titanium metal layer, titanium nitride layer, aluminum copper metal layer, titanium metal
a layer, a titanium nitride layer, a silicon nitride layer, a titanium nitride layer, an aluminum-copper metal layer, and a titanium nitride layer.
请参阅下表所示，本发明对三组使用不同的制造方法制造的电容进行分层
测试分析，其中：测试1是现有的下电极板为（Ti+TiN+AlCu+Ti+TiN）结构，
介质层为SiN，上电极为（AlCu+TiN）结构的电容。测试2是采用本发明的方法
的电容，即电容的结构为下电极为（Ti+TiN+AlCu+Ti+TiN）结构，介质层为SiN，
上电极为（AlCu+TiN）结构，在介质层和上电极之间设置有一层TiN缓冲层。
测试3是下电极板为（Ti+TiN+AlCu+Ti+TiN）结构，介质层为SiN，上电极为
（AlCu+TiN）结构的电容，但对介质层进行降低应力处理。测试结果如下：
Referring to the table below, the present invention stratifies three sets of capacitors fabricated using different manufacturing methods.
Test analysis, wherein: test 1 is that the existing lower electrode plate is (Ti + TiN + AlCu + Ti + TiN) structure,
The dielectric layer is SiN and the upper electrode is a capacitor of (AlCu+TiN) structure. Test 2 is a method using the present invention
The capacitance, that is, the structure of the capacitor, is such that the lower electrode is (Ti+TiN+AlCu+Ti+TiN) and the dielectric layer is SiN.
The upper electrode is of an (AlCu+TiN) structure, and a TiN buffer layer is disposed between the dielectric layer and the upper electrode.
Test 3 is a structure in which the lower electrode plate is (Ti+TiN+AlCu+Ti+TiN), the dielectric layer is SiN, and the upper electrode is
The capacitance of the (AlCu+TiN) structure, but the stress reduction treatment of the dielectric layer. The test results are as follows:
经过三组测试的比对可以看出测试1和测试3仍然会有分层的情况，而采
用本发明方法制造的晶圆都没有存在分层的情况，证明本发明的方法能够很好
的解决半导体晶圆电容制程中介质分层的问题。
After comparing the three sets of tests, it can be seen that test 1 and test 3 still have stratification.
None of the wafers produced by the method of the present invention have delamination, demonstrating that the method of the present invention is very good
Solve the problem of media stratification in the semiconductor wafer capacitor process.
本发明的解决半导体晶圆电容制程中介质分层的方法在电容上电极板的金
属层与介质层之间沉积一层氮化钛缓冲层作为应力缓冲层，使得介质层上下应
力达到平衡，能够从本质上改善电容分层的情况。
The method for solving the dielectric layering in the semiconductor wafer capacitor process of the present invention is in the gold of the capacitor upper electrode plate
A layer of titanium nitride buffer layer is deposited between the genus layer and the dielectric layer as a stress buffer layer, so that the dielectric layer is applied up and down
The balance of forces can essentially improve the stratification of the capacitor.
上述说明已经充分揭露了本发明的具体实施方式。需要指出的是，熟悉该
领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权
利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具
体实施方式。
The above description has fully disclosed the specific embodiments of the present invention. It should be pointed out that familiar with the
Any changes made to the specific embodiments of the present invention by those skilled in the art will not depart from the scope of the present invention.
The scope of the request. Accordingly, the scope of the claims of the present invention is not limited to the foregoing
Body embodiment.
Claims (8)
- 一种改善半导体晶圆电容制程中介质分层的方法，其包括： A method of improving dielectric layering in a semiconductor wafer capacitor process, comprising:在硅片上沉积电容下电极板； Depositing a capacitor lower electrode plate on the silicon wafer;在电容下电极板上沉积介质层； Depositing a dielectric layer on the lower electrode plate of the capacitor;在电容的介质层上沉积一层氮化钛缓冲层；和 Depositing a layer of titanium nitride buffer layer on the dielectric layer of the capacitor;在氮化钛缓冲层上沉积电容上电极板。 A capacitor upper electrode plate is deposited on the titanium nitride buffer layer.
- 如权利要求1所述的改善半导体晶圆电容制程中介质分层的方法，其特 征在于：所述电容上电极板金属层的结构为自下而上相互叠加的铝铜金属层和 氮化钛层，所述电容下电极板金属层的结构为自下而上相互叠加的钛金属层、 氮化钛层、铝铜金属层、钛金属层、氮化钛层，所述介质层为氮化硅层。 The method for improving dielectric layering in a semiconductor wafer capacitor process according to claim 1 The structure of the metal layer of the upper electrode plate of the capacitor is an aluminum-copper metal layer superposed on each other from bottom to top and a titanium nitride layer, the metal layer of the capacitor lower electrode plate is a titanium metal layer superposed on each other from bottom to top, a titanium nitride layer, an aluminum-copper metal layer, a titanium metal layer, and a titanium nitride layer, wherein the dielectric layer is a silicon nitride layer.
- 如权利要求1所述的改善半导体晶圆电容制程中介质分层的方法，其特 征在于：所述氮化钛缓冲层是通过物理气相沉积工艺形成于介质层上。 The method for improving dielectric layering in a semiconductor wafer capacitor process according to claim 1 The titanium nitride buffer layer is formed on the dielectric layer by a physical vapor deposition process.
- 如权利要求3所述的改善半导体晶圆电容制程中介质分层的方法，其特 征在于：所述物理气相沉积氮化钛的工艺采用的气体为氩和氮气。 The method for improving dielectric layering in a semiconductor wafer capacitor process according to claim 3 The gas used in the process of physical vapor deposition of titanium nitride is argon and nitrogen.
- 如权利要求3所述的改善半导体晶圆电容制程中介质分层的方法，其特 征在于：所述物理气相沉积氮化钛的靶材为钛金属靶材。 The method for improving dielectric layering in a semiconductor wafer capacitor process according to claim 3 The target is that the target of the physical vapor deposition titanium nitride is a titanium metal target.
- 如权利要求3所述的改善半导体晶圆电容制程中介质分层的方法，其特 征在于：所述物理气相沉积氮化钛工艺温度为300摄氏度。 The method for improving dielectric layering in a semiconductor wafer capacitor process according to claim 3 The invention is that the physical vapor deposition titanium nitride process temperature is 300 degrees Celsius.
- 如权利要求3所述的改善半导体晶圆电容制程中介质分层的方法，其特 征在于：所述物理气相沉积氮化钛工艺的压力为4200—4800兆托。 The method for improving dielectric layering in a semiconductor wafer capacitor process according to claim 3 The invention is that the pressure of the physical vapor deposition titanium nitride process is 4200-4800 megaTorr.
- 如权利要求1所述的改善半导体晶圆电容制程中介质分层的方法，其特 征在于：所述氮化钛缓冲层沉积的厚度为285—315埃。 The method for improving dielectric layering in a semiconductor wafer capacitor process according to claim 1 The thickness of the titanium nitride buffer layer is 285-315 angstroms.
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| CN201310115731.6A CN103187244B (en) | 2013-04-03 | 2013-04-03 | A kind of method of improving the layering of semiconductor crystal wafer electric capacity processing procedure medium |
| CN201310115731.6 | 2013-04-03 |
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| CN109920729B (en) * | 2019-03-27 | 2022-12-02 | 合肥鑫晟光电科技有限公司 | Preparation method of display substrate and display device |
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