CN102386125B - Method for preparing semiconductor structure for detection by transmission electron microscope, and semiconductor structure - Google Patents
Method for preparing semiconductor structure for detection by transmission electron microscope, and semiconductor structure Download PDFInfo
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- CN102386125B CN102386125B CN201010274956.2A CN201010274956A CN102386125B CN 102386125 B CN102386125 B CN 102386125B CN 201010274956 A CN201010274956 A CN 201010274956A CN 102386125 B CN102386125 B CN 102386125B
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Abstract
The invention discloses a method for preparing a semiconductor structure for the detection by a transmission electron microscope, which comprises the steps of: providing a front-end device, and forming a dielectric material layer on the front-end device; depositing a barrier layer on the dielectric material layer; depositing a first seed crystal layer on the barrier layer; setting an interface layer on the first seed crystal layer; depositing a second seed crystal layer on the interface layer; and setting a filling layer on the second seed crystal layer. The invention further discloses a semiconductor structure for the detection by the transmission electron microscope. The method and the structure can be conveniently applicable to a copper interconnection technology when a semiconductor is manufactured, step coverage which is performed to the barrier layer and the seed crystal layers is detected by the transmission electron microscope, a through hole cannot be deformed when the transmission electron microscope is used for sampling, and the detecting image of the transmission electron microscope, which shows the step coverage of the barrier layer and the seed crystal layers, can be further clearly obtained.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of barrier layer and the method and structure of planting crystal layer stepcoverage of detecting semiconductor structure for transmission electron microscope (TEM).
Background technology
Along with the development of very lagre scale integrated circuit (VLSIC) technique, semiconductor technology has now entered the sub-micro epoch.In new technological level, especially, on 90 nanometers or following technology node, main signal lag is from the part of interconnection circuit.In traditional semiconductor technology, the main aluminium adopting is restricted on signal lag as interconnect materials.Therefore, searched out new material and met the requirement to resistance, this material is exactly copper.Briefly, process for copper just refers to and usings a series of semiconductor fabrication process of copper as interconnect materials.Process for copper is incorporated to the integrated level that integrated circuit fabrication process can improve chip, improve device density, improve clock frequency and fall low consumed energy.Reaching such requirement just need to be to making corresponding adjustment in technique.
Select the smaller metal material of resistivity as interconnection material, and to select the lower dielectric material of dielectric constant (K) be two main directions that reduce signal lag, improve clock frequency.The resistivity of copper is 1.7 μ Ω cm, and the resistivity of aluminium is 2.8 μ Ω cm, so copper product is more superior.Simultaneously owing to adopting copper cash can reduce the thickness of interconnection layer, so also reduced electric capacity simultaneously.In order further to reduce signal lag, technical field of manufacturing semiconductors is also being selected than silicon dioxide (SiO
2) the lower dielectric material of K value, i.e. so-called low K value dielectric material.Existing aluminum (conventionally selecting the aluminum copper alloy material that mixes a small amount of copper) also there will be the integrity problem being caused by electron transfer in the situation that device density further improves, and copper product also has very strong superiority than aluminium in this respect.When the current density of integrated circuit surpasses a threshold value, dystectic material is easier to occur electron transfer than the material of low melting point, and reason is that the former has higher crystal boundary activation energy of diffusion power.The fusing point of copper is 1083 ℃, and the fusing point of aluminium is 660 ℃, so copper product is not easy to occur electron transfer more.Compare with aluminum, the electromigration failures time of copper product is wanted large one to two order of magnitude, so it can pass through higher current density on less interconnection layer thickness, thereby falls low-energy-consumption.
Due to very difficult to the etching of copper, so copper-connection adopts dual damascene formula technique, claims again dual damascene process (dual damascene), 1) first deposit the silicon nitride (Si that one deck is thin
3n
4) as diffusion impervious layer and etch stop layer, 2) then deposit certain thickness silica (SiO in the above
2), 3) then make micro through hole (via) by lithography, 4) through hole is carried out to partial etching, 5) make again afterwards groove (trench) by lithography, 6) continue to etch complete through hole and groove, 7) be then sputter diffusion impervious layer and copper kind crystal layer, 8) be exactly the electroplating technology of copper interconnecting line afterwards, 9) be finally annealing and chemico-mechanical polishing (CMP), copper coating is carried out to planarization and cleaning.Wherein plant crystal layer and be the conductive layer when electroplating, and barrier layer is as diffusion impervious layer and etch stop layer.In copper interconnection technology, an important aspect is the stepcoverage (step coverage) of controlling barrier layer and planting crystal layer (barrier and seed).Stepcoverage refers on chip every film, deposition materials etc. between each level, when covering, crossing over beneath level, because beneath level just rises and falls, differ and have line weight to change, (as the height intersection that rises and falls) coverage can variation in product section region can to cause this film, deposition materials, the degree of this variation, is stepcoverage.Generally with varied in thickness than representing: stepcoverage=thickness thinnest part and thickness thickness, this ratio more approaches 1 unreasonablely to be thought, otherwise poorer.This just need to detect the stepcoverage of the barrier layer in various structures and kind crystal layer.The copper metallization backend interconnect that are widely used at present great majority improvement in semiconductor technology by the technology of physical vapour deposition (PVD) barrier layer and kind crystal layer.Gradient coating performance is to evaluate barrier layer and plant the key standard that crystal layer forms performance and technology stability.The resolution detecting due to transmission electron microscope is high, can be to lattice structure direct imaging, than the analysis that is more suitable for carrying out micro-scale defect, so the method for conventional inspection stepcoverage is to use transmission electron microscope to detect.
As shown in Figure 1, for detect the method flow diagram of barrier layer and kind crystal layer stepcoverage in prior art for transmission electron microscope, method 100 comprises step 101,102 and 103.In step 101, deposited barrier layer on dielectric materials layer.In step 102, deposition kind of crystal layer on barrier layer.Then in step 103, said structure is carried out to transmission electron microscope sampling, in order to transmission electron microscope detection is carried out in barrier layer and kind crystal layer stepcoverage.
Yet there are some unavoidable problems in transmission electron microscope sampling method of the prior art.Due in more advanced semiconductor fabrication process, dielectric material is all to select the lower material of dielectric constant (K), does like this and can correspondingly reduce electric capacity.But the dielectric material of low-k has the characteristics such as porous and loose (porous), and it also exists defect when having this advantage of the electric capacity of reduction.Relatively more significant one side is, according to the method for Fig. 1, carrying out in the sampling process of transmission electron microscope detection, because for example epoxides adhesion and the sclerosis of transmission electron microscope sampling procedure, focused ion beam (FIB) cutting and ion beam grinding etc. all can produce heat, make the dielectric material of low-k cannot bear the heat of generation, thereby further cause the micro through hole in copper interconnection structure to be badly deformed.Problem is on the other hand, very unclear in the opening data (pinch off data) of carrying out the groove (trench) that transmission electron microscope detection obtains according to the method for Fig. 1.This is to cause the opening of groove inhomogeneous because through hole is badly deformed between transmission electron microscope sampling date.The opening data that this makes cannot clearly obtain groove when transmission electron microscope detects, have greatly affected the effect that transmission electron microscope detects.
Fig. 2 is the schematic diagram of the copper interconnection structure after transmission electron microscope detects in prior art, and the region explanation micro through hole in circle 201 is badly deformed.Fig. 3 is another schematic diagram of the copper interconnection structure after transmission electron microscope detects in prior art, and its mean camber line 301 is expressed through hole and is out of shape, and straight line 302 is expressed groove opening and become very inhomogeneous.
In sum, the above-mentioned problems in the prior art has affected the application of copper interconnection technology more significantly, and it has become current technical field of manufacturing semiconductors problem urgently to be resolved hurrily.
Summary of the invention
In summary of the invention part, introduced the concept of a series of reduced forms, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order to solve when the transmission electron microscope of prior art detects barrier layer and plants crystal layer stepcoverage, cause through hole distortion and the thing followed cannot clearly obtain the problem of transmission electron microscope inspection image data, the invention discloses a kind of method of the semiconductor structure detecting for the preparation of transmission electron microscope, said method comprising the steps of: front end device is provided, on described front end device, is formed with dielectric materials layer; Deposited barrier layer on described dielectric materials layer; On described barrier layer, deposit the first crystal layer; On described the first crystal layer, boundary layer is set; On described boundary layer, deposit the second crystal layer; On described the second crystal layer, packed layer is set.
According to an aspect of the present invention, the K value of wherein said dielectric materials layer is less than 2.75.
According to an aspect of the present invention, the material of wherein said boundary layer is a kind of in tantalum, tungsten, cobalt and ruthenium.
According to an aspect of the present invention, wherein said a kind of setting in physical vapour deposition (PVD), chemical vapour deposition (CVD) and atomic layer electro-deposition for boundary layer.
According to an aspect of the present invention, wherein, when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used no-bias tantalum, and the thickness of described no-bias tantalum is 20 to 200 dusts.
According to an aspect of the present invention, wherein, when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used double-deck tantalum, and described double-deck tantalum is that thickness is the no-bias tantalum of 5 to 10 dusts and the high etching deposition ratio tantalum that thickness is 20 to 200 dusts.
According to an aspect of the present invention, the material of wherein said the second crystal layer is copper.
According to an aspect of the present invention, the thickness of wherein said the second crystal layer is less than 500 dusts.
According to an aspect of the present invention, the material of wherein said packed layer is copper, and uses Cu electroplating that described packed layer is set.
According to an aspect of the present invention, the thickness of wherein said packed layer is greater than 200 dusts.
The invention also discloses a kind of semiconductor structure detecting for transmission electron microscope, described structure comprises: front end device is formed with dielectric materials layer on described front end device; Barrier layer, described barrier deposition is on described dielectric materials layer; The first crystal layer, described the first crystal layer is deposited on described barrier layer; Boundary layer, described boundary layer is arranged on described the first crystal layer; The second crystal layer, described the second crystal layer is deposited on described boundary layer; Packed layer, described packed layer is arranged on described the second crystal layer.
According to an aspect of the present invention, the K value of wherein said dielectric materials layer is less than 2.75.
According to an aspect of the present invention, the material of wherein said boundary layer is a kind of in tantalum, tungsten, cobalt and ruthenium.
According to an aspect of the present invention, wherein said a kind of setting in physical vapour deposition (PVD), chemical vapour deposition (CVD) and atomic layer electro-deposition for boundary layer.
According to an aspect of the present invention, wherein, when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used no-bias tantalum, and the thickness of described no-bias tantalum is 20 to 200 dusts.
According to an aspect of the present invention, wherein, when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used double-deck tantalum, and described double-deck tantalum is that thickness is the no-bias tantalum of 5 to 10 dusts and the high etching deposition ratio tantalum that thickness is 20 to 200 dusts.
According to an aspect of the present invention, the material of wherein said the second crystal layer is copper.
According to an aspect of the present invention, the thickness of wherein said the second crystal layer is less than 500 dusts.
According to an aspect of the present invention, the material of wherein said packed layer is copper, and uses Cu electroplating that described packed layer is set.
According to an aspect of the present invention, the thickness of wherein said packed layer is greater than 200 dusts.
According to the method and structure that detects barrier layer and kind crystal layer stepcoverage for transmission electron microscope provided by the present invention, can be conveniently used in the copper interconnection technology of semiconductor fabrication, and carry out transmission electron microscope detection for barrier layer and kind crystal layer stepcoverage, and can guarantee that through hole can not be out of shape between transmission electron microscope sampling date, and can further clearly obtain the transmission electron microscope detected image for barrier layer and kind crystal layer stepcoverage.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the method flow diagram that detects barrier layer for transmission electron microscope in prior art and plant crystal layer stepcoverage;
Fig. 2 is the schematic diagram of the copper interconnection structure after transmission electron microscope detects in prior art; Fig. 3 is another schematic diagram of the copper interconnection structure after transmission electron microscope detects in prior art;
Fig. 4 is the method flow diagram that detects barrier layer and kind crystal layer stepcoverage for transmission electron microscope according to an embodiment of the invention; And
Fig. 5 is the schematic diagram that detects the structure of barrier layer and kind crystal layer stepcoverage for transmission electron microscope according to an embodiment of the invention;
Fig. 6 is the schematic diagram of the method according to this invention or the copper interconnection structure of structure after transmission electron microscope detects;
Fig. 7 is another schematic diagram of the method according to this invention or the copper interconnection structure of structure after transmission electron microscope detects.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, to detailed step and structure be proposed in following description, so that how explanation the present invention solves prior art cannot guarantee the not problem of damaged distortion of through hole when transmission electron microscope detection is carried out to kind crystal layer stepcoverage in barrier layer.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
As shown in Figure 4, be method 400 flow charts that detect barrier layer and kind crystal layer stepcoverage for transmission electron microscope according to an embodiment of the invention.In step 401, deposited barrier layer on dielectric materials layer.In step 402, deposition kind of crystal layer on barrier layer.The method of barrier layer and kind crystal layer stepcoverage being carried out to transmission electron microscope detection according to prior art, after having carried out above-mentioned steps 401 and step 402, just the sampling of stepcoverage is carried out detecting for transmission electron microscope in barrier layer and kind crystal layer structure.Yet, because the copper interconnection structure being comprised of low K value dielectric material, barrier layer and kind crystal layer is easy to damage and cause such as consequences such as through hole distortion, therefore need to strengthen " intensity " of above-mentioned copper interconnection structure in order to keep not damaged in sampling process in sampling process.
According to the present invention, an effective method strengthening " intensity " of above-mentioned copper interconnection structure is to fill above-mentioned copper interconnection structure completely with packing material.This packing material need to have with above-mentioned porous and the diametical feature of loose feature and have the high good thermal stability of fusing point.
Yet, after using this packing material to fill above-mentioned copper interconnection structure completely, above-mentioned packing material by with step 402 in deposition kind crystal layer, be the first crystal layer " bonding " together, therefore in transmission electron microscope detects the sampling process of stepcoverage, cannot distinguish step 402 in the interface of the first crystal layer of deposition.Therefore, must between above-mentioned the first crystal layer and above-mentioned packing material, one deck boundary layer be set, in order to separate above-mentioned the first crystal layer and above-mentioned packing material, thereby make at the interface of carrying out can clearly distinguishing when transmission electron microscope detects stepcoverage the first crystal layer to be detected, in order to draw correct stepcoverage testing result.More particularly, owing to being applied in copper-connection semiconductor structure, the material require of this boundary layer is heavy metal, the Heat stability is good larger than the atomic weight of copper, and will have reasonable imbibition characteristic between itself and copper product, thereby can " adhere to " on the first crystal layer of copper product.There is various heavy material to meet above-mentioned characteristic requirements and can be for boundary layer is set, such as tantalum (Ta), cobalt (Co), tungsten (W) and ruthenium (Ru) etc.In one embodiment of the invention, preferably with tantalum material, boundary layer is set.
But, using after boundary layer separates above-mentioned the first crystal layer and above-mentioned packing material, packing material cannot directly be arranged on boundary layer securely.For example using between the packed layer of copper product setting and the boundary layer of use tantalum setting and cannot fix, thereby need on packed layer, deposit again one deck kind crystal layer, i.e. the second crystal layer.Require the material of the second crystal layer can be filled material filling and can connect good combination each other.Certainly, good thermal stability is also the requisite characteristic that the material of the second crystal layer should have.
Therefore, according to embodiments of the invention, in step 403, on the first crystal layer being deposited by step 402, one deck boundary layer is set, for the first crystal layer of step 402 deposition and the packed layer " differentiation " that arranges in step are in the back opened.In step 404, in interface layer, deposit again one deck the second crystal layer, for the packed layer that step arranges is in the back filled in above-mentioned copper interconnection structure securely.In step 405, on the second crystal layer being deposited by step 404, packed layer is set, packed layer is filled above-mentioned copper interconnection structure completely.In step 406, utilize transmission electron microscope to carry out the sampling of stepcoverage and detection.
In embodiments of the invention, conventionally select the dielectric material that K value is lower to be used to form dielectric materials layer.Preferably, the K value of dielectric material is less than 2.75.
In a preferred embodiment of the invention, in step 403, use tantalum (Ta) that boundary layer is set and can utilize kinds of processes, techniques such as physical vapour deposition (PVD) (PVD), chemical vapour deposition (CVD) (CVD) and atomic layer electro-deposition (ALD).In one embodiment of the invention, when boundary layer being set with physical vapour deposition (PVD), can choice for use no-bias tantalum when using tantalum that boundary layer is set, and the thickness of no-bias tantalum is 20 to 200 dusts.In another embodiment of the present invention, when boundary layer being set with physical vapour deposition (PVD), can the double-deck tantalum of choice for use when using tantalum that boundary layer is set, wherein double-deck tantalum is that thickness is the no-bias tantalum of 5 to 10 dusts and high etching deposition ratio (Etch and the Deposition Ratio) tantalum that thickness is 20 to 200 dusts.Etching deposition ratio refers to, in carrying out deposition process, when particle additional bias to needs depositions, having part particle penetrates from deposition surface backwash, the particle that can penetrate with backwash and the ratio between the particle of deposition characterize etching deposition ratio, i.e. etching deposition rate example=particle reverse sputtering rate/particle deposition rate.No-bias tantalum refers in deposition process not to tantalum particle additional bias, so the etching deposition ratio of no-bias tantalum is zero.High etching deposition ratio tantalum refers in deposition process tantalum particle additional bias, and makes its etching deposition ratio reach certain numerical value, typically is and is greater than 30%, even can reach 60%.The advantage of no-bias tantalum is, because it has additional bias in deposition process, can not produce damage effect.The advantage of the high etching deposition ratio tantalum in double-deck tantalum is its additional bias in deposition process, and bias voltage can bombard on the kind crystal layer of copper product that tantalum material is attached to sidewall better.
In a preferred embodiment of the invention, in step 404, the kind crystal layer depositing on boundary layer completes with copper product.The thickness of the kind crystal layer preferably, depositing on boundary layer is less than 500 dusts.
In a preferred embodiment of the invention, in step 405, above-mentioned packing material is used copper, and uses electrochemistry plating (ECP) technique to form the packed layer of copper product.Preferably, the thickness of packed layer is greater than 200 dusts.
Therefore owing to having used copper product to fill the copper interconnection structure being formed by dielectric material, barrier layer and kind crystal layer completely in embodiment above, according to the method for Fig. 4, carry out not causing through hole distortion in the sampling process of transmission electron microscope detection.And can obtain more clearly about such as barrier layer with plant the stepcoverage data of crystal layer, the transmission electron microscope testing results such as opening data of groove.
As shown in Figure 5, be the schematic diagram that detects the structure 500 of barrier layer and kind crystal layer stepcoverage for transmission electron microscope according to an embodiment of the invention.The barrier layer 502 that structure 500 comprises dielectric materials layer 501, deposits on dielectric materials layer 501, and the first crystal layer 503 depositing on barrier layer 502.Dielectric materials layer 501, barrier layer 502 and the first crystal layer 503 have formed the copper interconnection structure that carries out transmission electron microscope detection barrier layer and plant crystal layer stepcoverage.Structure 500 is also included in boundary layer 504 that the first crystal layer 503 arranges above, on boundary layer 504 deposition the second crystal layer 505, be arranged on the packed layer 506 on the second crystal layer 505, boundary layer 504 is for planting crystal layer 503 and packed layer 506 " differentiation " is opened, with the boundary face carrying out can being clearly sampled to when transmission electron microscope detects sampling kind of crystal layer 503.Because packed layer 506 cannot closely be filled in the copper interconnection structure detecting for transmission electron microscope of having been opened by boundary layer 504 " separation ", so the second crystal layer 505 is used in particular for making packed layer 506 can completely closely be filled in the copper interconnection structure detecting for transmission electron microscope.It should be noted that, because the effect of kind of crystal layer 505 is exactly for packed layer 506 being filled in completely by the whole copper interconnection structure of boundary layer 504 " differentiation " (, by dielectric materials layer 501, barrier layer 502 and kind crystal layer 503, formed), therefore plant crystal layer 505 and packed layer 506 is bonded together completely, between them, do not have clear and complete boundary (dotting) in Fig. 3.
In the structure shown in Fig. 5, conventionally select the dielectric material that K value is lower to come for dielectric materials layer.Preferably, the K value of dielectric material is less than 2.75.
In the structure shown in Fig. 5, in boundary layer 504, use tantalum (Ta) that boundary layer is set and can utilize kinds of processes, techniques such as physical vapour deposition (PVD) (PVD), chemical vapour deposition (CVD) (CVD) and atomic layer electro-deposition (ALD).When boundary layer being set with physical vapour deposition (PVD), can choice for use no-bias tantalum when using tantalum that boundary layer is set, and the thickness of no-bias tantalum is 20 to 200 dusts.Selectively, when boundary layer being set with physical vapour deposition (PVD), can the double-deck tantalum of choice for use when using tantalum that boundary layer is set, wherein double-deck tantalum is that thickness is the no-bias tantalum of 5 to 10 dusts and high etching deposition ratio (Etch and the Deposition Ratio) tantalum that thickness is 20 to 200 dusts.
In the structure shown in Fig. 5, in kind of crystal layer 505, the kind crystal layer depositing on boundary layer completes with copper product.The thickness of the kind crystal layer preferably, depositing on boundary layer is less than 500 dusts.
In the structure shown in Fig. 5, in packed layer 506, above-mentioned packing material is used copper, and uses electrochemistry plating (ECP) technique to form the packed layer of copper product.Preferably, the thickness of packed layer is greater than 200 dusts.
Fig. 6 is the schematic diagram of the method according to this invention or the copper interconnection structure of structure after transmission electron microscope detects, and the region explanation micro through hole in circle 601 does not have distortion substantially.Fig. 7 is another schematic diagram of the method according to this invention or the copper interconnection structure of structure after transmission electron microscope detects, its mean camber line 701 is expressed through hole does not have distortion substantially, and it is still very even that straight line 702 and 703 is expressed groove opening, and the special expression groove opening of straight line 704 is very even.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (18)
1. a method for the semiconductor samples detecting for the preparation of transmission electron microscope, said method comprising the steps of:
Front end device is provided, on described front end device, is formed with dielectric materials layer;
Deposited barrier layer on described dielectric materials layer;
On described barrier layer, deposit the first crystal layer;
On described the first crystal layer, boundary layer is set;
On described boundary layer, deposit the second crystal layer, the material of described the second crystal layer is copper;
On described the second crystal layer, packed layer is set, the material of described packed layer is copper.
2. method according to claim 1, the K value of wherein said dielectric materials layer is less than 2.75.
3. method according to claim 1, the material of wherein said boundary layer is a kind of in tantalum, tungsten, cobalt and ruthenium.
4. method according to claim 3, wherein said a kind of setting in physical vapour deposition (PVD), chemical vapour deposition (CVD) and atomic layer electro-deposition for boundary layer.
5. method according to claim 4, wherein, when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used no-bias tantalum, and the thickness of described no-bias tantalum is 20 to 200 dusts.
6. method according to claim 4, wherein when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used double-deck tantalum, and described double-deck tantalum is that thickness is the no-bias tantalum of 5 to 10 dusts and the high etching deposition ratio tantalum that thickness is 20 to 200 dusts.
7. method according to claim 1, the thickness of wherein said the second crystal layer is less than 500 dusts.
8. method according to claim 1, is wherein used Cu electroplating that described packed layer is set.
9. method according to claim 8, the thickness of wherein said packed layer is greater than 200 dusts.
10. the semiconductor structure detecting for transmission electron microscope, described structure comprises:
Front end device is formed with dielectric materials layer on described front end device;
Barrier layer, described barrier deposition is on described dielectric materials layer;
The first crystal layer, described the first crystal layer is deposited on described barrier layer;
Boundary layer, described boundary layer is arranged on described the first crystal layer;
The second crystal layer, described the second crystal layer is deposited on described boundary layer, and the material of described the second crystal layer is copper;
Packed layer, described packed layer is arranged on described the second crystal layer, and the material of described packed layer is copper.
11. semiconductor structures according to claim 10, the K value of wherein said dielectric materials layer is less than 2.75.
12. semiconductor structures according to claim 10, the material of wherein said boundary layer is a kind of in tantalum, tungsten, cobalt and ruthenium.
13. semiconductor structures according to claim 12, wherein said a kind of setting in physical vapour deposition (PVD), chemical vapour deposition (CVD) and atomic layer electro-deposition for boundary layer.
14. semiconductor structures according to claim 13, wherein, when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used no-bias tantalum, and the thickness of described no-bias tantalum is 20 to 200 dusts.
15. semiconductor structures according to claim 13, wherein when described boundary layer being set with described physical vapour deposition (PVD), described boundary layer is used double-deck tantalum, and described double-deck tantalum is that thickness is the no-bias tantalum of 5 to 10 dusts and the high etching deposition ratio tantalum that thickness is 20 to 200 dusts.
16. semiconductor structures according to claim 10, the thickness of wherein said the second crystal layer is less than 500 dusts.
17. semiconductor structures according to claim 10, are wherein used Cu electroplating that described packed layer is set.
18. semiconductor structures according to claim 17, the thickness of wherein said packed layer is greater than 200 dusts.
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| US5214283A (en) * | 1991-07-23 | 1993-05-25 | Sgs-Thomson Microelectronics, Inc. | Method of determining the cause of open-via failures in an integrated circuit |
| US6303399B1 (en) * | 2000-09-12 | 2001-10-16 | Advanced Micro Devices Inc. | Method of sample preparation for electron microscopy |
| CN1865898A (en) * | 2005-05-19 | 2006-11-22 | 中芯国际集成电路制造(上海)有限公司 | Transmitted electron microscope sample preparing method for step coverage detection |
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| WO2003026001A2 (en) * | 2001-09-18 | 2003-03-27 | Applied Materials, Inc. | Integrated equipment set for forming an interconnect on a substrate |
| US20050282300A1 (en) * | 2002-05-29 | 2005-12-22 | Xradia, Inc. | Back-end-of-line metallization inspection and metrology microscopy system and method using x-ray fluorescence |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5214283A (en) * | 1991-07-23 | 1993-05-25 | Sgs-Thomson Microelectronics, Inc. | Method of determining the cause of open-via failures in an integrated circuit |
| US6303399B1 (en) * | 2000-09-12 | 2001-10-16 | Advanced Micro Devices Inc. | Method of sample preparation for electron microscopy |
| CN1865898A (en) * | 2005-05-19 | 2006-11-22 | 中芯国际集成电路制造(上海)有限公司 | Transmitted electron microscope sample preparing method for step coverage detection |
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