CN101831618B - Gate dielectric film with TiO2/ZrO2 two-layer stack structure and high dielectric constant and preparation method thereof - Google Patents
Gate dielectric film with TiO2/ZrO2 two-layer stack structure and high dielectric constant and preparation method thereof Download PDFInfo
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- CN101831618B CN101831618B CN2010101528191A CN201010152819A CN101831618B CN 101831618 B CN101831618 B CN 101831618B CN 2010101528191 A CN2010101528191 A CN 2010101528191A CN 201010152819 A CN201010152819 A CN 201010152819A CN 101831618 B CN101831618 B CN 101831618B
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Abstract
The invention provides a film which can obtain a high dielectric constant and improved crystallization temperature to a certain extent simultaneously and has a TiO2/ZrO2 two-layer stack structure as well as a preparation method thereof. The film takes a silicon slice as a substrate and is characterized in that a ZrO2 film is firstly deposited on the Si substrate by adopting a magnetron sputtering technology, and then a TiO2 film is deposited on the ZrO2 film to form the film with the TiO2/ZrO2 two-layer stack structure. In the invention, the film with the TiO2/ZrO2 two-layer stack structure is prepared by adopting the magnetron sputtering technology, the introduction of Ti can effectively restrict the crystallization of the film, and the crystallization temperature can be improved to a certain extent; and meanwhile, the invention can also obtain an appropriate high dielectric constant.
Description
Technical field
That the present invention relates to is a kind of TiO with high-k
2/ ZrO
2Two-layer stack structure film and preparation method thereof belongs to microelectronic, dielectric substance scientific domain and nanoscale science and technology field.
Technical background
ZrO
2Because its specific inductivity (18--25) that is fit to, energy gap (～7.8eV), good chemicalstability is acknowledged as and is best suited for substituting traditional Si O
2The high-dielectric-coefficient grid medium material.Use high-k (k) ZrO
2Material substitutes SiO
2, make and under identical equivalent thickness, not only can eliminate the tunnelling leakage current, and can make power consumption reduce by 10000 times.Yet because ZrO
2Tc lower, be approximately about 350 ℃, limited its application.In order to improve Tc, suppress the crystallization of film, carried out a large amount of research in the world, major part all is about ZrO
2/ SiO
2, ZrO
2/ Al
2O
3Two-layer stack structure.In these structures, though the introducing of Si, Al can both suppress the crystallization of film to a certain extent, but, generate the interfacial layer of one deck low-k, thereby make specific inductivity reduce, so effect is very desirable owing to easy and Si substrate react.Seek new two-layer stack structure and substitute traditional Si O
2Gate dielectric material, very important to the performance that improves microelectronic product.
Summary of the invention
The objective of the invention is to propose a kind of TiO that has high-k and higher crystallization temperature simultaneously
2/ ZrO
2Gate dielectric membrane of two-layer stack structure and preparation method thereof.
The present invention realizes like this.It is substrate with the silicon chip, deposits one deck ZrO above that earlier with magnetron sputtering technique
2Film deposits one deck TiO more above that
2Film so just obtains TiO
2/ ZrO
2The two-layer stack structure film.With film at O
2In carry out anneal, annealing temperature is 300--500 ℃, annealing 30min, wherein 400 ± 20 ℃ of effects are best.
Preparing method of the present invention is:
1, selecting purity for use is 99.99% ZrO
2Target and TiO
2Target is a sputtering target material, and it is placed on respectively on two rotary target platforms in the sputtering chamber, and the target-substrate distance of regulating both respectively is 4--8cm, and the Si sheet that cleans up (P type, resistivity are 8--13 Ω cm) is placed on the chip bench in the sputtering chamber.
2, the sputtering chamber base vacuum is evacuated to 2.0--2.5 * 10
-4Pa feeds high-purity argon gas then, and the flow of controlling argon gas through mass flowmeter is 30--70sccm, regulates the sputtering chamber main valve and makes the sputtering chamber operating air pressure be stabilized in 0.3--1Pa.
3, adopt magnetron sputtering technique on the Si substrate, to deposit one deck ZrO
2Film is regulated sputtering voltage and sputtering current, makes sputtering power be about 100--150W, and sputtering time is 3--5min.
4, adopt magnetron sputtering technique at ZrO
2Deposit one deck TiO above the film again
2Film is regulated sputtering voltage and sputtering current, makes sputtering power be about 100--150W, and sputtering time is 3--5min.
5, after thin film deposition is all accomplished, film is taken out at O
2In carry out anneal, annealing temperature is 300--500 ℃, annealing 30min.
The present invention compared with prior art has tangible advantage, TiO
2/ ZrO
2In the two-layer stack structure film,, can suppress the crystallization of film to a certain extent, as shown in Figures 2 and 3, when annealing temperature is 500 ℃, also can't see the obvious diffraction peak owing to the introducing of Ti.Simultaneously because TiO
2Specific inductivity bigger, be approximately about 80, thereby make the film of this structure before and after annealing, all have a higher dielectric constant.
Accompanying drawing and explanation
Fig. 1 is the TiO with the present invention's preparation
2/ ZrO
2Two-layer stack structure mos capacitance device structural representation;
Fig. 2 is the TiO of embodiment 1 preparation
2/ ZrO
2The X ray diffracting spectrum of two-layer stack structure film;
Fig. 3 is the TiO of embodiment 2 preparations
2/ ZrO
2The X ray diffracting spectrum of two-layer stack structure film;
Fig. 4 is the capacity measurement result of embodiment 1, and test curve when wherein a is unannealed, b are at O
2In 300 ℃ when annealing test curve, c is at O
2In 400 ℃ when annealing test curve, d is at O
2In 500 ℃ when annealing test curve;
Fig. 5 is the capacity measurement result of embodiment 2, and test curve when wherein a is unannealed, b are at O
2In 300 ℃ when annealing test curve, c is at O
2In 400 ℃ when annealing test curve, d is at O
2In 500 ℃ when annealing test curve;
Embodiment
In conjunction with content of the present invention, following examples are provided:
Embodiment 1:
1, selecting purity for use is 99.99% ZrO
2Target and TiO
2Target is a sputtering target material, and it is placed on respectively on two rotary target platforms in the sputtering chamber, regulates both target-substrate distances and is 5cm, and the Si sheet that cleans up (P type, resistivity are 8--13 Ω cm) is placed in the substrate holder in the sputtering chamber.
2, sediment chamber's base vacuum is evacuated to 2.0 * 10
-4Pa feeds high-purity argon gas then, and the flow of controlling argon gas through mass flowmeter is 30sccm, regulates the sputtering chamber main valve and makes the sputtering chamber operating air pressure be stabilized in 0.3Pa.
3, regulate ZrO
2The sputtering voltage of target and sputtering current make its build-up of luminance sputter, and sputtering power is about 150W.Specimen rotating holder, make on the sample table subsequent use Si sheet over against its below ZrO
2Target, the ZrO of deposition one 5 minutes (min)
2Layer is removed sample table then.
4, regulate TiO
2The sputtering voltage of target and sputtering current make its build-up of luminance sputter, and sputtering power is about 150W.Specimen rotating holder makes the TiO of sample table over against its below
2Target deposits the TiO of 4 minutes (min) again
2Layer is removed sample table then.
5, after thin film deposition is all accomplished, film is taken out at O
2In carry out anneal, annealing temperature is 300--500 ℃, annealing 30min.
Process the Thin Film MOS electrical condenser as follows and carry out performance test.
1, selecting purity for use is that 99.99% Pt target is a sputtering target material, adopts magnetron sputtering equipment at the thick Pt lower electrode of the back spatter 100nm that makes sample.
2, selecting purity for use is that 99.99% Pt target is a sputtering target material, adopts magnetron sputtering equipment positive at these samples again, through the thick Pt top electrode figure of the method sputter 100nm of mask film covering plate.Form TiO
2/ ZrO
2Two-layer stack structure Thin Film MOS electrical condenser.
The X-ray diffraction test shows adopts the TiO of magnetron sputtering technique preparation
2/ ZrO
2The two-layer stack structure film is a non-crystalline state, and and silicon substrate between no tangible interfacial layer, when 500 ℃ down annealing still do not have obvious crystallization after half hour, as shown in Figure 2, this is illustrated in TiO
2/ ZrO
2In the two-layer stack structure, the introducing of Ti can effectively suppress the crystallization of film.The C-V test shows is by TiO
2/ ZrO
2The two-layer stack structure film is 21 as the mos capacitance device specific inductivity that dielectric medium constitutes, and after 400 ℃ of anneal, the specific inductivity of sample is up to 25, and maximum capacitor is 875.88PF, and is as shown in Figure 4, and this shows TiO
2/ ZrO
2The two-layer stack structure film has suitable specific inductivity as gate dielectric membrane.
Embodiment 2:
1, selecting purity for use is 99.99% ZrO
2Target and TiO
2Target is a sputtering target material, and it is placed on respectively on two rotary target platforms in the sputtering chamber, regulates both target-substrate distances and is 5cm, and the Si sheet that cleans up (P type, resistivity are 8--13 Ω cm) is placed in the substrate holder in the sputtering chamber.
2, sediment chamber's base vacuum is evacuated to 2.0 * 10
-4Pa feeds high-purity argon gas then, and the flow of controlling argon gas through mass flowmeter is 30sccm, regulates the sputtering chamber main valve and makes the sputtering chamber operating air pressure be stabilized in 0.3Pa.
3, regulate ZrO
2The sputtering voltage of target and sputtering current make its build-up of luminance sputter, and sputtering power is about 150W.Specimen rotating holder, make on the sample table subsequent use Si sheet over against its below ZrO
2Target, the ZrO of deposition one 5 minutes (min)
2Layer is removed sample table then.
4, regulate TiO
2The sputtering voltage of target and sputtering current make its build-up of luminance sputter, and sputtering power is about 150W.Specimen rotating holder makes the TiO of sample table over against its below
2Target deposits the TiO of 5 minutes (min) again
2Layer is removed sample table then.
5, after thin film deposition is all accomplished, film is taken out at O
2In carry out anneal, annealing temperature is 300--500 ℃, annealing 30min.
Process the Thin Film MOS electrical condenser as follows and carry out performance test.
1, selecting purity for use is that 99.99% Pt target is a sputtering target material, the thick Pt lower electrode of sample back spatter 100nm that adopts magnetron sputtering equipment making.
2, selecting purity for use is that 99.99% Pt target is a sputtering target material, adopts magnetron sputtering equipment positive at these samples again, through the thick Pt top electrode figure of the method sputter 100nm of mask film covering plate.Form TiO
2/ ZrO
2Two-layer stack structure Thin Film MOS electrical condenser.
The X-ray diffraction test shows adopts the TiO of magnetron sputtering technique preparation
2/ ZrO
2The two-layer stack structure film is a non-crystalline state, and and silicon substrate between no tangible interfacial layer, when 500 ℃ down annealing still do not have obvious crystallization after half hour, as shown in Figure 3, this is illustrated in TiO
2/ ZrO
2In the two-layer stack structure, the introducing of Ti can effectively suppress the crystallization of film.The C-V test shows is by TiO
2/ ZrO
2The two-layer stack structure film is 22 as the mos capacitance device specific inductivity that dielectric medium constitutes, and after 400 ℃ of anneal, the specific inductivity of sample is up to 34, and maximum capacitor is 1064.7PF, and is as shown in Figure 5, and this shows TiO
2/ ZrO
2The two-layer stack structure film has suitable specific inductivity as gate dielectric membrane.
Claims (4)
1. TiO
2/ ZrO
2The two-layer stack structure gate dielectric membrane with high dielectric coefficient, it is a substrate with the silicon chip, it is characterized in that depositing one deck ZrO above that earlier with magnetron sputtering technique
2Film deposits one deck TiO more above that
2Film obtains TiO
2/ ZrO
2The two-layer stack structure film, with film at O
2In carry out anneal, annealing temperature is 300--500 ℃, annealing 30min.
2. a kind of TiO according to claim 1
2/ ZrO
2The two-layer stack structure gate dielectric membrane with high dielectric coefficient is characterized in that described annealing temperature is 400 ± 20 ℃.
3. TiO
2/ ZrO
2The preparation method of two-layer stack structure gate dielectric membrane with high dielectric coefficient is characterized in that step is:
A, to select purity for use be 99.99% ZrO
2Target and TiO
2Target is a sputtering target material, and it is placed on respectively on two rotary target platforms in the sputtering chamber, and the target-substrate distance of regulating both respectively is 4--8cm, is that 8--13 Ω cm Si sheet is placed in the substrate holder in the sediment chamber with the P type that cleans up, resistivity;
B, the sputtering chamber base vacuum is evacuated to 2.0--2.5 * 10
-4Pa feeds high-purity argon gas then, and the flow of controlling argon gas through mass flowmeter is 30-70sccm, regulates the sputtering chamber main valve and makes the sputtering chamber operating air pressure be stabilized in 0.3--1Pa;
C, employing magnetron sputtering technique deposit one deck ZrO on the Si substrate
2Film is regulated sputtering voltage and sputtering current, makes that sputtering power is 100-150W, and sputtering time is 3-5min;
D, employing magnetron sputtering technique are at ZrO
2Deposit one deck TiO above the film again
2Film is regulated sputtering voltage and sputtering current, makes that sputtering power is 100-150W, and sputtering time is 3--5min;
E, thin film deposition after all accomplishing are taken out film at O
2In carry out anneal, annealing temperature is 300-500 ℃, annealing 30min.
4. a kind of TiO according to claim 3
2/ ZrO
2The preparation method of two-layer stack structure gate dielectric membrane with high dielectric coefficient is characterized in that the described annealing temperature of step e is 400 ± 20 ℃.
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| CN105261657B (en) * | 2015-10-30 | 2018-05-11 | 中国振华集团云科电子有限公司 | A kind of manufacturing process of MIS thin film capacitors |
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| CN1541963A (en) * | 2003-11-04 | 2004-11-03 | 上海大学 | Substrate glass material for magnetic recording memory medium and preparing process thereof |
| CN1779923A (en) * | 2005-09-23 | 2006-05-31 | 中国科学院上海技术物理研究所 | Production of thin-film ferroelectric materials with lead zirconate-titanate with reading circuit integration |
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| CN1541963A (en) * | 2003-11-04 | 2004-11-03 | 上海大学 | Substrate glass material for magnetic recording memory medium and preparing process thereof |
| CN1779923A (en) * | 2005-09-23 | 2006-05-31 | 中国科学院上海技术物理研究所 | Production of thin-film ferroelectric materials with lead zirconate-titanate with reading circuit integration |
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