TWI624090B - Resistive random access memory device and method for manufacturing the same - Google Patents

Abstract

A resistive random access memory device includes a bottom electrode, a resistance conversion layer, a top electrode, a metal layer, and a barrier layer. The resistance conversion layer is disposed on the bottom electrode. The top electrode is disposed on the resistance conversion layer. The metal layer is disposed on the top electrode. The barrier layer covers the metal layer. Wherein, the barrier layer surrounds the metal layer and the top electrode.

Description

Resistive random access memory device and manufacturing method thereof

The present disclosure relates generally to a resistive random access memory device, and more particularly to a resistive random access memory device including a barrier layer.

Resistive random-access memory (ReRAM) is a memory having an element called a memristor (abbreviation of memory resistance). The resistance of the resistive random access memory varies with the different voltages applied. The resistive random access memory device acts by changing the resistance of the memristor to store data.

During the manufacture of the resistive random access memory device, a back-end process can be performed, such as forming an inter-metal dielectric layer (IMD layer), a metal layer, and protection. The process of the passivation. However, these latter stages may generate some gas (such as hydrogen (H), ammonia (NH ₃ ), silane (SiH ₄ ), which causes loss of data storage in the resistive random access memory device. Therefore, currently There is still a need to develop a method for preventing data loss of a resistive random access memory device, and to manufacture a resistive random access memory device having excellent structural reliability.

The present disclosure relates to a resistive random access memory device and a method of fabricating the same. The resistive random access memory device has a barrier layer covering and surrounding the metal layer, so that the resistive random access memory device is performing a back end process (for example, forming an intermetal dielectric layer, a metal layer, And the process of the protective layer) can have a lower data retention loss and improve the reliability of the resistive random access memory device.

According to an embodiment, the present disclosure provides a resistive random access memory. The resistive random access memory includes a bottom electrode, a resistance conversion layer, a top electrode, a metal layer, and a barrier layer. The resistance conversion layer is disposed on the bottom electrode. The top electrode is disposed on the resistance conversion layer. The metal layer is disposed on the top electrode. The barrier layer covers the metal layer. Wherein, the barrier layer surrounds the metal layer and the top electrode.

According to an embodiment, the present disclosure provides a method of fabricating a resistive random access memory device. The manufacturing method includes: forming an opening in an insulating layer; depositing a conductive material in the opening; removing the conductive material above the opening to form a bottom electrode; forming a resistance conversion layer on the bottom electrode; Forming a top electrode on the resistance conversion layer; forming a metal layer on the top electrode; and forming a barrier layer covering the metal layer, wherein the barrier layer surrounds the metal layer and the top electrode.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings are set forth below. However, the scope of the invention is defined by the scope of the appended claims.

10, 20, 30‧‧‧Resistive random access memory devices

100‧‧‧Substrate

101‧‧‧ preliminary structure

110‧‧‧ Well

112‧‧‧Slightly doped bungee

120‧‧‧ gate oxide structure

122‧‧‧Oxide layer

124‧‧‧ gate material layer

210‧‧‧Dielectric layer

210a‧‧‧ top surface

220, 320‧‧‧ conductive connection structure

230‧‧‧Insulation

240‧‧‧ openings

250, 350, 450‧‧‧Resistive random access memory cells

252, 352, 452‧‧ ‧ bottom electrode

254, 354, 454‧‧‧ resistance conversion layer

256, 356, 456‧ ‧ top electrode

260‧‧‧Block

2521‧‧‧First bottom electrode layer

2522‧‧‧second bottom electrode layer

2561‧‧‧First top electrode layer

2562‧‧‧second top electrode layer

M1‧‧‧ metal layer

M1a‧‧‧ side wall

1 is a cross-sectional view of a resistive random access memory device in accordance with an embodiment of the present disclosure.

2A to 2J are cross-sectional views showing the fabrication of a resistive random access memory device in accordance with an embodiment of the present disclosure.

3 is a cross-sectional view of a resistive random access memory device in accordance with another embodiment of the present disclosure.

4 is a cross-sectional view of a resistive random access memory device in accordance with still another embodiment of the present disclosure.

The embodiments of the present disclosure are for explaining a resistive random access memory device and a method of fabricating the same. The resistive random access memory device and the manufacturing method thereof provide a resistive random access memory device with a barrier layer covering and surrounding the metal to protect the resistive random access memory unit, so that the resistor The random access memory device can have lower data retention loss and improve resistive random access memory after the back end process (for example, the process of forming an intermetal dielectric layer, a metal layer, and a protective layer) The reliability of the device.

Hereinafter, various embodiments of the present disclosure will be described with reference to the accompanying drawings to describe the related configurations and manufacturing methods. Relevant structural details such as related layers and spatial configurations are as described in the following examples. However, the disclosure is not limited to the described aspects, and the disclosure does not show all possible embodiments. The same or similar reference numerals in the embodiments are used to designate the same or similar parts. Furthermore, other than those disclosed in this disclosure Implementation aspects may also be applicable. Variations and modifications of the structure of the embodiments can be made in the relevant embodiments without departing from the spirit and scope of the disclosure. The drawings have been simplified to clearly illustrate the contents of the embodiments, and the dimensional ratios in the drawings are not drawn to scale in terms of actual products. Therefore, the description and illustration are for illustrative purposes only and are not intended to be limiting.

Furthermore, the terms used in the specification and the claims, such as "first", "second", "third" and the like, are used to modify the elements of the claim, which are not intended to be Any previous ordinal does not represent the order of a request element and another request element, or the order of the manufacturing method. The use of these ordinals is only used to make one request element with a certain name the same as the other. Named request elements can make a clear distinction.

1 is a cross-sectional view of a resistive random access memory device in accordance with an embodiment of the present disclosure.

Referring to FIG. 1 , the resistive random access memory device 10 includes a substrate 100 , a dielectric layer 210 (eg, an inter-layer dielectric (ILD)), a conductive connection structure 220 , and an insulating layer. The layer 230, a bottom electrode 252, a resistive conversion layer 254, a top electrode 256, a metal layer M1, and a barrier layer 260. The conductive connection structure 220 is disposed on the substrate 100 and passes through the dielectric layer 210. The insulating layer 230 The bottom electrode 252 is disposed on the substrate 100 and the conductive connection structure 220. The resistance conversion layer 254 is disposed on the bottom electrode 252. The top electrode 256 is disposed on the resistance conversion layer 254. The metal layer M1 is disposed on the top electrode 256. The barrier layer 260 covers the metal layer M1. The bottom electrode 252, the resistance conversion layer 254, and the top electrode 256 form a resistive random access memory unit 250.

In this embodiment, the barrier layer 260 surrounds the insulating layer 230, the bottom electrode 252, the resistance conversion layer 254, the top electrode 256, and the metal layer M1, and the barrier layer 260 contacts one sidewall of the insulating layer 230 and one sidewall of the top electrode 256. And a side wall M1a of the metal layer M1. The dielectric layer 210 has a top surface 210a, and the barrier layer 260 continuously covers the top surface 210a, the insulating layer 230, the top electrode 256, and the metal layer M1. The bottom electrode 252 and the resistance conversion layer 254 are disposed in the opening 240 of the insulating layer 230 (as shown in FIG. 2C).

In some embodiments, substrate 100 may be formed of a cerium-containing oxide or other material suitable for use in a substrate. A well 110 and a lightly doped drain implant (LDD) 112 may be formed in the substrate 100. Well 110 can be a P-type doped well or an N-type doped well and can be a source or a drain. The gate oxide structure 120 may be formed on the substrate 100. The gate oxide structure 120 can include an oxide layer 122 and a gate material layer 124. The gate material layer 124 can be formed of polysilicon. A spacer (not shown) may be formed on the sidewall of the gate oxide structure 120. A field oxide layer (not shown) may be formed on the substrate 100.

In some embodiments, the dielectric layer 210 can be a plurality of layers, such as Undoped Silicate Glass (USG), Phosphorus-doped Phosphorus Glass (PSG), and Tantalum Nitride Layer (SiN). A layer formed of a layer and a tetraethoxysilane (TEOS). The insulating layer 230 may be formed of a dielectric material and has a thickness ranging from 200 angstroms to 2000 angstroms. In this embodiment The insulating layer 230 is formed of an oxide and has a thickness of 1000 angstroms.

In some embodiments, the electrically conductive connection structure 220 can be a single layer structure or a two layer structure. The conductive connection structure 220 may be formed of a metal such as tungsten (W), titanium nitride (TiN), or a combination thereof.

In some embodiments, the bottom electrode 252 can include, but is not limited to, tungsten (W), copper (Cu), iron (Fe), titanium (Ti), nickel (Ni), hafnium (Hf), titanium nitride. (TiN), tantalum nitride (TaN), and other applicable materials. The bottom electrode 252 may be a single layer structure or a two layer structure, for example, a two-layer structure formed of tungsten (W) and titanium nitride (TiN). The thickness of the bottom electrode 252 may be in the range of 200 angstroms to 2000 angstroms. In the present embodiment, the bottom electrode 252 has a thickness of 1000 angstroms. In the present embodiment, the bottom electrode 252 is formed on the top surface 210a of the dielectric layer 210 and is in contact with the conductive connection structure 220.

The resistance conversion layer 254 may include a material selected from the group consisting of titanium nitride (TiN), tungsten oxide (WO _X ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), and hafnium oxide (SiO ₂ ). The material of the resistance conversion layer 254 is not limited thereto, and may be any other material suitable as a resistance conversion layer of a resistive random access memory device. The bottom electrode 252 and the conductive connection structure 220 may comprise the same material.

In some embodiments, the top electrode 256 can be a single layer structure or a multilayer structure. For example, the top electrode 256 may be a two-layer structure formed of titanium nitride (TiN) and titanium (Ti).

In some embodiments, the material of the metal layer M1 may be any metal material such as aluminum (Al) or copper (Cu).

In some embodiments, the barrier layer 260 can comprise an oxynitride material such as bismuth oxynitride (SiON), titanium oxynitride (TiON) or strontium titanium oxide (TiSiON). Resistance The thickness of the barrier layer 260 can be in the range of 50 angstroms to 1000 angstroms. In the present embodiment, the barrier layer 260 is formed of bismuth oxynitride (SiON) and has a thickness of 500 angstroms.

In some embodiments, the resistive random access memory device 10 can include one or more than one dielectric layer (eg, an inter-metal dielectric layer (IMD layer)) disposed over the dielectric layer 210. The protective layer may be formed on the dielectric layer 210 and the inter-metal dielectric layer (not shown). The inter-metal dielectric layer may cover the barrier layer 260, and interlayer vias may be formed on the metal layer M1. A portion of the barrier layer 260 (not shown) is penetrated and penetrated.

In some embodiments, the resistive random access memory cell 250 can be formed on the interlayer connection point disposed on the metal layer M1 instead of the conductive connection structure 220, and the barrier layer 260 can cover and contact other configurations. On the metal layer above the interlayer connection point, instead of covering and contacting the dielectric layer 210 (not shown). That is, the barrier layer 260 can surround the metal layer and the resistive random access memory cell (not shown) located above the connection point between the layers.

Since the barrier layer 260 continuously covers the top surface 210a and the metal layer M1 of the dielectric layer 210, and also surrounds the top electrode 256 and the metal layer M1, the resistive random access memory unit 250 can be fully protected from being protected from The gas generated by the back end process (for example, a process for forming an inter-metal dielectric layer, a metal layer, and a protective layer) (for example, hydrogen (H), ammonia (NH ₃ ), and decane (SiH ₄ ). Since the barrier layer 260 of the present disclosure is formed directly on the metal layer M1 and surrounds the top electrode 256 and the metal layer M1, the barrier layer 260 is not formed between the metal layer M1 and the top electrode 256, so the metal layer M1 is not required. An additional conductive structure is formed between the top electrodes 256. Therefore, the process of the present disclosure is simpler and faster than the comparative example in which the barrier layer is formed between the metal layer and the top electrode.

2A to 2J are cross-sectional views showing the fabrication of the resistive random access memory device 10 in accordance with an embodiment of the present disclosure.

Please refer to FIG. 2A to provide a preliminary structure 101. The preliminary structure 101 can be formed by a front-end process in a conventional CMOS process. The preliminary structure 101 may include a substrate 100, a well 110 formed in the substrate 100, a slightly doped gate 112 formed in the substrate 100, a gate oxide structure 120 formed on the substrate 100, and formed on the substrate 100. A dielectric layer 210 (eg, an interlayer dielectric layer) and a conductive connection structure 220 are disposed. The conductive connection structure 220 is formed on the substrate 100 and passes through the dielectric layer 210. The gate oxide structure 120 can include an oxide layer 122 and a gate material layer 124. The gate material layer 124 can be formed of polysilicon. A spacer (not shown) may be formed on the sidewall of the gate oxide structure 120. A field oxide layer (not shown) may be formed on the substrate 100. The conductive connection structure 220 corresponds to the well 110 formed in the substrate 100. The top surface 210a of the dielectric layer 210 and the conductive connection structure 220 may be exposed by performing a chemical mechanical polishing (CMP) process.

Referring to FIG. 2B, the insulating layer 230 can be formed by a deposition process (for example, Plasma-Enhanced Chemical Vapor Deposition (PECVD), Chemical Vapor Deposition (CVD)). The dielectric layer 210 and the conductive connection structure 220. The material of the insulating layer 230 may be formed of a dielectric material and may have a thickness ranging from 200 angstroms to 2000 angstroms. In the present disclosure, the insulating layer 230 is formed of an oxide and has a thickness of 1000 angstroms.

Referring to FIG. 2C, an opening 240 is formed in the insulating layer 230 by an etching process (for example, a dry etching process). The opening 240 exposes a portion of the conductive connection structure 220 and defines a region for forming the bottom electrode 252. The width of the opening 240 is less than the width of the conductive connection structure 220.

Referring to FIG. 2D, a first bottom electrode layer 2521 and a second bottom electrode layer 2522 are formed on the insulating layer 230 and in the opening 240. The first bottom electrode layer 2521 and the second bottom electrode layer 2522 can be formed by depositing a conductive material on the insulating layer 230 and in the opening 240. In an embodiment, the material of the first bottom electrode layer 2521 may be titanium (Ti) or titanium nitride (TiN), and the material of the second bottom electrode layer 2522 may include, but is not limited to, tungsten (W), copper. (Cu), iron (Fe), titanium (Ti), nickel (Ni), hafnium (Hf), titanium nitride (TiN), tantalum nitride (TaN), and other applicable materials. The thickness of the first bottom electrode layer 2521 may be in the range of 10 angstroms to 200 angstroms. The thickness of the second bottom electrode layer 2522 may be in the range of 1000 to 3000 angstroms. In the present embodiment, the thickness of the first bottom electrode layer 2521 is 25 angstroms, and the thickness of the second bottom electrode layer 2522 is 2500 angstroms.

Referring to FIG. 2E, a portion of the first bottom electrode layer 2521 and the second bottom electrode layer 2522 are removed by mechanical grinding to remove the conductive material located above the opening 240. That is, the first bottom electrode layer 2521 and the second bottom electrode layer 2522 located above the opening 240 are completely removed. Next, a bottom electrode 252 including the first bottom electrode layer 2521 and the second bottom electrode layer 2522 passing through the insulating layer 230 and contacting the conductive connection structure 220 is formed in the opening 240.

Referring to FIG. 2F, a resistance conversion layer 254 is formed by performing an oxidation process on the bottom electrode 252. In some embodiments, the oxidation process is performed by a plasma oxidation process. The resistance conversion layer 254 may include a material selected from the group consisting of titanium nitride (TiN), tungsten oxide (WO _X ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), and hafnium oxide (SiO ₂ ). In the present embodiment, the resistance conversion layer 254 is formed of tungsten oxide (WO _X ).

Referring to FIG. 2G, the first top electrode layer 2561 and the second top electrode layer 2562 are sequentially formed on the insulating layer 230 by a deposition process. The first top electrode layer 2561 may be formed of titanium (Ti) and has a thickness in the range of 10 angstroms to 100 angstroms. The second top electrode layer 2562 may be formed of titanium nitride (TiN) and has a thickness in the range of 100 angstroms to 1000 angstroms.

Referring to FIG. 2H, a portion of the insulating layer 230, the first top electrode layer 2561 and the second top electrode layer 2562 are removed by an etching process (for example, a dry etching process) to form the first top electrode layer 2561 and The top electrode 256 of the second top electrode layer 2562. The first top electrode layer 2561 can serve as a buffer layer between the resistance conversion layer 254 and the second top electrode layer 2562. After the etching process, the remaining portion of the insulating layer 230 may cover a portion of the top surface 210a of the dielectric layer 210 and the conductive connection structure 220, and the sidewalls of the insulating layer 230 may be aligned with the sidewalls of the top electrode 256. As a result, the resistive random access memory cell 250 including the bottom electrode 252, the resistance conversion layer 254, and the top electrode 256 is formed. The top electrode 256 is exemplarily illustrated as a two-layer structure, and the structure of the top electrode 256 is not limited thereto.

Referring to FIG. 2I, a metal layer M1 is formed on the conductive connection structure 220 and the top electrode 256. Next, a metal layer M1 corresponding to the conductive connection structure 220 is formed by an etching process. A side wall M1a of the metal layer M1 is aligned with the sidewall of the top electrode 256 and the sidewall of the insulating layer 230. The material of the metal layer M1 may be any metal material such as aluminum (Al) or copper (Cu).

Referring to FIG. 2J, the barrier layer 260 is formed by a deposition process. The barrier layer 260 covers the top surface 210a of the dielectric layer 210, the insulating layer 230, the resistive random access memory cell 250, and the metal layer M1. In some embodiments, the barrier layer 260 can comprise an oxynitride material such as bismuth oxynitride (SiON), titanium oxynitride (TiON) or strontium titanium oxide (TiSiON). The thickness of the barrier layer 260 may range from 50 angstroms to 1000 angstroms. In the present embodiment, the barrier layer 260 is formed of bismuth oxynitride (SiON) and has a thickness of 500 angstroms. As such, the resistive random access memory device 10 according to an embodiment of the present disclosure is formed.

FIG. 3 is a cross-sectional view of a resistive random access memory device 20 in accordance with another embodiment of the present disclosure. Please also refer to Figure 1. In the drawings, the same and/or similar elements are denoted by the same and/or the same reference numerals, and the configuration, the manufacturing method and the functions of the layers of the same elements/layers are not described herein again.

Referring to FIG. 3, the bottom electrode 352 and the conductive connection structure 320 having the same material and width can be formed by different deposition processes. Alternatively, the bottom electrode 352 and the conductive connection structure 320 having substantially the same structure may be formed by the same process. The bottom electrode 352 can be formed in an opening of the dielectric material 210, and the resistance conversion layer 354 can be formed by performing an oxidation process on the bottom electrode 352. The bottom electrode 352 and the resistance conversion layer 354 may be formed under the top surface 210a. The top electrode 356 may be formed on a portion of the top surface 210a and the resistance conversion layer 354. As such, a resistive random access memory cell 350 including a bottom electrode 352, a resistance conversion layer 354, and a top electrode 356 can be formed on the conductive connection structure 320. The metal layer M1 is disposed on the top electrode 356. The barrier layer 260 continuously covers the top surface 210a and the metal Layer M1 surrounds metal layer M1 and top electrode 356. The barrier layer 260 also contacts the sidewall of the top electrode 356 and the sidewall M1a of the metal layer M1.

4 is a cross-sectional view of a resistive random access memory device 30 in accordance with yet another embodiment of the present disclosure. Please also refer to Figure 1. Furthermore, the same and/or similar elements in the fourth and the first drawings are given the same and/or similar reference numerals, and the configuration, the manufacturing method and the functions of the layers of the same elements/layers are not described herein again.

Referring to FIG. 4, the bottom electrode 452 is not formed in the opening of the insulating layer formed on the dielectric layer, but is formed directly on the top surface 210a and the conductive connection structure 220. There may be no remaining insulating layer on the top surface 210a of the dielectric layer 210, and the bottom electrode 452 covers and contacts a portion of the top surface 210a and the conductive connection structure 220. The width of the bottom electrode 452 is greater than the width of the conductive connection structure 220. The resistance conversion layer 454 is disposed on the bottom electrode 452, and the top electrode 456 is disposed on the resistance conversion layer 454. As a result, a resistive random access memory cell 450 including a bottom electrode 452, a resistance conversion layer 454, and a top electrode 456 is formed on the conductive connection structure 220. The metal layer M1 is disposed on the top electrode 456. The barrier layer 260 continuously covers the top surface 210a and the metal layer M1, and surrounds the metal layer M1 and the resistive random access memory unit 450. Moreover, the barrier layer 260 is in contact with the sidewall of the bottom electrode 452, the sidewall of the resistance conversion layer 454, the sidewall of the top electrode 456, and the sidewall M1a of the metal layer M1.

According to the above description, the barrier layer covers the metal layer and surrounds the top electrode and the metal layer, so that the resistive random access memory cell can be perfectly protected from the back end process (for example, forming an intermetal dielectric) The gas generated by the process of the metal layer, the metal layer, and the protective layer (for example, hydrogen (H), ammonia (NH ₃ ), decane (SiH ₄ )). The barrier layer is formed after the metal layer is formed. The barrier layer can be formed directly on the metal layer. That is, the electrical connection between the metal layer and the top electrode can be interrupted by the barrier layer without forming an additional conductive structure between the metal layer and the top electrode. The process method of the present disclosure is simpler and faster than the comparative example in which the barrier layer is formed between the metal layer and the top electrode. Therefore, the resistive random access memory device of the present disclosure can have a lower The data storage loss and the better resistive random access memory reliability, and the manufacturing method of the resistive random access memory device of the present disclosure can be low in cost and time.

Other embodiments, such as known components of components, may have different arrangements and arrangements, and may be applied, depending on the actual needs and conditions of the application, and may be appropriately adjusted or changed. Therefore, the structures shown in the specification and drawings are for illustrative purposes only and are not intended to limit the scope of the disclosure. In addition, it is to be understood by those skilled in the art that the shapes and positions of the components in the embodiments are not limited to those illustrated in the drawings, and the requirements and/or manufacturing steps according to actual applications are not deviated from the spirit of the disclosure. In the case of the situation can be adjusted accordingly.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (10)

A resistive random access memory device includes: a bottom electrode; a resistance conversion layer disposed on the bottom electrode; a top electrode disposed on the resistance conversion layer; and a metal layer disposed on the top electrode And a barrier layer covering the metal layer, wherein the barrier layer surrounds the metal layer and the top electrode. The resistive random access memory device of claim 1, wherein the barrier layer comprises an oxynitride material. The resistive random access memory device according to claim 2, wherein the nitrogen oxide material is cerium oxynitride (SiON), titanium oxynitride (TiON) or titanium oxynitride (TiSiON). The resistive random access memory device of claim 1, wherein the barrier layer has a thickness in the range of 50 angstroms to 1000 angstroms. The resistive random access memory device of claim 1, further comprising: a substrate, wherein the bottom electrode is disposed on the substrate; a dielectric layer disposed on the substrate; An electrically conductive connection structure is disposed on the substrate and passes through the dielectric layer, wherein the dielectric layer has a top surface that continuously covers the top surface and the metal layer. A method of manufacturing a resistive random access memory device, comprising: forming an opening in an insulating layer; depositing a conductive material in the opening; removing the conductive material above the opening to form a bottom electrode; Forming a resistance conversion layer on the bottom electrode; forming a top electrode on the resistance conversion layer; forming a metal layer on the top electrode; and forming a barrier layer covering the metal layer, wherein the barrier layer surrounds the metal layer And the top electrode. The method of fabricating a resistive random access memory device according to claim 6, wherein the barrier layer comprises an oxynitride material. The method of manufacturing a resistive random access memory device according to claim 7, wherein the oxynitride material is cerium oxynitride (SiON), titanium oxynitride (TiON) or titanium oxynitride (TiSiON). . The method of manufacturing a resistive random access memory device according to claim 6, wherein the barrier layer has a thickness in the range of 50 angstroms to 1000 angstroms. The method for manufacturing a resistive random access memory device according to claim 6, further comprising: Forming a substrate before forming the bottom electrode, wherein the bottom electrode is formed on the substrate; forming a dielectric layer on the substrate; and forming a conductive connection structure on the substrate and passing through the dielectric layer, wherein The dielectric layer has a top surface that continuously covers the top surface and the metal layer.