CN102339780B - Adsorbing and supporting device of wafer and substrate and semiconductor processing equipment of wafer - Google Patents
Adsorbing and supporting device of wafer and substrate and semiconductor processing equipment of wafer Download PDFInfo
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- CN102339780B CN102339780B CN 201110298429 CN201110298429A CN102339780B CN 102339780 B CN102339780 B CN 102339780B CN 201110298429 CN201110298429 CN 201110298429 CN 201110298429 A CN201110298429 A CN 201110298429A CN 102339780 B CN102339780 B CN 102339780B
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Abstract
The invention provides a substrate for supporting a wafer. The substrate comprises a first surface and a second surface which are suitable for supporting the wafer to be processed, wherein the first surface is provided with a plurality of first pores; the second surface is provided with a plurality of grooves; and the grooves are not extended to the side wall of the substrate and are communicated with the first pores. The substrate and a vacuum chuck or an electrostatic chuck can form an adsorbing and supporting device of the wafer. During the processing of the wafer, the substrate can increase the mechanical strength of the wafer to ensure that the wafer can be processed into a semiconductor device with very thin thickness on the device, the semiconductor device can be easily separated from the device, and the device cannot be damaged during separation. The invention also provides the adsorbing and supporting device of the wafer comprising the substrate; moreover, the invention also provides semiconductor processing equipment comprising the adsorbing and supporting device of the wafer.
Description
Technical field
The present invention relates to the semiconductor processing equipment technical field.
Background technology
Obtain meeting the semiconductor device of dimensional requirement after the photoetching of pending wafer (Wafer) process, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma etching, ion injection, the chemico-mechanical polishing semiconductor technologies such as (CMP).When the thickness requirement of required device is thinner, for the mechanical strength that increases wafer to be processed so that the other problem that causes because of undercapacity in the follow-up course of processing, can not occur, way conventional in the prior art is: wafer to be processed and a supporting wafers are sticked together by gum, then they are fixed on and treat processed wafer on the vacuum cup of semiconductor processing equipment or the electrostatic chuck and carry out various semiconductor machining, treat after various the machining the device that forms to be separated with supporting wafers, the supporting wafers here is a wafer suitable with wafer size to be processed, need not form any semiconductor element in this wafer.
When the very thin thickness of required semiconductor device, because itself and supporting wafers are sticked together by gum, therefore be difficult to semiconductor device is separated with supporting wafers, though perhaps both separated but in separating process semiconductor device therefore produced some flaws, do not meet quality requirement.
Summary of the invention
The problem to be solved in the present invention provides a kind of liner for supporting wafers, this liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer, wafer can be processed to form the semiconductor device of very thin thickness on this device, and easily semiconductor device is separated, and in separating process, can not cause damage to device from described device.
For addressing the above problem, the invention provides a kind of liner for supporting wafers, comprising:
Be suitable for supporting the first surface of pending wafer;
Second surface;
Described first surface is provided with some first apertures;
Described second surface is provided with some grooves, and described groove does not extend to the sidewall of described liner, and described groove and the described first aperture conducting.
Optionally, described first aperture is shaped as cross.
Optionally, described first aperture be shaped as quincunx.
Optionally, described first aperture is spaced apart and formation rectangular array at the first surface of described liner, the Cutting Road of the corresponding pending wafer of the arrangement of rectangular array.
Optionally, described groove and all described first aperture conductings of arranging point-blank, described groove is criss-cross arrangement at the second surface of described liner.
Optionally, the material of described liner is electric conducting material.
Optionally, described electric conducting material is doped silicon.
Optionally, described liner first surface is provided with dielectric layer, and the position of corresponding described first aperture of described dielectric layer is provided with the 3rd aperture, the shape of described the 3rd aperture, big or small identical with described first aperture.
Optionally, described dielectric layer is the doping dielectric layer.
Optionally, the material of described dielectric layer is pottery.
Optionally, the thickness of the thickness of described liner and pending wafer is suitable.
Optionally, the shape sizableness of the shape of described liner size and pending wafer.
For addressing the above problem, the present invention also provides a kind of absorption and bracing or strutting arrangement of wafer, comprising:
Aforesaid liner;
Be suitable for supporting the vacuum cup of described liner, its surface is provided with some second apertures, described groove at least with the second aperture conducting of a described vacuum cup.
Optionally, each second aperture on the described vacuum cup and the groove conducting of described liner.
For addressing the above problem, the present invention also provides a kind of absorption and bracing or strutting arrangement of wafer, comprising:
Aforesaid liner;
Be suitable for supporting the electrostatic chuck of described liner.
For addressing the above problem, the present invention also provides a kind of semiconductor processing equipment, comprising:
Treatment chamber;
Be positioned at absorption and the bracing or strutting arrangement of described treatment chamber, aforesaid wafer;
Be suitable for processing unit (plant) that pending wafer is handled.
Compared with prior art, the invention has the advantages that:
One, liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer, this liner can increase the mechanical strength of wafer in the course of processing of wafer, thereby wafer can be processed to the semiconductor device of very thin thickness on this device, and easily semiconductor device is separated, and in separating process, can not cause damage to device from described device.
Two, liner can repeatedly use, and cuts the waste.
Three, this liner can use in multiple semiconductor processing equipment, applied range, and can under some special processing conditions, use, there is penetrating part as processed wafer.
Four, the size of this liner can be adjusted in actual applications, can adapt to the wafer of multiple dimensions.
Description of drawings
Fig. 1 is the vertical view of liner among the liner embodiment of the present invention.
Fig. 2 is the upward view of liner among the liner embodiment of the present invention.
Fig. 3 is that liner shown in Figure 1 is along the cutaway view of A-A direction.
Fig. 4 is that liner shown in Figure 1 is along the cutaway view of B-B direction.
Fig. 5 is that liner shown in Figure 1 is along the cutaway view of C-C direction.
Embodiment
The object of the present invention is to provide a kind of liner for supporting wafers, this liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer, this liner can increase the mechanical strength of wafer in the course of processing of wafer, thereby wafer can be processed to the semiconductor device of very thin thickness on this device, and easily semiconductor device is separated, and in separating process, can not cause damage to device from described device.
For achieving the above object, main design of the present invention is: liner is provided with aperture with the surface that pending wafer contacts, its surface that contacts with vacuum cup is provided with groove, and this groove and vacuum cup lip-deep hole conducting, when pending wafer places on the vacuum cup with liner, start the vacuum pump of vacuum cup equipment, vacuum pump is taken the air between pending wafer and the liner contact surface away the formation vacuum, pending like this wafer tightly is adsorbed on the vacuum cup by liner, just can carry out multiple semiconductor machining to obtain the semiconductor device of thinner thickness to pending wafer then.When vacuum pump fed gas to the hole in the vacuum cup, wafer, liner, vacuum cup after processing under the effect of gas pressure intensity were separated from each other, and wafer can not sustain damage in separating process.
Yet pending wafer needs to process under vacuum environment sometimes, and as the plasma implanter, at this moment vacuum cup can't be worked under vacuum environment, and therefore above-mentioned gasket construction can't continue to have adsorbed pending wafer with vacuum cup.According to the commonly used adsorbent equipment of semiconductor processing equipment as can be known, electrostatic chuck can adsorb wafer under vacuum environment, therefore the inventor considers to make some improvement at above-mentioned gasket construction, make it adsorb pending wafer with vacuum cup, also can adsorb pending wafer with electrostatic chuck.
The concrete improvement comprises: the material that makes liner is electric conducting material, deposit one deck dielectric layer on this pad surfaces then, and this dielectric layer is the doping dielectric layer, its material can be pottery.When the liner that is provided with dielectric layer with the surface when pending wafer places on the electrostatic chuck, electrostatic chuck is applied voltage, dielectric layer produces electric charge, be positioned at the opposite electric charge of wafer polarization on the dielectric layer, pending like this wafer is provided with dielectric layer by the surface liner tightly is adsorbed on the electrostatic chuck, just can carry out multiple semiconductor machining to pending wafer then; When electrostatic chuck was applied reverse voltage, pending wafer, liner, electrostatic chuck were separated from each other.Accordingly, can work with vacuum cup simultaneously for the liner that makes this surface be provided with dielectric layer, the position of the corresponding pad surfaces aperture of dielectric layer also arranges aperture.
In addition, characteristics according to the ion implantor platform: being fit to place thickness is the semiconductor structure of conventional die size, therefore, after wafer process is extremely very thin, inject processing if need to continue to carry out ion to wafer, then its with the surface be provided with dielectric layer liner the thickness sum should with wafer process before thickness suitable.And other semiconductor processing equipments do not require semiconductor structure thicknesses to be processed, for this gasket construction can be used in most semiconductor processing equipments, so that the present invention can make the surface be provided with the thickness of the thickness of liner of dielectric layer and pending wafer is suitable.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
The absorption of wafer and bracing or strutting arrangement comprise the liner 10 that is suitable for supporting pending wafer among the present invention, and to shown in Figure 5, it comprises as Fig. 1:
Be suitable for supporting first surface 11, the second surface 12 of pending wafer;
Be located at some first apertures 13 on the first surface 11;
Be located at some grooves 14 of second surface 12, groove 14 does not extend to the sidewall of liner 10 so that vacuum cup (not shown) can adsorbent pad 10, groove 14 and 13 conductings of first aperture.
Described device comprises vacuum cup in addition, and its surface is provided with some second apertures.
With pending wafer after liner 10 places on the vacuum cup surface, the second surface 12 of liner 10 contacts with the vacuum cup surface, make on the second surface 12 groove 14 at least with lip-deep second an aperture conducting of vacuum cup, start vacuum cup, vacuum pump successively by first aperture 13, the groove 14 with 13 conductings of first aperture, the extraction of second aperture, makes pending wafer be adsorbed and be fixed on the vacuum cup with liner 10 air between pending wafer and liner 10 first surfaces 11.Thereby so just can carry out multiple semiconductor machining to pending wafer and obtain required semiconductor device, when vacuum pump feeds gas to second aperture in the vacuum cup, gas is fed by second aperture that groove 14 with the second aperture conducting feeds again and first aperture 13 of groove 14 conductings, semiconductor device separates with liner under the effect of atmospheric pressure, and semiconductor device can not produce damage in separating process.
Especially when the semiconductor device very thin thickness, liner 10 can increase its mechanical strength and its processing carried out smoothly and it can be obtained satisfactory device after separating in its forming process.
When the wafer thickness after the processing is very thin, excessive so that wafer that adsorbed by vacuum cup forms in the position of corresponding first aperture 13 and subsides for the absorption affinity of avoiding vacuum cup, the shape of first aperture 13 can be cross or quincunx, compare its aperture area with circular aperture littler for the aperture of this shape when guaranteeing enough absorption affinities, reduce the possibility that wafer subsides, thereby improve the quality of wafer.It should be noted that for first aperture being described at the arrangement mode of pad surfaces and the general structure of whole liner, first hole shape among Fig. 1, Fig. 3, Fig. 4, Fig. 5 is circular, should not limit protection scope of the present invention with this.
Wafer is being added man-hour, processing technology comprises etching, therefore might can there be penetrating part by wafer, wafer in order to ensure this structure on the vacuum cup energy adsorbent pad, can make first aperture 13 spaced apart and formation rectangular array on first surface 11, the Cutting Road of the corresponding pending wafer of the arrangement of rectangular array.Corresponding, the groove 14 on liner 10 second surfaces 12 and arrangement all first aperture, 13 conductings point-blank are to increase absorption affinity, and groove 14 is criss-cross arrangement at the second surface 12 of liner 10 liners.Like this because can there be penetrating part in wafer cutting path, therefore even wafer is etched and forms penetrating part, the wafer of vacuum cup on still can adsorbent pad 10.At this moment, in order to increase absorption affinity, can make groove 14 and lip-deep all the second aperture conductings of vacuum cup, namely the arrangement mode of vacuum cup surface second aperture is identical with the arrangement mode of groove 14.
In concrete the application, in order to increase vacuum cup to the absorption affinity of liner, wafer and to prevent that vacuum cup can't work on when wafer is etched the penetrating part of formation, need vacuum cup, liner, wafer three are positioned aligning, for example can one small rut be set at vacuum cup, at the liner second surface one raised structures that can cooperate with described pit is set, both can realize rapid alignment like this; The liner sidewall one mark or marking structure are set so that on the liner first aperture aim at wafer cutting path, both can realize rapid alignment like this.
As mentioned above, sometimes pending wafer needs to process under vacuum environment, as the plasma implanter, at this moment can use electrostatic chuck to adsorb pending wafer by liner, therefore need above-mentioned gasket construction is improved so that the wafer of vacuum cup on can adsorbent pad 10, simultaneously the wafer of electrostatic chuck on also can adsorbent pad 10.
Making the material of liner 10 is electric conducting material, and doped silicon is a kind of good electric conducting material in the semiconductor applications, and can carry out Precision Machining to it and obtain required structure, so preferred doped silicon in the present embodiment, and metal material also can certainly.Be formed with dielectric layer at liner 10 first surfaces 11, liner 10 is placed on the electrostatic chuck with pending wafer, electrostatic chuck is applied voltage, the electrostatic chuck surface can produce electric charge, this charge generation electric field makes the opposite electric charge of second surface 12 polarizations of liner 10, because liner 10 is electric conducting material, dielectric layer can be subjected to the effect of voltage simultaneously, therefore dielectric layer also can produce electric charge, the electric charge of dielectric layer surface can produce electric field, this electric field makes the opposite electric charge of wafer surface polarization that places on the liner 10, and the principle electrostatic chuck of inhaling mutually according to the charges of different polarity is attached together liner 10 and wafer.Close the voltage that electrostatic chuck is applied, thereby can exist remaining electrostatic charge to make both continue to be attached together between liner 10 and the wafer.When applying reverse voltage to electrostatic chuck, electrostatic chuck, liner 10, wafer are separated from each other, can not produce damage to wafer in the separating process.Wherein, dielectric layer is the doping dielectric layer, and its material can be pottery.
In some special manufacture of semiconductor, as the BSI processing procedure, wafer is reduced to and can carries out ion implantation technology to it after very thin, and according to the characteristics of ion implantor platform: being fit to place thickness is the semiconductor structure of conventional die size, therefore, when being machined to very thin wafer and also need carrying out ion implantation technology, its with the surface be provided with dielectric layer liner the thickness sum should with wafer process before thickness suitable.And other semiconductor processing equipments do not require semiconductor structure thicknesses to be processed, can use in most semiconductor processing equipments in order to make this gasket construction, and it is suitable to make the surface be provided with the thickness of the thickness of liner of dielectric layer and pending wafer.Simultaneously, design feature and minimizing cost in order to be suitable for semiconductor processing equipment can make the size of liner and the sizableness of pending wafer.
For the liner after the above improvement can be applied on the vacuum cup simultaneously, the position of corresponding first aperture 13 is provided with the 3rd aperture on the dielectric layer, and its shape size is identical with first aperture 13.In actual manufacture process, the 3rd aperture can once form by same processing with first aperture 13.In actual applications, when pending wafer need carry out certain special semiconductor machining, have penetrating part as wafer, need make first aperture 13 on liner 10 first surfaces 11 aim at the Cutting Road of pending wafer this moment.
It should be noted that in actual applications, pad size needs according to the actual conditions adjustment among the present invention, need to adjust according to the wafer to be processed of its support as its thickness, diameter, so that the thickness of its thickness, diameter and wafer, diameter are suitable; The size of first aperture needs to adjust according to the wafer to be processed of its support, so that the full-size of first aperture is less than the width of wafer cutting path; Groove on the second surface needs to adjust according to the size of first aperture, so that the width of groove is greater than the full-size of first aperture.Corresponding, when utilizing vacuum cup that the wafer on the liner is adsorbed, in order to increase absorption affinity, need diameter, the arrangement mode of aperture on the vacuum cup surface are adjusted.
Compared with prior art, the present invention has the following advantages:
One, liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer, this liner can increase the mechanical strength of wafer in the course of processing of wafer, thereby wafer can be processed to the semiconductor device of very thin thickness on this device, and easily semiconductor device is separated, and in separating process, can not cause damage to device from described device.
Two, liner can repeatedly use, and cuts the waste.
Three, this liner can use in multiple semiconductor processing equipment, applied range, and can under some special processing processing conditions, use, there is penetrating part as processed wafer.
Four, the size of this liner can be adjusted in actual applications, can adapt to the wafer of multiple dimensions.
In addition, the present invention also provides a kind of semiconductor processing equipment, comprising:
Treatment chamber;
Be positioned at absorption and the bracing or strutting arrangement of described treatment chamber, aforesaid wafer;
Be suitable for processing unit (plant) that pending wafer is handled.
Though the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (16)
1. a liner that is used for supporting wafers is characterized in that, comprising:
Be suitable for supporting the first surface of pending wafer;
Second surface;
Described first surface is provided with some first apertures, and described first aperture is spaced apart and formation rectangular array at the first surface of described liner, the Cutting Road of the corresponding pending wafer of the arrangement of rectangular array;
Described second surface is provided with some grooves, and described groove does not extend to the sidewall of described liner, and described groove and the described first aperture conducting.
2. liner according to claim 1 is characterized in that, described first aperture be shaped as cross.
3. liner according to claim 1 is characterized in that, being shaped as of described first aperture is quincunx.
4. liner according to claim 1 is characterized in that, described groove and all described first aperture conductings of arranging point-blank, and described groove is criss-cross arrangement at the second surface of described liner.
5. liner according to claim 1 is characterized in that, the material of described liner is electric conducting material.
6. liner according to claim 5 is characterized in that, described electric conducting material is doped silicon.
7. liner according to claim 5 is characterized in that, its first surface is provided with dielectric layer, and the position of corresponding described first aperture of described dielectric layer is provided with the 3rd aperture, the shape of described the 3rd aperture, big or small identical with described first aperture.
8. liner according to claim 7 is characterized in that, described dielectric layer is the doping dielectric layer.
9. liner according to claim 7 is characterized in that, the material of described dielectric layer is pottery.
10. liner according to claim 7 is characterized in that, the thickness of described liner is suitable with the thickness of pending wafer.
11. liner according to claim 7 is characterized in that, the shape size of described liner and the shape sizableness of pending wafer.
12. the absorption of a wafer and bracing or strutting arrangement is characterized in that, comprising:
As each described liner of claim 1 to 11;
Be suitable for supporting the vacuum cup of described liner, its surface is provided with some second apertures, described groove at least with described some second apertures in a conducting.
13. the absorption of wafer according to claim 12 and bracing or strutting arrangement is characterized in that, each second aperture on the described vacuum cup and the groove conducting of described liner.
14. the absorption of a wafer and bracing or strutting arrangement is characterized in that, comprising:
As each described liner of claim 7 to 11;
Be suitable for supporting the electrostatic chuck of described liner.
15. a semiconductor processing equipment is characterized in that, comprising:
Treatment chamber;
Be positioned at described treatment chamber, as absorption and the bracing or strutting arrangement of claim 12 or 13 described wafers;
Be suitable for processing unit (plant) that pending wafer is handled.
16. a semiconductor processing equipment is characterized in that, comprising:
Treatment chamber;
Be positioned at absorption and the bracing or strutting arrangement of described treatment chamber, wafer as claimed in claim 14;
Be suitable for processing unit (plant) that pending wafer is handled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110298429 CN102339780B (en) | 2011-09-30 | 2011-09-30 | Adsorbing and supporting device of wafer and substrate and semiconductor processing equipment of wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110298429 CN102339780B (en) | 2011-09-30 | 2011-09-30 | Adsorbing and supporting device of wafer and substrate and semiconductor processing equipment of wafer |
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| Publication Number | Publication Date |
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| CN102339780A CN102339780A (en) | 2012-02-01 |
| CN102339780B true CN102339780B (en) | 2013-07-17 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI560794B (en) * | 2015-04-23 | 2016-12-01 | Advanced Semiconductor Eng | Semiconductor element carrier, method for attaching a semiconductor element to a carrier, and semiconductor process |
| CN105826211B (en) * | 2016-05-11 | 2018-10-19 | 苏州日月新半导体有限公司 | Semiconductor product, the jig and method for manufacturing the semiconductor product |
| CN107966886B (en) * | 2018-01-19 | 2020-07-14 | 京东方科技集团股份有限公司 | Heating device and photoetching equipment |
| CN109148309A (en) * | 2018-09-03 | 2019-01-04 | 苏州通富超威半导体有限公司 | Encapsulating structure and forming method thereof |
| CN110740556A (en) * | 2019-10-25 | 2020-01-31 | 上海华力微电子有限公司 | static eliminating device and method and electronic scanning microscope |
| CN114628240A (en) * | 2020-12-10 | 2022-06-14 | 武汉新芯集成电路制造有限公司 | Chip wafer stacking method |
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| JP3024384B2 (en) * | 1992-09-10 | 2000-03-21 | 富士通株式会社 | Method for manufacturing semiconductor device |
| US6342434B1 (en) * | 1995-12-04 | 2002-01-29 | Hitachi, Ltd. | Methods of processing semiconductor wafer, and producing IC card, and carrier |
| KR20100029802A (en) * | 2010-02-23 | 2010-03-17 | 주식회사 마이크로홀 | A vacuum pad for vacuum chuck and the manufacturing method of it |
| CN202307844U (en) * | 2011-09-30 | 2012-07-04 | 格科微电子（上海）有限公司 | A chip absorbing and supporting device, a liner of the chip absorbing and supporting device, and a semiconductor processing device having the chip absorbing and supporting device |
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