CN202307844U - A chip absorbing and supporting device, a liner of the chip absorbing and supporting device, and a semiconductor processing device having the chip absorbing and supporting device - Google Patents
A chip absorbing and supporting device, a liner of the chip absorbing and supporting device, and a semiconductor processing device having the chip absorbing and supporting device Download PDFInfo
- Publication number
- CN202307844U CN202307844U CN2011203725546U CN201120372554U CN202307844U CN 202307844 U CN202307844 U CN 202307844U CN 2011203725546 U CN2011203725546 U CN 2011203725546U CN 201120372554 U CN201120372554 U CN 201120372554U CN 202307844 U CN202307844 U CN 202307844U
- Authority
- CN
- China
- Prior art keywords
- liner
- wafer
- aperture
- chip
- supporting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The utility model provides a liner used for supporting a chip. The liner used for supporting the chip includes a first surface and a second surface together suitable for supporting the to-be-processed chip. The first surface is provided with a plurality of first small holes. The second surface is provided with a plurality of grooves. The grooves do not extend to side walls of the liner. And the grooves communicate with the first small holes. A chip absorbing and supporting device can be formed by the liner and a vacuum sucker or a static sucker. In a processing process of the chip, the liner can increase the mechanical strength of the chip. In this way, the chip can be processed into very thin semiconductor devices on the chip absorbing and supporting device, and the semiconductor devices can be separated from the chip absorbing and supporting device easily. No damage is made to the semiconductor devices in a separating process. The utility model also provides the chip absorbing and supporting device containing the liner. Besides, the utility model also provides a semiconductor processing device having the chip absorbing and supporting device.
Description
Technical field
The utility model relates to the semiconductor processing equipment technical field.
Background technology
Obtain meeting the semiconductor device of dimensional requirement after the photoetching of pending wafer (Wafer) process, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma etching, ion injection, the chemico-mechanical polishing semiconductor technologies such as (CMP).When the thickness requirement of required device approaches; For the mechanical strength that increases wafer to be processed so that the other problem that causes because of undercapacity in the follow-up course of processing, can not occur; Way conventional in the prior art is: wafer to be processed and a supporting wafers are sticked together through gum; Then they are fixed on and treat processed wafer on vacuum cup or the electrostatic chuck of semiconductor processing equipment and carry out various semiconductor machining; Treat after various the machining the device that forms to be separated with supporting wafers, the supporting wafers here is a wafer suitable with wafer size to be processed, need not form any semiconductor element in this wafer.
When the very thin thickness of required semiconductor device; Because itself and supporting wafers are sticked together through gum; Therefore be difficult to semiconductor device is separated with supporting wafers, though perhaps both separated but in separating process semiconductor device therefore produced some flaws, do not meet quality requirement.
The utility model content
The problem that the utility model will solve provides a kind of liner that is used for supporting wafers; This liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer; Wafer can be processed to form the semiconductor device of very thin thickness on this device; And easily semiconductor device is separated, and in separating process, can not cause damage to device from said device.
For addressing the above problem, the utility model provides a kind of liner that is used for supporting wafers, comprising:
Be suitable for supporting the first surface of pending wafer;
Second surface;
Said first surface is provided with some first apertures;
Said second surface is provided with some grooves, and said groove does not extend to the sidewall of said liner, and said groove and the said first aperture conducting.
Optional, said first aperture be shaped as cross.
Optional, being shaped as of said first aperture is quincunx.
Optional, said first aperture is spaced apart and formation rectangular array at the first surface of said liner, the Cutting Road of the corresponding pending wafer of the arrangement of rectangular array.
Optional, said groove and all said first aperture conductings of arranging point-blank, said groove is criss-cross arrangement on the second surface of said liner.
Optional, the material of said liner is an electric conducting material.
Optional, said electric conducting material is a doped silicon.
Optional, said liner first surface is provided with dielectric layer, and the position of corresponding said first aperture of said dielectric layer is provided with the 3rd aperture, the shape of said the 3rd aperture, big or small identical with said first aperture.
Optional, said dielectric layer is the doping dielectric layer.
Optional, the material of said dielectric layer is a pottery.
Optional, the thickness of said liner is suitable with the thickness of pending wafer.
Optional, the shape size of said liner and the shape sizableness of pending wafer.
For addressing the above problem, the utility model also provides a kind of absorption and bracing or strutting arrangement of wafer, comprising:
Aforesaid liner;
Be suitable for supporting the vacuum cup of said liner, its surface is provided with some second apertures, said groove at least with the second aperture conducting of a said vacuum cup.
Optional, each second aperture on the said vacuum cup and the groove conducting of said liner.
For addressing the above problem, the utility model also provides a kind of absorption and bracing or strutting arrangement of wafer, comprising:
Aforesaid liner;
Be suitable for supporting the electrostatic chuck of said liner.
For addressing the above problem, the utility model also provides a kind of semiconductor processing equipment, comprising:
Treatment chamber;
Be positioned at the absorption and the bracing or strutting arrangement of said treatment chamber, aforesaid wafer;
Be suitable for treating the processing unit (plant) that processing wafers is handled.
Compared with prior art, the advantage of the utility model is:
One, liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer; This liner can increase the mechanical strength of wafer in the course of processing of wafer; Thereby wafer can be processed to the semiconductor device of very thin thickness on this device; And easily semiconductor device is separated, and in separating process, can not cause damage to device from said device.
Two, liner can repeatedly use, and cuts the waste.
Three, this liner can use in multiple semiconductor processing equipment, applied range, and can under some special processing conditions, use, there is penetrating part like processed wafer.
Four, the size of this liner can be adjusted in practical application, can adapt to the wafer of multiple dimensions.
Description of drawings
Fig. 1 is the vertical view of liner among the utility model liner embodiment.
Fig. 2 is the upward view of liner among the utility model liner embodiment.
Fig. 3 is the cutaway view of liner shown in Figure 1 along the A-A direction.
Fig. 4 is the cutaway view of liner shown in Figure 1 along the B-B direction.
Fig. 5 is the cutaway view of liner shown in Figure 1 along the C-C direction.
Embodiment
The purpose of the utility model is to provide a kind of liner that is used for supporting wafers; This liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer; This liner can increase the mechanical strength of wafer in the course of processing of wafer; Thereby wafer can be processed to the semiconductor device of very thin thickness on this device, and easily semiconductor device is separated from said device, and in separating process, can not cause damage to device.
For realizing above-mentioned purpose; The main design of the utility model is: liner is provided with aperture with the surface that pending wafer contacts; Its surface that contacts with vacuum cup is provided with groove, and this groove and vacuum cup lip-deep hole conducting, when pending wafer places on the vacuum cup with liner; Start the vacuum pump of vacuum cup equipment; Vacuum pump is taken the air between pending wafer and the liner contact surface away the formation vacuum, and pending like this wafer tightly is adsorbed on the vacuum cup through liner, just can treat processing wafers then and carry out multiple semiconductor machining to obtain the semiconductor device of thinner thickness.When the hole of vacuum pump in vacuum cup fed gas, wafer, liner, vacuum cup after processing under the effect of gas pressure intensity were separated from each other, and wafer can not sustain damage in separating process.
Yet pending sometimes wafer needs under vacuum environment, to process, and like the plasma implanter, at this moment vacuum cup can't be worked under vacuum environment, and therefore above-mentioned gasket construction can't continue to have adsorbed pending wafer with vacuum cup.Adsorbent equipment according to semiconductor processing equipment is commonly used can be known; Electrostatic chuck can adsorb wafer under vacuum environment; Therefore the inventor considers on above-mentioned gasket construction, to make some improvement; Make it adsorb pending wafer, also can adsorb pending wafer with electrostatic chuck with vacuum cup.
The concrete improvement comprises: the material that makes liner is an electric conducting material, deposit one deck dielectric layer on this pad surfaces then, and this dielectric layer is the doping dielectric layer, its material can be pottery.When the liner that is provided with dielectric layer with the surface when pending wafer places on the electrostatic chuck; Electrostatic chuck is applied voltage; Dielectric layer produces electric charge; Be positioned at the opposite electric charge of wafer polarization on the dielectric layer, pending like this wafer is provided with dielectric layer through the surface liner tightly is adsorbed on the electrostatic chuck, just can treat processing wafers then and carry out multiple semiconductor machining; When electrostatic chuck was applied reverse voltage, pending wafer, liner, electrostatic chuck were separated from each other.Accordingly, can work with vacuum cup simultaneously for the liner that makes this surface be provided with dielectric layer, the position of the corresponding pad surfaces aperture of dielectric layer also is provided with aperture.
In addition; Characteristics according to the ion implantor platform: being fit to place thickness is the semiconductor structure of conventional die size; Therefore; After wafer process is extremely very thin, process if need continue to carry out the ion injection wafer, then it should be suitable with the thickness before the wafer process with the surperficial thickness sum that is provided with the liner of dielectric layer.And other semiconductor processing equipments do not require semiconductor structure thicknesses to be processed; For this gasket construction can be used in most semiconductor processing equipments, so it is suitable to make the surface be provided with the thickness of thickness and pending wafer of liner of dielectric layer in the utility model.
For above-mentioned purpose, the feature and advantage that make the utility model can be more obviously understandable, the embodiment of the utility model is done detailed explanation below in conjunction with accompanying drawing.
Set forth detail in the following description so that make much of the utility model.But the utility model can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of the utility model intension.Therefore the utility model does not receive the restriction of following disclosed embodiment.
The absorption of wafer and bracing or strutting arrangement comprise the liner 10 that is suitable for supporting pending wafer in the utility model, and to shown in Figure 5, it comprises like Fig. 1:
Be suitable for supporting first surface 11, the second surface 12 of pending wafer;
Be located at some first apertures 13 on the first surface 11;
Be located at some grooves 14 of second surface 12, groove 14 does not extend to the sidewall of liner 10 so that vacuum cup (not shown) can adsorbent pad 10, groove 14 and 13 conductings of first aperture.
Said device comprises vacuum cup in addition, and its surface is provided with some second apertures.
With pending wafer after liner 10 places on the vacuum cup surface; The second surface 12 of liner 10 contacts with the vacuum cup surface; Make on the second surface 12 groove 14 at least with lip-deep second an aperture conducting of vacuum cup; Start vacuum cup; Vacuum pump successively by first aperture 13, extract out with groove 14, second aperture of 13 conductings of first aperture, makes pending wafer be adsorbed and be fixed on the vacuum cup with liner 10 air between pending wafer and liner 10 first surfaces 11.Thereby so just can treat processing wafers carries out multiple semiconductor machining and obtains required semiconductor device; When second aperture of vacuum pump in vacuum cup feeds gas; Gas is fed by second aperture that groove 14 with the second aperture conducting feeds again and first aperture 13 of groove 14 conductings; Semiconductor device separates with liner under the effect of atmospheric pressure, and semiconductor device can not produce damage in separating process.
Especially when the semiconductor device very thin thickness, in its forming process liner 10 can increase its mechanical strength make its processing carry out smoothly and it is separated after can obtain satisfactory device.
When the wafer thickness after the processing is very thin; Excessive so that formed in the position of corresponding first aperture 13 by the wafer of vacuum cup absorption and to subside for the absorption affinity of avoiding vacuum cup; The shape of first aperture 13 can be cross or quincunx; Compare its aperture area with circular aperture littler for the aperture of this shape when guaranteeing enough absorption affinities, reduces possibility that wafer subsides, thus the quality of raising wafer.What need explanation is that in order first aperture to be described at the arrangement mode of pad surfaces and the general structure of whole liner, first hole shape among Fig. 1, Fig. 3, Fig. 4, Fig. 5 is circular, should not limit the protection range of the utility model with this.
Wafer is being added man-hour; Processing technology comprises etching; Therefore might can there be penetrating part by wafer; In order to ensure the wafer of this structure on the vacuum cup ability adsorbent pad, can make first aperture 13 spaced apart and formation rectangular array on first surface 11, the Cutting Road of the corresponding pending wafer of the arrangement of rectangular array.Corresponding, the groove 14 on liner 10 second surfaces 12 and arrangement all first aperture, 13 conductings point-blank are to increase absorption affinity, and groove 14 is criss-cross arrangement on the second surface 12 of liner 10 liners.Like this because can there be penetrating part in wafer cutting path, therefore even wafer is etched and forms penetrating part, the wafer of vacuum cup on still can adsorbent pad 10.At this moment, in order to increase absorption affinity, can make groove 14 and lip-deep all the second aperture conductings of vacuum cup, promptly the arrangement mode of vacuum cup surface second aperture is identical with the arrangement mode of groove 14.
In concrete the application; In order to increase vacuum cup to the absorption affinity of liner, wafer and prevent that vacuum cup can't work on when forming penetrating part when wafer is etched; Need vacuum cup, liner, wafer three are positioned aligning; For example a small rut can be set on vacuum cup, the raised structures that can cooperate with said pit is set on the liner second surface, both can realize rapid alignment like this; The liner sidewall one mark or marking structure are set so that on the liner first aperture aim at wafer cutting path, both can realize rapid alignment like this.
As stated; Sometimes pending wafer needs under vacuum environment, to process; Like the plasma implanter; Therefore at this moment can use electrostatic chuck to pass through liner and adsorb pending wafer, need above-mentioned gasket construction is improved so that the wafer of vacuum cup on can adsorbent pad 10, simultaneously the wafer of electrostatic chuck on also can adsorbent pad 10.
Making the material of liner 10 is electric conducting material, and doped silicon is a kind of good electric conducting material in the semiconductor applications, and can carry out Precision Machining to it and obtain required structure, so preferred doped silicon in the present embodiment, and metal material also can certainly.On liner 10 first surfaces 11, be formed with dielectric layer, liner 10 is placed on the electrostatic chuck with pending wafer, electrostatic chuck is applied voltage; The electrostatic chuck surface can produce electric charge; This charge generation electric field makes the opposite electric charge of second surface 12 polarizations of liner 10, because liner 10 is an electric conducting material, dielectric layer can receive the effect of voltage simultaneously; Therefore dielectric layer also can produce electric charge; The electric charge of dielectric layer surface can produce electric field, and this electric field makes the opposite electric charge of wafer surface polarization that places on the liner 10, and the principle electrostatic chuck of inhaling mutually according to the charges of different polarity is attached together liner 10 and wafer.Close the voltage that electrostatic chuck is applied, thereby can exist remaining electrostatic charge to make both continue to be attached together between liner 10 and the wafer.When electrostatic chuck applies reverse voltage, electrostatic chuck, liner 10, wafer are separated from each other, can not produce damage in the separating process to wafer.Wherein, dielectric layer is the doping dielectric layer, and its material can be pottery.
In some special manufacture of semiconductor; Like the BSI processing procedure; Wafer is reduced to and can carries out ion implantation technology to it after very thin, and according to the characteristics of ion implantor platform: being fit to place thickness is the semiconductor structure of conventional die size, therefore; When being machined to very thin wafer and also need carrying out ion implantation technology, it is provided with the thickness sum of the liner of dielectric layer with the surface should be suitable with the thickness before the wafer process.And other semiconductor processing equipments do not require semiconductor structure thicknesses to be processed, can in most semiconductor processing equipments, use in order to make this gasket construction, and it is suitable to make the surface be provided with the thickness of thickness and pending wafer of liner of dielectric layer.Simultaneously, design feature and minimizing cost in order to be suitable for semiconductor processing equipment can make the size of liner and the sizableness of pending wafer.
For the liner after the above improvement can be applied on the vacuum cup simultaneously, the position of corresponding first aperture 13 is provided with the 3rd aperture on the dielectric layer, and its shape size is identical with first aperture 13.In actual manufacture process, the 3rd aperture can once form through same processing with first aperture 13.In practical application, when pending wafer need carry out certain special semiconductor machining, there is penetrating part like wafer, need make first aperture 13 on liner 10 first surfaces 11 aim at the Cutting Road of pending wafer this moment.
What need explanation is, in practical application, pad size needs according to the actual conditions adjustment in the utility model, needs to adjust according to the wafer to be processed of its support like its thickness, diameter, so that the thickness of its thickness, diameter and wafer, diameter are suitable; The size of first aperture needs to adjust according to the wafer to be processed of its support, so that the full-size of first aperture is less than the width of wafer cutting path; Groove on the second surface needs to adjust according to the size of first aperture, so that the width of groove is greater than the full-size of first aperture.Corresponding, when utilizing vacuum cup that the wafer on the liner is adsorbed,, need diameter, the arrangement mode of aperture on the vacuum cup surface are adjusted in order to increase absorption affinity.
Compared with prior art, the utlity model has following advantage:
One, liner and vacuum cup or electrostatic chuck all can constitute a kind of absorption and bracing or strutting arrangement of wafer; This liner can increase the mechanical strength of wafer in the course of processing of wafer; Thereby wafer can be processed to the semiconductor device of very thin thickness on this device; And easily semiconductor device is separated, and in separating process, can not cause damage to device from said device.
Two, liner can repeatedly use, and cuts the waste.
Three, this liner can use in multiple semiconductor processing equipment, applied range, and can under some special processing processing conditions, use, there is penetrating part like processed wafer.
Four, the size of this liner can be adjusted in practical application, can adapt to the wafer of multiple dimensions.
In addition, the utility model also provides a kind of semiconductor processing equipment, comprising:
Treatment chamber;
Be positioned at the absorption and the bracing or strutting arrangement of said treatment chamber, aforesaid wafer;
Be suitable for treating the processing unit (plant) that processing wafers is handled.
Though the utility model with preferred embodiment openly as above; But it is not to be used for limiting the utility model; Any those skilled in the art are in spirit that does not break away from the utility model and scope; Can utilize the method and the technology contents of above-mentioned announcement that the utility model technical scheme is made possible change and modification, therefore, every content that does not break away from the utility model technical scheme; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of the utility model technical scheme according to the technical spirit of the utility model.
Claims (17)
1. a liner that is used for supporting wafers is characterized in that, comprising:
Be suitable for supporting the first surface of pending wafer;
Second surface;
Said first surface is provided with some first apertures;
Said second surface is provided with some grooves, and said groove does not extend to the sidewall of said liner, and said groove and the said first aperture conducting.
2. liner according to claim 1 is characterized in that, said first aperture be shaped as cross.
3. liner according to claim 1 is characterized in that being shaped as of said first aperture is quincunx.
4. liner according to claim 1 is characterized in that, said first aperture is spaced apart and formation rectangular array at the first surface of said liner, the Cutting Road of the corresponding pending wafer of the arrangement of rectangular array.
5. liner according to claim 4 is characterized in that, said groove and all said first aperture conductings of arranging point-blank, and said groove is criss-cross arrangement on the second surface of said liner.
6. liner according to claim 1 is characterized in that, the material of said liner is an electric conducting material.
7. liner according to claim 6 is characterized in that, said electric conducting material is a doped silicon.
8. liner according to claim 6 is characterized in that, said liner first surface is provided with dielectric layer, and the position of corresponding said first aperture of said dielectric layer is provided with the 3rd aperture, the shape of said the 3rd aperture, big or small identical with said first aperture.
9. liner according to claim 8 is characterized in that, said dielectric layer is the doping dielectric layer.
10. liner according to claim 8 is characterized in that, the material of said dielectric layer is a pottery.
11. liner according to claim 8 is characterized in that, the thickness of said liner is suitable with the thickness of pending wafer.
12. liner according to claim 8 is characterized in that, the shape size of said liner and the shape sizableness of pending wafer.
13. the absorption of a wafer and bracing or strutting arrangement is characterized in that, comprising:
Like each described liner of claim 1 to 12;
Be suitable for supporting the vacuum cup of said liner, its surface is provided with some second apertures, said groove at least with said some second apertures in a conducting.
14. the absorption of wafer according to claim 13 and bracing or strutting arrangement is characterized in that, each second aperture on the said vacuum cup and the groove conducting of said liner.
15. the absorption of a wafer and bracing or strutting arrangement is characterized in that, comprising:
Like each described liner of claim 6 to 12;
Be suitable for supporting the electrostatic chuck of said liner.
16. a semiconductor processing equipment is characterized in that, comprising:
Treatment chamber;
Be positioned at said treatment chamber, like the absorption and the bracing or strutting arrangement of claim 13 or 14 described wafers;
Be suitable for treating the processing unit (plant) that processing wafers is handled.
17. a semiconductor processing equipment is characterized in that, comprising:
Treatment chamber;
Be positioned at the absorption and the bracing or strutting arrangement of said treatment chamber, wafer as claimed in claim 15;
Be suitable for treating the processing unit (plant) that processing wafers is handled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203725546U CN202307844U (en) | 2011-09-30 | 2011-09-30 | A chip absorbing and supporting device, a liner of the chip absorbing and supporting device, and a semiconductor processing device having the chip absorbing and supporting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203725546U CN202307844U (en) | 2011-09-30 | 2011-09-30 | A chip absorbing and supporting device, a liner of the chip absorbing and supporting device, and a semiconductor processing device having the chip absorbing and supporting device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202307844U true CN202307844U (en) | 2012-07-04 |
Family
ID=46376685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203725546U Expired - Lifetime CN202307844U (en) | 2011-09-30 | 2011-09-30 | A chip absorbing and supporting device, a liner of the chip absorbing and supporting device, and a semiconductor processing device having the chip absorbing and supporting device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202307844U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339780A (en) * | 2011-09-30 | 2012-02-01 | 格科微电子（上海）有限公司 | Adsorbing and supporting device of wafer and substrate and semiconductor processing equipment of wafer |
| CN105158568A (en) * | 2015-08-28 | 2015-12-16 | 广州市昆德科技有限公司 | Capacitance-charging-discharging-principle-based semiconductor resistivity surveying instrument and surveying method |
| CN109037109A (en) * | 2018-08-03 | 2018-12-18 | 德淮半导体有限公司 | A kind of method of semiconductor equipment and cleaning wafer |
| CN110911330A (en) * | 2018-09-14 | 2020-03-24 | 东莞市中麒光电技术有限公司 | Sucker and method for transferring and fixing LED chips in batches by transferring wafers |
-
2011
- 2011-09-30 CN CN2011203725546U patent/CN202307844U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339780A (en) * | 2011-09-30 | 2012-02-01 | 格科微电子（上海）有限公司 | Adsorbing and supporting device of wafer and substrate and semiconductor processing equipment of wafer |
| CN105158568A (en) * | 2015-08-28 | 2015-12-16 | 广州市昆德科技有限公司 | Capacitance-charging-discharging-principle-based semiconductor resistivity surveying instrument and surveying method |
| CN105158568B (en) * | 2015-08-28 | 2018-03-02 | 广州市昆德科技有限公司 | Semiconductor resistor rate surveying instrument and mapping method based on capacitor charge and discharge principle |
| CN109037109A (en) * | 2018-08-03 | 2018-12-18 | 德淮半导体有限公司 | A kind of method of semiconductor equipment and cleaning wafer |
| CN110911330A (en) * | 2018-09-14 | 2020-03-24 | 东莞市中麒光电技术有限公司 | Sucker and method for transferring and fixing LED chips in batches by transferring wafers |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102339780B (en) | Adsorbing and supporting device of wafer and substrate and semiconductor processing equipment of wafer | |
| CN202307844U (en) | A chip absorbing and supporting device, a liner of the chip absorbing and supporting device, and a semiconductor processing device having the chip absorbing and supporting device | |
| TWI584477B (en) | Dummy fin formation by gas cluster ion beam | |
| US10680078B2 (en) | Semiconductor arrangement and formation thereof | |
| CN100505206C (en) | Static cupule for vacuum processing device, vacuum processing device with the same, and its manufacturing method | |
| US20120276658A1 (en) | Method of etching a workpiece | |
| US20110115047A1 (en) | Semiconductor process using mask openings of varying widths to form two or more device structures | |
| US8575680B2 (en) | Semiconductor device having air gap and method of fabricating the same | |
| KR20140012727A (en) | Methods and apparatus for conformal doping | |
| CN103681836A (en) | Vertical microelectronic component and corresponding production method | |
| US20020151138A1 (en) | Method for fabricating an NROM | |
| US9093367B2 (en) | Methods of forming doped regions in semiconductor substrates | |
| US11764099B2 (en) | Patterned chuck for double-sided processing | |
| CN102610634A (en) | Semiconductor device and method of manufacturing semiconductor device | |
| CN109786381B (en) | Memory element and manufacturing method thereof | |
| US7824975B2 (en) | Method of fabricating semiconductor device having gate spacer layer with uniform thickness | |
| CN102779849A (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN109671674A (en) | The production method of semiconductor device | |
| US20130023112A1 (en) | Methods for post dopant implant purge treatment | |
| CN104051344B (en) | Semiconductor arrangement and formation thereof | |
| KR20000034831A (en) | Method of forming a buried plate | |
| WO2007133604B1 (en) | Method for forming a semiconductor on insulator structure | |
| US9337314B2 (en) | Technique for selectively processing three dimensional device | |
| CN112331717A (en) | Thyristor surge suppressor with low capacitance and low residual voltage and manufacturing method thereof | |
| CN102332401B (en) | MOS device formation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20120704 Effective date of abandoning: 20130717 |
|
| RGAV | Abandon patent right to avoid regrant |