CN104051344B - And forming a semiconductor arrangement - Google Patents

And forming a semiconductor arrangement Download PDF

Info

Publication number
CN104051344B
CN104051344B CN 201410095738 CN201410095738A CN104051344B CN 104051344 B CN104051344 B CN 104051344B CN 201410095738 CN201410095738 CN 201410095738 CN 201410095738 A CN201410095738 A CN 201410095738A CN 104051344 B CN104051344 B CN 104051344B
Authority
CN
Grant status
Grant
Patent type
Application number
CN 201410095738
Other languages
Chinese (zh)
Other versions
CN104051344A (en )
Inventor
亚历克斯·卡尔尼茨基
郑光茗
周建志
朱振梁
段孝勤
Original Assignee
台湾积体电路制造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Abstract

提供一种半导体布置和形成方法。 A semiconductor arrangement and method of forming. 半导体形成方法包括:使用单一光刻胶以掩蔽将形成低压器件的区域以及高压器件的栅极结构,同时执行高压器件的高能量注入。 A method of forming a semiconductor comprising: a photoresist using a single high voltage device region and a gate structure to form low-voltage devices of the mask while performing a high energy implantation of high-voltage devices. 半导体制造的另一种方法包括:通过图案化的光刻胶执行高压器件的高能量注入,其中,在形成高压器件的栅极结构之前并且在形成低压器件的栅极结构之前,光刻胶被图案化。 Another method of manufacturing a semiconductor comprising: a high voltage device by performing a patterned photoresist high energy implantation, wherein, prior to forming the gate structure is formed in the high voltage device and the low-side device before the gate structure, photoresist is patterning. 在执行高能量注入之后,执行随后处理以形成高压器件和低压器件。 After performing a high energy implantation, subsequent process is performed to form the high-voltage and low-voltage devices. 从而在CMOS处理中形成高压器件和低压器件而不需要附加掩模。 Thereby forming a high-voltage and low-voltage CMOS devices without the need for additional mask process.

Description

半导体布置及其形成 And forming a semiconductor arrangement

技术领域 FIELD

[0001] 本发明总的来说涉及半导体领域,更具体地,涉及一种半导体布置及其形成方法。 [0001] The present invention generally relates to the field of semiconductors, and more particularly, to a semiconductor arrangement and method of forming.

背景技术 Background technique

[0002] 在诸如晶体管的半导体器件中,当将足够电压或偏压施加至器件的栅极时,电流流过源极区和漏极区之间的沟道区。 [0002] In the semiconductor device such as a transistor, or when a sufficient bias voltage is applied to the gate of the device, current flows through the channel region between the source and drain regions. 当电流流过沟道区时,器件通常被认为处于"接通"状态,并且当电流不流过沟道区时,器件通常被认为处于"关闭"状态。 When a current flows through the channel region, the device is generally considered to be in "ON" state, and when the current does not flow through the channel region, the device is generally considered to be in "off" state.

发明内容 SUMMARY

[0003] 根据本发明的一个方面,提供了一种半导体制造方法,包括:形成具有第一工作电压的多个第一晶体管,多个第一晶体管包括在衬底的第一晶体管区域之上的多个第一栅极结构、邻近多个第一栅极结构的多个低压浅阱、以及邻近多个第一栅极结构的多个低压口袋注入区;以及邻近多个第一晶体管形成具有第二工作电压的多个第二晶体管。 [0003] In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor, comprising: forming a first plurality of transistors having a first operating voltage, the first plurality of transistors included in the transistor region over the first substrate, a plurality of low-pressure pocket implantation region first plurality of gate structures, a plurality of low pressure adjacent the shallow well of the first plurality of gate structures, and adjacent the first plurality of gate structures; and adjacent the first plurality of transistors are formed having a second plurality of two transistors operating voltage. 形成多个第二晶体管包括:在多个第一栅极结构之上、在第一晶体管区域之上并且在多个第二栅极结构之上形成第一高压光刻胶,多个第二栅极结构在衬底的第二晶体管区域之上,使得暴露邻近多个第二栅极结构的衬底的多个高压注入区和多个第二栅极结构的多个第二栅极顶部;以第一高能量执行高压LDD注入,以将第一高压掺杂物注入到多个高压注入区中,从而形成邻近多个第二栅极结构的多个高压浅阱;以及以第二高能量执行高压口袋注入,以将第二高压掺杂物注入到多个高压注入区中,从而形成邻近多个第二栅极结构的多个高压口袋注入区。 Forming a second plurality of transistors comprises: a first gate structure over a plurality of, and forming a first photoresist over a plurality of high voltage gate structure over a second region of the first transistor, a second plurality of gate a plurality of second electrode structure over the transistor region of the substrate, so that the substrate adjacent to the gate structure of a second plurality of exposed areas and a plurality of high-pressure injection plurality of the second gate structure of the top of the second gate electrode; to performing a first high-voltage LDD implantation of high energy, high voltage to a first dopant implanted into the plurality of high-pressure injection zone, thereby forming a plurality of high pressure adjacent a second plurality of gate structures shallow well; and performing a second high energy high-pressure pocket implantation, a high pressure to a second plurality of dopant implanted into the high-pressure injection zone, thereby forming a plurality of high-pressure pocket implantation region adjacent to a second plurality of gate structures.

[0004] 优选地,形成多个第一晶体管包括:在第二晶体管区域之上并且在多个第二栅极结构之上形成低压光刻胶,使得暴露多个第一栅极结构和邻近多个第一栅极结构的衬底的多个低压注入区;以第一低能量执行低压LDD注入,以将第一电压掺杂物注入到多个低压注入区中,从而形成多个低压浅阱;以及以第二低能量执行低压口袋注入,以将第二低压掺杂物注入到多个低压注入区中,从而形成多个低压口袋注入区。 [0004] Preferably, a plurality of first transistors comprising: forming a low pressure and a second photoresist over the plurality of transistor gate structure over the second region, such that the first plurality of gate structures is exposed and an adjacent multi- a plurality of low-pressure injection region of the substrates of the first gate structure; performing a first low-voltage LDD implantation energy low, voltage to a first dopant implanted into the plurality of low-pressure injection region, thereby forming a plurality of shallow low pressure wells ; and performing a second low-pressure pocket implantation at low energy, low pressure to a second dopant implanted into the plurality of low-pressure injection region, thereby forming a plurality of low-pressure pocket implantation region.

[0005] 优选地,该方法包括:在衬底之上形成第一层栅极介电材料;从衬底的第一晶体管区域去除第一层栅极介电材料,使得高压栅极电介质的第一部分留在衬底的第二晶体管区域之上;在衬底之上并且在高压栅极电介质的第一部分之上形成第二层栅极介电材料,使得低压栅极电介质留在衬底的第一晶体管区域之上,并且高压栅极电介质留在衬底的第二晶体管区域之上,其中,高压栅极电介质包括第一部分和来自第二层栅极介电材料的第二部分;在低压栅极电介质和高压栅极电介质之上形成栅电极材料层;以及图案化层栅电极材料层、低压栅极电介质和高压栅极电介质,以同时形成多个第一栅极结构和多个第二栅极结构。 [0005] Preferably, the method comprising: forming a first layer of gate dielectric material over the substrate; removing the first layer of gate dielectric material from the first transistor region of the substrate, such that the first high voltage gate dielectric leaving a portion of a second transistor over the region of the substrate; and forming a second layer of gate dielectric material over the first portion of the high voltage gate dielectric over the substrate, such that the low-voltage gate dielectric to remain in the first substrate, over a transistor region, and the high pressure left a gate dielectric over the second transistor region of the substrate, wherein the gate dielectric comprises a first high-pressure portion and a second portion from the second layer of gate dielectric material; low pressure gate medium and high-voltage electric pole above the gate dielectric layer, forming a gate electrode material; layer and patterning the gate electrode material layer, the low-pressure and high-pressure gate dielectric the gate dielectric to form a first plurality of gate structures and a plurality of second gate simultaneously pole structure.

[0006] 优选地,该方法包括:在多个第一栅极结构、多个第二栅极结构和衬底之上形成侧壁材料层;以及图案化侧壁材料层,以同时形成邻近多个第一栅极结构的多个第一侧壁隔离物和邻近第二栅极结构的多个第二侧壁隔离物。 [0006] Preferably, the method comprising: a first plurality of gate structures, a plurality of second gate structure and sidewall material over a substrate layer; sidewall material and patterning the layer to simultaneously form multiple adjacent a plurality of first sidewall spacers and a plurality of second gate structure adjacent the first gate structure of the second sidewall spacers.

[0007] 优选地,执行低压口袋注入包括:通过所选额定电压,注入在器件制造中使用的剂量。 [0007] Preferably, performing a low pressure pocket implantation comprising: a selected rated voltage, implant dose used in device fabrication.

[0008] 优选地,多个第一晶体管与多个第二晶体管的类型不同。 [0008] Preferably, the plurality of first type transistors and a plurality of second transistors are different.

[0009] 优选地,执行高压LDD注入包括:注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 [0009] Preferably, the high-pressure performs LDD implant comprising: injecting boron, phosphorous, at least one of arsenic, antimony, boron, boron fluoride, nitrogen or carbon.

[0010] 优选地,执行高压口袋注入包括:注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 [0010] Preferably, performing a high-pressure pocket implantation comprising: injecting boron, phosphorous, at least one of arsenic, antimony, boron, boron fluoride, nitrogen or carbon. Won] 根据本发明的另一方面,提供了一种半导体制造方法,包括:在衬底的第一晶体管区域和衬底的第二晶体管区域之上形成第一高压光刻胶;图案化第一高压光刻胶,以形成第一晶体管区域之上的高压光刻胶和第二晶体管区域之上的多个高压残留光刻胶,使得暴露邻近多个高压残留光刻胶的衬底的多个高压注入区;以第一高能量执行高压LDD注入,以将第一高压掺杂物注入到多个高压注入区中,从而形成邻近多个高压残留光刻胶的多个高压浅阱;以及以第二高能量执行高压口袋注入,以将第二高压掺杂物注入到多个高压注入区中,从而形成邻近多个高压残留光刻胶的多个高压口袋注入区。 Won] According another aspect of the present invention, there is provided a method for manufacturing a semiconductor, comprising: forming a first photoresist on the second high-voltage transistor region of the first transistor and the substrate region of the substrate; a first patterning resist high pressure, high pressure to form a photoresist over the first high voltage transistor regions and a plurality of photoresist remaining on the second transistor region, so that a plurality of high pressure adjacent the remaining photoresist exposing the substrate a plurality of high-pressure injection zone; performing a first high energy to a high pressure LDD implantation, a high pressure to a first dopant implanted into the plurality of high-pressure injection zone, thereby forming a plurality of shallow wells adjacent to a plurality of high-pressure high-pressure residual photoresist; and to performing a second high-energy high-pressure pocket implantation, a high pressure to a second plurality of dopant implanted into the high-pressure injection zone, thereby forming a plurality of high pressure near the high pressure residual photoresist plurality of pocket implantation region.

[0012] 优选地,该方法包括:形成第一晶体管区域中的多个第一栅极结构和第二晶体管区域中的多个第二栅极结构;在多个第一栅极结构和多个第二栅极结构之上形成第一低压光刻胶;图案化第一低压光刻胶,以在第二晶体管区域之上和多个第二栅极结构之上形成低压光刻胶,使得暴露多个第一栅极结构和邻近多个第一栅极结构的衬底的多个低压注入区;以第一低能量执行低压LDD注入,以将第一低压掺杂物注入到多个低压注入区中,从而形成邻近多个第一栅极结构的多个低压浅阱;以及以第二低能量执行低压口袋注入,以将第二低压掺杂物注入到多个低压注入区中,从而形成邻近多个第一栅极结构的多个低压口袋注入区。 [0012] Preferably, the method comprising: forming a first plurality of gate structures and a plurality of second gate structure of a first transistor in the second region of the transistor region; and a plurality of a first plurality of gate structures a second gate structure formed over a first low-pressure photoresist; patterning a first photoresist low pressure to above the transistor region over the second gate structure is formed and a plurality of second low pressure photoresist exposure such that a plurality of low-pressure injection region of the first plurality of substrate adjacent the gate structure and the first plurality of gate structures; performing a first low energy implantation LDD low pressure, low pressure to a first dopant implanted into the plurality of low-pressure injection region, thereby forming a plurality of first gate structures adjacent to the plurality of low voltage shallow wells; and performing a second low-pressure pocket implantation energy low, to the second low dopant implanted into the plurality of low-pressure injection zone, thereby forming a plurality of low pressure adjacent the pocket implantation region of the first plurality of gate structures.

[0013] 优选地,该方法包括:在衬底之上形成第一层栅极介电材料;从衬底的第一晶体管区域去除第一层栅极介电材料,使得高压栅极电介质的第一部分留在衬底的第二晶体管区域之上;在衬底之上并且在高压栅极电介质的第一部分之上形成第二层栅极介电材料,使得低压栅极电介质留在衬底的第一晶体管区域之上,并且高压栅极电介质留在衬底的第二晶体管区域之上,其中,高压栅极电介质包括第一部分和来自第二层栅极介电材料的第二部分;在低压栅极电介质之上和高压栅极电介质之上形成一层栅电极材料;以及图案化栅电极材料层、低压栅极电介质和高压栅极电介质,以同时形成多个第一栅极结构和多个第二栅极结构。 [0013] Preferably, the method comprising: forming a first layer of gate dielectric material over the substrate; removing the first layer of gate dielectric material from the first transistor region of the substrate, such that the first high voltage gate dielectric leaving a portion of a second transistor over the region of the substrate; and forming a second layer of gate dielectric material over the first portion of the high voltage gate dielectric over the substrate, such that the low-voltage gate dielectric to remain in the first substrate, over a transistor region, and the high pressure left a gate dielectric over the second transistor region of the substrate, wherein the gate dielectric comprises a first high-pressure portion and a second portion from the second layer of gate dielectric material; low pressure gate -electrode over the gate dielectric over the dielectric layer forming a high pressure and a gate electrode material; and patterning the gate electrode material layer, the low-pressure and high-pressure gate dielectric the gate dielectric, to simultaneously form a plurality of first gate structure and a plurality of two gate structures.

[00M] 优选地,该方法包括:在多个第一栅极结构、多个第二栅极结构和衬底之上形成侧壁材料层;以及图案化侧壁材料层,以同时形成邻近多个第一栅极结构的多个第一侧壁隔离物和邻近多个第二栅极结构的多个第二侧壁隔离物。 [00M] Preferably, the method comprising: a first plurality of gate structures, a plurality of second gate structure and sidewall material over a substrate layer; sidewall material and patterning the layer to simultaneously form multiple adjacent a plurality of first gate structure and a plurality of first sidewall spacers adjacent the gate structure of a second plurality of second sidewall spacers.

[0015] 优选地,执行低压口袋注入包括:通过所选额定电压,注入在器件制造中使用的剂量。 [0015] Preferably, performing a low pressure pocket implantation comprising: a selected rated voltage, implant dose used in device fabrication.

[0016] 优选地,多个低压口袋注入区与多个高压口袋注入区的类型不同。 [0016] Preferably, a plurality of low-pressure type pocket implantation region and a plurality of different high-pressure pocket implantation region.

[0017] 优选地,执行高压LDD注入包括:注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种;和/或执行高压口袋注入包括:注入硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 [0017] Preferably, the high-pressure performs LDD implant comprising: boron is implanted, at least one phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen, and carbon; and / or performing a high-pressure pocket implantation comprising: implanting boron, phosphorus, arsenic, antimony, at least one of boron, boron fluoride, nitrogen or carbon.

[0018] 优选地,执行高压LDD注入包括:以基本垂直于衬底的表面的角度注入第一高压掺杂物;和/或执行高压口袋注入包括:以基本垂直于衬底的表面的角度注入第二高压掺杂物。 [0018] Preferably, the high-pressure performs LDD implant comprising: an angle substantially perpendicular to the injection surface of the substrate a first dopant high pressure; and / or performing a high-pressure pocket implantation comprising: an angle substantially perpendicular to the injection surface of the substrate The second high pressure dopant.

[0019] 根据本发明的又一方面,提供了一种注入掺杂物的方法,包括:在栅极结构之上沉积光刻胶,栅极结构位于衬底之上;图案化光刻胶,使得光刻胶在栅极结构的部分顶面而不是所有顶面之上,使得光刻胶的光刻胶宽度小于栅极结构的栅极结构宽度;以及在光刻胶在栅极结构之上时,将第一掺杂物注入到衬底中,以邻近栅极结构在衬底中形成第一掺杂区。 [0019] According to another aspect of the present invention, there is provided a method of dopant implantation, comprising: depositing a photoresist over the gate structure, a gate structure is disposed over the substrate; patterned photoresist, photoresist such that portions over the top surface of the gate structure instead of all the top surface of the photoresist such that the photoresist is smaller than the width of the gate structure width of the gate structure; and a photoresist over the gate structure when the first dopant implanted into the substrate adjacent to the gate structure to form a first doped region in the substrate.

[0020] 优选地,该方法包括:在光刻胶在栅极结构之上时,将第二掺杂物注入到衬底中, 以邻近栅极结构在衬底中形成第二掺杂区。 [0020] Preferably, the method comprising: when a photoresist over the gate structure and implanting a second dopant into the substrate adjacent to the gate structure to form a second doped region in the substrate.

[0021] 优选地,注入第一掺杂物包括:注入磷、砷、硼、氮或碳中的至少一种;和/或注入第二掺杂物包括:注入磷、砷、硼、氮或碳中的至少一种。 [0021] Preferably, the implanted first dopant comprises: injecting at least one phosphorus, arsenic, boron, nitrogen, and carbon; and / or implanting a second dopant comprises: implanting phosphorus, arsenic, boron, nitrogen, or at least one carbon.

[0022] 优选地,注入第一掺杂物包括:以基本垂直于衬底的顶面的角度注入第一掺杂物; 和/或注入第一掺杂物包括:以基本不垂直于衬底的顶面的角度注入第一掺杂物。 [0022] Preferably, the first dopant implantation comprising: a first implanted dopant substantially perpendicular to the angle of the top surface of the substrate; and / or implanting a first dopant comprising: substantially perpendicular to the substrate the angle of the top surface of the first dopant implantation.

附图说明 BRIEF DESCRIPTION

[0023] 当阅读附图时,通过以下详细说明最好地理解本发明的多个方面。 [0023] When reading the accompanying drawings, the following detailed description are best understood aspects of the present invention. 注意,根据工业中的标准实践,多种部件不按比例绘制。 Note that, in accordance with standard practice in the industry, various features are not drawn to scale. 实际上,为了论述的清楚起见,多种部件的尺寸可以任意地增大或减小。 Indeed, for clarity of discussion, various dimensions of the components may be arbitrarily increased or decreased.

[0024] 图1是示出根据一些实施例的半导体制造方法的流程图。 [0024] FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor some embodiments.

[0025] 图2是示出根据一些实施例的半导体制造方法的流程图。 [0025] FIG 2 is a flowchart illustrating a method of manufacturing a semiconductor some embodiments.

[0026] 图3是根据一些实施例的半导体布置的图解。 [0026] FIG. 3 is an illustration of some embodiments of the semiconductor arrangement.

[0027] 图4是根据一些实施例的半导体布置的图解。 [0027] FIG. 4 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0028] 图5是根据一些实施例的半导体布置的图解。 [0028] FIG. 5 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0029] 图6是根据一些实施例的半导体布置的图解。 [0029] FIG. 6 is an illustration of some embodiments of the semiconductor arrangement.

[0030] 图7是根据一些实施例的半导体布置的图解。 [0030] FIG. 7 is an illustration of some embodiments of the semiconductor arrangement.

[0031] 图8是根据一些实施例的半导体布置的图解。 [0031] FIG. 8 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0032] 图9是根据一些实施例的半导体布置的图解。 [0032] FIG. 9 is an illustration of some embodiments of the semiconductor arrangement.

[0033] 图10是根据一些实施例的半导体布置的图解。 [0033] FIG. 10 is an illustration of some embodiments of the semiconductor arrangement.

[0034] 图11是根据一些实施例的半导体布置的图解。 [0034] FIG. 11 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0035] 图12是根据一些实施例的半导体布置的图解。 [0035] FIG. 12 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0036] 图13是根据一些实施例的半导体布置的图解。 [0036] FIG. 13 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0037] 图14是根据一些实施例的半导体布置的图解。 [0037] FIG. 14 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0038] 图15是根据一些实施例的半导体布置的图解。 [0038] FIG. 15 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0039] 图16是根据一些实施例的半导体布置的图解。 [0039] FIG. 16 is an illustration of some embodiments of the semiconductor arrangement.

[0040] 图17是根据一些实施例的半导体布置的图解。 [0040] FIG. 17 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0041] 图18是根据一些实施例的半导体布置的图解。 [0041] FIG. 18 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0042] 图19是根据一些实施例的半导体布置的图解。 [0042] FIG. 19 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0043] 图20是根据一些实施例的半导体布置的图解。 [0043] FIG. 20 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0044] 图21是根据一些实施例的半导体布置的图解。 [0044] FIG. 21 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0045] 图22是根据一些实施例的半导体布置的图解。 [0045] FIG. 22 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0046] 图23是根据一些实施例的半导体布置的图解。 [0046] FIG. 23 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0047] 图24是根据一些实施例的半导体布置的图解。 [0047] FIG. 24 is an illustration of some embodiments of the semiconductor arrangement.

[0048] 图25是根据一些实施例的半导体布置的图解。 [0048] FIG. 25 is an illustration of a semiconductor arrangement in accordance with some embodiments.

[0049] 图26是根据一些实施例的半导体布置的图解。 [0049] FIG. 26 is an illustration of some embodiments of the semiconductor arrangement.

具体实施方式 detailed description

[0050] 以下公开提供用于实现所提供的主题的不同部件的多个不同实施例或实例。 [0050] The following disclosure provides many different embodiments or examples, for different components to achieve the subject matter provided. 以下描述组件和布置的特定实例,以简化本公开。 The following describes specific examples of components and arrangements, to simplify the present disclosure. 当然,这些仅是实例并且不用于限制。 Of course, these are merely examples and are not intended to limit. 例如,以下说明书中的第一特征在第二部件之上或上形成可以包括第一和第二部件直接接触的实施例,并且还可以包括可以在第一和第二部件之间形成附加部件,使得第一和第二部件可以不直接接触的实施例。 For example, a first feature of the following description of embodiments may include forming a first member and a second direct contact over the second or upper member, and may also include additional features may be formed between the first and second member, such that the first and second embodiments may not be in direct contact member. 另外,本公开可以在多个实例中可以重复参考数字和/或字母。 Further, the present disclosure may repeat reference numerals and / or letters in the various examples. 该重复用于简单和清楚的目的,并且其本身不指示所论述的多个实施例和/或结构之间的关系。 This was repeated for purposes of simplicity and clarity and does not in itself dictate a relationship between the embodiments and / or configurations discussed in the various embodiments.

[0051] 而且,诸如"在...之下"、"之下"、"下面"、"之上"、"上面"等的空间相对术语可以在此被用于容易说明,以描述如图中所示的一个元件或部件与另一个元件或部件的关系。 [0051] Further, such as "beneath ...", "below", "lower", "above", "upper" and the like Spatially relative terms may be used for ease of illustration herein, to describe FIG. relationship of one element or elements shown in the other member or members. 除了在图中所示的定向之外,空间相对术语旨在包括正在使用或操作的器件的不同定向。 In addition to the orientation depicted in the figures, different orientations of the spatially relative terms are intended to include the use or operation of the device. 装置可以另外被定向(旋转90度或者为其他定向),并且在此使用的空间相对描述符被另外相应地解释。 Further means may be oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are interpreted accordingly additionally.

[0052] 在此提供用于形成半导体布置的一个或多个技术和由此形成的结构。 [0052] The techniques and structures are provided for forming a semiconductor arrangement thus formed one or more.

[0053] 图1示出根据一些实施例的半导体制造的第一方法100,并且在图3至图15中示出在多个制造阶段的由此形成的一个或多个结构。 [0053] FIG. 1 shows a first method of manufacturing a semiconductor according to some embodiments of 100, and shown in FIGS. 3 to 15 in one or more structures formed therefrom in various stages of fabrication. 根据一些实施例,诸如在图15中所示,半导体布置300包括位于第一晶体管区域321a中的多个第一晶体管332a和位于衬底302之上的第二晶体管区域321b中的多个第二晶体管332b,多个第一晶体管具有第一工作电压且邻近具有大于第一工作电压的第二工作电压的多个第二晶体管332b。 According to some embodiments, such as in the arrangement shown in FIG. 15 of the semiconductor 300 includes a plurality of the first plurality of transistor regions 321a of the first transistor and the second transistor region 332a located above the substrate 302 in a second 321b transistor 332b, a first plurality of transistors having a plurality of adjacent first operating voltage and having a second operating voltage is greater than the first operating voltage of the second transistor 332b. 将想到,在此描述的不同区域中形成其多个晶体管和部件、元件等,并且为了简单起见,仅在图中示出其单个实例。 It will occur in different regions described herein which form a plurality of transistors and parts, elements and the like, and for simplicity, only a single example of which is shown in FIG. 线399示出第一晶体管332a通常与第二晶体管332b电隔离或去耦。 Line 399 illustrates generally a first transistor a second transistor 332a or 332b is electrically isolated and decoupled. 在一些实施例中,多个第一晶体管332a包括多个第一栅极结构330a和邻近多个第一栅极结构330a的多个第一侧壁隔离物309a。 In some embodiments, the first plurality of transistors 332a comprises a first plurality of gate structures 330a and 330a adjacent the first gate structure of the plurality of the plurality of first sidewall spacers 309a. 在一些实施例中,多个第一源极漏极区344a在邻近多个第一栅极结构330a的衬底302中。 In some embodiments, the plurality of first source and drain regions adjacent the first plurality of gate structures 330a of the substrate 302 344a. 在一些实施例中,多个低压口袋注入区328a邻近多个第一源极漏极区344a,使得多个低压口袋注入区328a在多个第一栅极结构330a下面比多个第一源极漏极区344a延伸得更远。 In some embodiments, a plurality of low-pressure pockets 328a adjacent to the plurality of first source-drain region implanted region 344a, such that a plurality of low-pressure pocket implantation region 328a in the first plurality of gate structures 330a than the plurality of first source electrode below drain region 344a extends further. 在一些实施例中,多个第二晶体管332b包括多个第二栅极结构330b和邻近多个第二栅极结构330b的多个第二侧壁隔离物309b。 In some embodiments, a plurality of the second transistor 332b includes a plurality of second gate structure 330b and 330b adjacent to the plurality of the second gate structure of the plurality of second sidewall spacers 309b. 在一些实施例中,多个第二源极漏极区344b在邻近多个第二栅极结构330b的衬底302中。 In some embodiments, the plurality of second source drain region 344b adjacent the second plurality of gate structures 330b of the substrate 302. 在一些实施例中,多个高压口袋注入区328b邻近多个第二源极漏极区344b,使得多个高压口袋注入区328b在多个第二栅极结构330b下面比多个第二源极漏极区344b延伸得更远。 In some embodiments, a plurality of high-pressure pockets 328b adjacent to the plurality of second source-drain region implanted region 344b, such that a plurality of high-pressure pocket implantation region 328b in a second plurality of gate structures over a plurality of electrode 330b below the second source drain region 344b extend further. 在一个实施例中,多个第一晶体管332a 包括低压器件或中压器件中的至少一个。 In one embodiment, the plurality of transistors 332a of the first means comprises a low or medium voltage device at least one. 在一些实施例中,多个第二晶体管332b包括中压器件或高压器件中的至少一个。 In some embodiments, a plurality of the second transistor 332b includes a high-voltage or medium voltage device at least one device. 在一些实施例中,多个第一晶体管332a是不同类型,诸如, 不同于多个第二晶体管332b的器件电压类型。 In some embodiments, the first plurality of transistors 332a of different types, such as, a plurality of the second transistor 332b is different from the device voltage type. 在一些实施例中,低压器件具有小于约1.5V 的工作电压。 In some embodiments, the device having a low pressure of less than about 1.5V working voltage. 在一些实施例中,中压器件具有在约3.3V至约IOV之间的工作电压。 In some embodiments, the pressure device has an operating voltage between about 3.3V to about the IOV. 在一些实施例中,高压器件具有在约30V以上的工作电压。 In some embodiments, the device having a high-voltage operating voltage of about 30V or more. 在一些实施例中,根据第一方法100形成的半导体布置300具有比不根据第一方法100形成的布置更薄的栅电极。 In some embodiments, the semiconductor having a first arrangement 300 the method 100 is formed thinner than the arrangement not in accordance with the method of the first gate electrode 100 is formed. 在一个实施例中,多个第一晶体管332a和多个第二晶体管332b被形成为单个CMOS制造处理的一部分而不需要附加掩模。 In one embodiment, the first plurality of transistors 332a and 332b are a plurality of second transistors formed without additional mask is a part of a single CMOS fabrication process.

[0054] 根据一些实施例,在方法100的102中,在衬底302的第一晶体管区域321a之上形成多个第一栅极结构330a,并且在衬底302的第二晶体管区域321b之上形成多个第二栅极结构330b,如图7所示。 [0054] According to some embodiments, at 102 method 100, a first plurality of gate structures 330a formed over the first transistor region 321a of the substrate 302, and a second transistor over the substrate 302 in the region 321b forming a second plurality of gate structures 330b, as shown in FIG. 转到图3,在图7之前,根据一些实施例在衬底302的顶面302a之上形成第一层栅极介电材料304。 Turning to FIG. 3, FIG. 7 prior to, in accordance with some embodiments forming the first layer of gate dielectric material 304 over the top surface 302 of the substrate 302a. 在一些实施例中,衬底302包括硅或锗中的至少一种。 In some embodiments, the substrate 302 comprises at least one of silicon or germanium. 根据一些实施例,衬底302包括外延层、绝缘体上硅(SOI)结构、晶圆、或由晶圆形成的管芯中的至少一个。 According to some embodiments, the substrate includes an epitaxial layer 302, a silicon on insulator (SOI) structure, wafer or die in the wafer formed by at least. 在一些实施例中,第一层栅极介电材料304包括氧化物或氮化物中的至少一种。 In some embodiments, the first layer of gate dielectric material 304 comprises at least one oxide or nitride. 在一些实施例中,第一层栅极介电材料304具有约IOA至约1000 A之间的第一厚度303a。 In some embodiments, the first layer of gate dielectric material 304 having a first thickness 303a between about IOA to about 1000 A. 在一些实施例中,诸如通过蚀刻,从第一晶体管区域321a之上的衬底302的顶面302a去除第一层栅极介电材料304,使得高压栅极电介质304b的第一部分304bl留在衬底302的第二晶体管区域321b之上,如图4所示。 In some embodiments, such as by etching, from above the top surface 321a of the first transistor region 302a of the substrate 302 to remove the first layer of gate dielectric material 304, such that the high voltage gate dielectric 304b remain in the first portion of the liner 304bl transistor region 321b on the second substrate 302, as shown in FIG. 在一些实施例中,在衬底302的顶面302a之上并且在高压栅极电介质304b的第一部分304bl之上形成第二层栅极介电材料305,使得低压栅极电介质304a留在衬底302的第一晶体管区域231a之上,并且高压栅极电介质304b留在衬底302的第二晶体管区域321b之上,如图5所示。 In some embodiments, the second layer of gate dielectric material 305 is formed over the high-voltage gate and dielectric 304b, a first portion 304bl over the top surface 302a of the substrate 302, so that the low-voltage gate dielectric 304a remain in the substrate 302 over the first transistor region 231a, 304b and the high pressure left a gate dielectric over the second transistor region 321b of the substrate 302, as shown in FIG. 在一些实施例中,第二层栅极介电材料305包括氧化物或氮化物中的至少一种。 In some embodiments, the second layer of gate dielectric material 305 comprises at least one oxide or nitride. 在一些实施例中,第二层栅极介电材料305具有约IoA至约500A之间的第二厚度303b,使得低压栅极电介质304a具有第二厚度303b。 In some embodiments, the second layer of gate dielectric material 305 having a thickness of between about a second to about IoA 500A 303b, 304a so that the low-voltage gate dielectric having a second thickness 303b. 在一些实施例中,高压栅极电介质304b包括第一部分304bl和来自第二层栅极介电材料305的第二部分304b2。 In some embodiments, the high voltage gate dielectric 304b comprises a first portion and a second portion 304bl 304b2 from the second layer of gate dielectric material 305. 在一些实施例中,高压栅极电介质304b具有约2ΌΑ至约1200A之间的第三厚度303c,其中,第三厚度303c通常等于第一厚度303a和第二厚度303b的总和。 In some embodiments, the high voltage gate dielectric 304b 303c having a third thickness between about 1200A to about 2ΌΑ, wherein the third thickness is generally equal to the first thickness 303c 303a and 303b of the sum of the second thickness. 在一些实施例中,在低压栅极电介质304a和高压栅极电介质304b之上形成一层栅电极材料310,如图6所示。 In some embodiments, a layer of gate electrode material 310 is formed over the low-voltage gate dielectric and a gate dielectric 304a 304b a high pressure, as shown in FIG. 在一些实施例中,该层栅电极材料310具有基本均匀的厚度。 In some embodiments, the layer of gate electrode material 310 having a substantially uniform thickness. 在一些实施例中,该层栅电极材料310包括多晶硅或金属中的至少一种。 In some embodiments, the gate electrode material layer 310 comprises at least one of polysilicon or metal. 在一些实施例中,该层栅电极材料310、低压栅极电介质304a和高压栅极电介质304b被图案化,以同时形成第一晶体管区域321a中的多个第一栅极结构330a和第二晶体管区域321b中的多个第二栅极结构330b,如图7所示。 In some embodiments, the gate electrode material layer 310, the low-pressure and high-pressure gate dielectric a gate dielectric 304a 304b is patterned to simultaneously form a first plurality of transistors 321a of the first region 330a and a second transistor gate structure a second plurality of gate structures in the region 321b 330b, as shown in FIG. 在一些实施例中,多个第一栅极结构330a的相应栅极结构具有第一宽度340a,并且多个第二栅极结构330b的相应栅极结构具有第二宽度340b。 In some embodiments, a respective plurality of gate structures 330a of the first gate structure having a first width 340a, and a second plurality of gate structures corresponding gate structure 330b having a second width 340b. 在一些实施例中,第二宽度340b大于第一宽度340a。 In some embodiments, the second width greater than the first width 340b 340a. 在一些实施例中,多个低压注入区311a邻近第一晶体管区域321a中的多个第一栅极结构330a。 In some embodiments, a plurality of low-pressure injection region 311a adjacent to the first plurality of transistor regions 321a of the first gate structure 330a. 在一些实施例中,多个高压注入区311b邻近第二晶体管区域321b中的多个第二栅极结构330b。 In some embodiments, the plurality of the plurality of high-pressure injection zone 311b adjacent to the second region 321b of a second transistor gate structure 330b.

[0055] 根据一些实施例,在方法100的104中,在多个第二栅极结构330b和第二晶体管区域321b之上形成低压光刻胶308a,由此暴露多个第一栅极结构330a和多个低压注入区311a,如图9所示。 [0055] According to some embodiments, at 104 method 100, a photoresist 308a is formed over the plurality of low-pressure second gate structure 330b and a second transistor region 321b, thereby exposing the first plurality of gate structures 330a and a plurality of low-pressure injection region 311a, as shown in FIG. 转到图8,根据一些实施例,在图9之前,诸如通过在多个第一栅极结构330a、多个第二栅极结构330b以及衬底302之上进行沉积而形成第一低压光刻胶308。 Turning to Figure 8, in accordance with some embodiments, prior to FIG. 9, such as by deposition over a first plurality of gate structures 330a, 330b, and a plurality of second gate structure formed in the substrate 302 and the first low-lithography glue 308. 在一些实施例中,第一低压光刻胶308被图案化,以形成低压光刻胶308a,如图9所示。 In some embodiments, the first low-pressure photoresist 308 is patterned to form a low pressure resist 308a, as shown in FIG.

[0056] 根据一些实施例,在方法100的106中,执行低压LDD注入,以将第一低压掺杂物318a注入到多个低压注入区311a中,以形成多个低压浅阱314a,如图10所示。 [0056] According to some embodiments, the method 100 at 106, the low pressure LDD implantation performed to the first low-pressure 318a dopant implanted into the plurality of low-pressure injection region 311a, a low pressure to form a plurality of shallow wells 314a, FIG. 10 FIG. 在一些实施例中,第一低压掺杂物318a包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the first low dopant 318a comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第一低压掺杂物318a。 In some embodiments, the selected nominal voltage, in a dose and energy used in device fabrication implantation first low dopant 318a. 在一些实施例中,对半导体布置300执行第一退火,使得多个低压浅阱314a在多个第一栅极结构330a下面迀移。 In some embodiments, the semiconductor arrangement 300 first annealing, so that a plurality of shallow wells 314a Gan low voltage shift below the plurality of first gate structures 330a. 在一些实施例中,低压光刻胶308a防止第一低压掺杂物318a进入低压光刻胶308a下面的区域中。 In some embodiments, the photoresist 308a prevents the low pressure region of the first low-pressure into the low dopant 318a 308a below the photoresist. 在一些实施例中,通过所选额定电压,以在器件制造中使用的第一角度注入第一低压掺杂物318a。 In some embodiments, the selected nominal voltage at a first angle used in device fabrication implantation first low dopant 318a.

[0057] 根据一些实施例,在方法100的108中,执行低压口袋注入,以将第二低压掺杂物318b注入到多个低压注入区311a中,以形成多个低压口袋注入区328a,如图11所示。 [0057] According to some embodiments, at 108 method 100, a low-pressure pocket implantation performed to the second low dopant implanted into the plurality of low voltage 318b implant regions 311a, to form a plurality of low-pressure pocket implantation region 328a, such as 11 shown in FIG. 在一些实施例中,第二低压掺杂物318b包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the second low dopant 318b includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第二低压掺杂物318b。 In some embodiments, the selected nominal voltage, in a dose and energy used in the second low-pressure injection device fabrication dopant 318b. 在一些实施例中,低压光刻胶308a防止第二低压掺杂物318b进入低压光刻胶308a下面的区域中。 In some embodiments, the photoresist 308a to prevent the low-pressure region of the second low-pressure into the low dopant photoresist 308a 318b below. 在一些实施例中,通过所选额定电压,以在器件制造中使用的第二角度注入第二低压掺杂物。 In some embodiments, the selected nominal voltage at a second angle used in the second low-pressure injection device fabrication dopant. 在一些实施例中,多个低压口袋注入区328a至少部分地在多个第一栅极结构330a下面。 In some embodiments, a plurality of low-pressure pocket implantation region 328a at least partially below the first plurality of gate structures 330a. 在一些实施例中,对半导体布置300执行第二退火,使得多个低压浅阱314a和多个低压口袋注入区328a在多个第一栅极结构330a下面迀移。 In some embodiments, the semiconductor 300 disposed second annealing, so that a plurality of shallow wells 314a and a plurality of low-pressure low-pressure pocket implantation region 328a Gan shift plurality of first gate structures 330a below. 在一些实施例中,诸如通过酸洗或蚀刻中的至少一个,从多个第二栅极结构330b和第二晶体管区域321b去除低压光刻胶308a,如图12所示。 In some embodiments, such as by etching or pickling in at least one of the plurality of the second gate structure is removed from the second transistor 330b and the low pressure region 321b of the photoresist 308a, as shown in Fig.

[0058] 根据一些实施例,在方法100的110中,在多个第一栅极结构330a之上、在衬底的第一晶体管区域321a之上形成高压光刻胶331a,并且在多个第二栅极结构330b之上形成多个高压残留光刻胶331b,从而暴露衬底302的多个高压注入区311b和多个第二栅极结构330b 的多个第二顶部326,如图13所示。 [0058] According to some embodiments, the method 100 at 110, over a plurality of first gate structure 330a, 331a are formed over the first resist high voltage transistor region of the substrate 321a, and a plurality of two gate structure 330b is formed over a plurality of high-pressure residual photoresist 331b, thereby exposing a plurality of high-pressure injection region 311b of the substrate 302 and a second plurality of gate structures 330b plurality of second top 326, FIG. 13 shows. 在一些实施例中,通过诸如通过在多个第一栅极结构330a、多个第二栅极结构330b以及衬底302之上沉积形成第一高压光刻胶(未示出)并且诸如通过酸洗或蚀刻中的至少一个图案化第一高压光刻胶,形成高压光刻胶331a和多个高压残留光刻胶331b。 In some embodiments, such as by formed by depositing a first resist high pressure over the plurality of first gate structures 330a, 330b, and a plurality of second gate structure of the substrate 302 (not shown), such as by acid and washing or etching at least one first high pressure patterned photoresist, the photoresist 331a and a plurality of high-pressure high-pressure residual photoresist 331b. 在一些实施例中,多个高压残留光刻胶331b在多个第二栅极顶部326之间,其中,多个高压残留光刻胶331b与第一栅极边缘329a相距第一距离324a,并且与第二栅极边缘329b相距第二距离324b。 In some embodiments, the plurality of high voltage remaining photoresist 331b between the top of the plurality of the second gate electrode 326, wherein the plurality of first high-pressure residual photoresist 331b and 329a a first distance from the gate edge 324a, and a second gate electrode 329b and a second distance from the edge 324b. 在一些实施例中,第一距离324a和第二距离324b是不同距离。 In some embodiments, the first distance 324a and 324b are different from the second distance. 在一些实施例中,第一距离324a等于第二距离324b。 In some embodiments, the first distance 324a equal to the second distance 324b. 在一些实施例中,第一距离324a在约30nm至约90nm之间,或者第二距离324b在约30nm至约90nm之间。 In some embodiments, the first distance 324a is between about 30nm to about of 90 nm, or the second distance 324b between about 30nm to about 90nm.

[0059] 根据一些实施例,在方法100的112中,执行高压LDD注入,以将第一高压掺杂物318c注入到多个高压注入区311b中,以形成多个高压浅阱314b,如图13中所示。 [0059] According to some embodiments, the method 112 100, the high-voltage LDD implantation performed to inject dopant 318c into a first plurality of high-pressure high-pressure injection region 311b to form a plurality of shallow high pressure wells 314b, FIG. 13 shown in FIG. 在一些实施例中,第一高压掺杂物318c包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the first high pressure dopant 318c include boron, phosphorous, at least one of arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第一高压掺杂物318c。 In some embodiments, the selected nominal voltage, in a dose and energy used in the first high-pressure injection device fabrication dopant 318c. 在一些实施例中,对半导体布置300执行第三退火,使得多个高压浅阱314b在多个第二栅极结构330b下面迀移。 In some embodiments, the arrangement 300 for performing a third annealing the semiconductor, so that a plurality of shallow high pressure wells 314b Gan plurality of shift below the second gate structure 330b. 在一些实施例中,高压光刻胶331a防止第一高压掺杂物318c进入高压光刻胶331a下面的区域中。 In some embodiments, the photoresist 331a prevents the high pressure region of the first high pressure enters the high pressure dopant 318c below the photoresist 331a. 在一些实施例中,多个高压残留光刻胶331b类似地保护多个第二栅极结构不受第一高压掺杂物318c影响。 In some embodiments, a plurality of high-pressure residual photoresist 331b similarly protected by a second plurality of gate structures 318c from a first high pressure dopant affecting matter. 在一些实施例中,通过所选额定电压,以在器件制造中使用的第三角度注入第一高压掺杂物318c。 In some embodiments, the selected nominal voltage, a third angle used in the first high-pressure injection device fabrication dopant 318c.

[0060] 根据一些实施例,在方法100的114中,执行高压口袋注入,以将第二高压掺杂物318d注入到多个高压注入区311b中,以形成多个高压口袋注入区318b,如图14所示。 [0060] According to some embodiments, the method 100 at 114, the high-pressure pocket implantation performed to inject a second plurality of high pressure to a high pressure dopant implanted regions 318d 311b to form a plurality of high-pressure pocket implantation region 318b, such as 14 shown in FIG. 在一些实施例中,第二高压掺杂物318d包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the second high pressure dopant 318d comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第二高压掺杂物318d。 In some embodiments, the selected nominal voltage, in a dose and energy used in the second high-pressure injection device fabrication dopant 318d. 在一些实施例中,高压光刻胶331a防止第二高压掺杂物318d进入高压光刻胶331a下面的区域中。 In some embodiments, the photoresist 331a to prevent the high-pressure high-pressure region of the second dopant 318d enters the high pressure below the photoresist 331a. 在一些实施例中,多个高压残留光刻胶331b类似地保护多个第二栅极结构330b不受第二高压掺杂物318d影响。 In some embodiments, a plurality of high-pressure residual photoresist 331b similarly protected by a second plurality of gate structures 330b 318d from the second high pressure dopant affecting matter. 在一些实施例中,通过所选额定电压,以在器件制造中使用的第四角度注入第二高压掺杂物318d。 In some embodiments, the selected nominal voltage, at a fourth angle in the device used for producing high pressure in a second dopant implantation 318d. 在一些实施例中,多个高压口袋注入区328b至少部分地在多个第二栅极结构330b下面。 In some embodiments, a plurality of high-pressure pocket implantation region 328b in a plurality of at least partially under the second gate structure 330b. 在一些实施例中,对半导体布置300执行第四退火,使得多个高压浅阱314b和多个高压口袋注入区328b在多个第二栅极结构330b下面迀移。 In some embodiments, the arrangement 300 for performing a fourth semiconductor annealing, so that a plurality of shallow high pressure wells 314b and a plurality of high-pressure pocket implantation region 328b Gan plurality of shift below the second gate structure 330b. 在一些实施例中,诸如通过酸洗或蚀刻中的至少一种,从多个第二栅极结构330b、多个第一栅极结构330a和第一晶体管区域321a去除高压光刻胶331a和多个高压残留光刻胶331b,如图15所示。 In some embodiments, such as by etching or pickling in at least one, from a second plurality of gate structures 330b, a first plurality of gate structures 330a and a first high-voltage transistor region 321a is removed and the photoresist 331a plurality high-pressure residual photoresist 331b, as shown in Figure 15.

[0061] 在一些实施例中,在多个第一栅极结构330a、多个第二栅极结构330b和衬底302之上形成一层侧壁材料(未示出)。 [0061] In some embodiments, the sidewall material to form a layer (not shown) over the plurality of 330a, 330b, and a plurality of second gate structure 302 of the substrate a first gate structure. 在一些实施例中,该层侧壁材料包括氮化物。 In some embodiments, the sidewall material comprises a nitride layer. 在一些实施例中,该层侧壁材料被图案化,以同时形成邻近多个第一栅极结构330a的多个第一侧壁隔离物309a以及邻近多个第二栅极结构330b的多个第二侧壁隔离物309b。 In some embodiments, the sidewall material layer is patterned to simultaneously form a plurality of first sidewall spacers 309a and a second plurality of gate structures adjacent the first plurality of gate structures adjacent to the plurality of 330a and 330b second sidewall spacers 309b.

[0062] 在一些实施例中,根据一些实施例,与相应图案化的光刻胶(未不出)关联地执行低压深阱注入,以将第三低压掺杂物(未示出)注入到多个低压浅阱314a中,以形成第一源极漏极区344a,如图15所示。 [0062] In some embodiments, according to some embodiments, the respective patterned photoresist (not not) performed in association with the low-pressure deep well injection, to the third low dopant (not shown) into shallow wells 314a plurality of low pressure to form a first source-drain region 344a, shown in Figure 15. 在一些实施例中,第三低压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the third low dopant comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第三低压掺杂物。 In some embodiments, the selected nominal voltage, in a dose and energy used in device fabrication implantation third low dopant. 在一些实施例中,根据一些实施例,与相应图案化的光刻胶(未示出)关联地执行高压深阱注入,以将第三高压掺杂物(未示出)注入到多个高压浅阱314b中,以形成第二源极漏极区344b,如图15所示。 In some embodiments, according to some embodiments, the respective patterned photoresist (not shown) associated with the high pressure deep well implant is performed, a high pressure to a third dopant (not shown) is injected into the plurality of high pressure shallow wells 314b to form second source and drain regions 344b, shown in Figure 15. 在一些实施例中,第三高压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the third high pressure dopant comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第三高压掺杂物。 In some embodiments, the selected nominal voltage, in a dose and energy used in device fabrication implantation dopants third high voltage.

[0063] 假定在一些实施例中,第一距离324a不等于第二距离324b,诸如由于相对于多个第二栅极结构330b对准或形成多个高压残留光刻胶331b的不准确,多个高压浅阱314b、多个高压口袋注入区328b或多个第二源极漏极区344b中的至少一个关于相应的第二栅极结构330b不对称。 [0063] In some embodiments, assuming a first distance 324a is not equal to the second distance 324b, such as due to a second plurality of gate structures with respect to the alignment or 330b forming a plurality of high-pressure residual photoresist 331b is inaccurate, multiple a shallow high pressure wells 314b, 328b or a plurality of source and drain regions 344b of the second plurality of high-pressure pocket implantation region on at least a respective second gate structure 330b asymmetry. 根据一些实施例,第二栅极结构的一侧上的第二源极漏极区的尺寸不同于第二栅极结构的另一个侧上的第二源极漏极区的尺寸。 According to some embodiments, the size of the second source drain region on the side of the second gate structure is different from the size of the second source drain region on the other side of the second gate structure. 根据一些实施例,与当第二晶体管被反相偏置时相比,当第二晶体管被正向偏置时,在第二栅极结构周围注入的掺杂物的这种不对称产生不同特征曲线。 According to some embodiments, when compared to the second biased transistor is inverted, when the second transistor is forward biased, in which the second gate structure surrounding the implanted dopant asymmetric produce different characteristics curve.

[0064] 图2示出根据一些实施例的半导体制造的第二方法200,并且图16至26中示出在多个制造阶段处由此形成的一个或多个结构。 [0064] FIG. 2 shows a second method of manufacturing a semiconductor according to some embodiments of 200, and FIGS. 16 to 26 illustrate one or more structures thus formed at a plurality of manufacturing stages. 根据一些实施例,诸如图26中所示,半导体布置400包括位于第一晶体管区域421a中的多个第一晶体管432a和位于衬底402之上的第二晶体管区域421b中的多个第二晶体管432b,所述多个第一晶体管具有第一工作电压且邻近具有大于第一工作电压的第二工作电压的多个第二晶体管432b。 According to some embodiments, such as shown in FIG., A first semiconductor arrangement 400 includes a plurality of transistor regions 421a in a first plurality of transistors 432a and a second transistor region 421b of the substrate 402 located above the transistor 26 in the second 432b, a plurality of the first plurality of transistors having a first operating voltage and second operating voltage having adjacent to the first operating voltage is greater than the second transistor 432b. 将想到,在此描述的不同区域中形成其多个晶体管和特征、元件等,并且为了简单起见,仅示出其单个实例。 It will occur in different regions described herein which form a plurality of transistors and features, elements and the like, and for simplicity, only a single instance thereof. 线499示出第一晶体管432a通常与第二晶体管432b电隔离或去耦。 Line 499 illustrates generally a first transistor 432a is electrically isolated from the second transistor 432b or decoupling. 在一些实施例中,多个第一晶体管432a包括多个第一栅极结构430a和邻近多个第一栅极结构430a的多个第一侧壁隔离物409a。 In some embodiments, the first plurality of transistors 430a and 432a comprises a plurality of first gate structures adjacent to the plurality of first gate structures 430a of the first plurality of sidewall spacers 409a. 在一些实施例中,多个第一源极漏极区444a在邻近多个第一栅极结构430a的衬底402 中。 In some embodiments, the plurality of first source-drain region 444a on the substrate 402 adjacent to the first plurality of gate structures 430a. 在一些实施例中,多个低压口袋注入区428a邻近多个第一源极漏极区444a,使得多个低压口袋注入区428a在多个第一栅极结构430a下面比多个第一源极漏极区444a延伸得更远。 In some embodiments, a plurality of low-pressure pockets 428a adjacent to the plurality of first source-drain region implanted region 444a, a low-pressure pocket implantation region so that a plurality of electrode 428a in the first plurality of gate structures 430a following a first plurality of source than drain region 444a extends further. 在一些实施例中,多个第二晶体管432b包括多个第二栅极结构430b和邻近多个第二栅极结构430b的多个第二侧壁隔离物409b。 In some embodiments, the second plurality comprises a plurality of transistors 432b and 430b adjacent to a second plurality of gate structures a second plurality of gate structures 430b of the second sidewall spacer 409b. 在一些实施例中,多个第二源极漏极区444b在邻近多个第二栅极结构430b的衬底402中。 In some embodiments, the plurality of second source drain region 444b in the substrate 402 adjacent to the plurality of the second gate structure 430b. 在一些实施例中,多个高压口袋注入区428b邻近多个第二源极漏极区444b,使得多个高压口袋注入区428b在多个第二栅极结构430b下面比多个第二源极漏极区444b延伸得更远。 In some embodiments, a plurality of high-pressure pockets 428b adjacent to the plurality of second source-drain region implanted region 444b, such that a plurality of high-pressure pocket implantation region 428b in a second plurality of gate structures 430b below the second source electrode over a plurality of drain region 444b extend further. 在一些实施例中,多个第一晶体管432a包括低压器件或中压器件中的至少一个。 In some embodiments, the plurality of transistors 432a of the first means comprises a low or medium voltage device at least one. 在一些实施例中,多个第二晶体管432b包括中压器件或高压器件中的至少一个。 In some embodiments, a plurality of the second transistor 432b includes a high-voltage or medium voltage device at least one device. 在一些实施例中,多个第一晶体管432a是不同类型的,诸如,不同于多个第二晶体管432b的器件电压类型。 In some embodiments, the first plurality of transistors 432a of a different type, such as a voltage different from the device types of the plurality of the second transistor 432b. 在一些实施例中,低压器件具有小于约1.5V的工作电压。 In some embodiments, the device having a low pressure of less than about 1.5V working voltage. 在一些实施例中,中压器件具有在约3.3V至约IOV之间的工作电压。 In some embodiments, the pressure device has an operating voltage between about 3.3V to about the IOV. 在一些实施例中,高压器件具有约30V以上的工作电压。 In some embodiments, the device has a high pressure above about 30V working voltage. 在一些实施例中,根据第二方法200形成的半导体布置400具有比不根据第二方法200形成的布置更薄的栅电极。 In some embodiments, the semiconductor arrangement 400 having a second method 200 is formed thinner than the arrangement not in accordance with the second method of the gate electrode 200 is formed. 在一些实施例中,多个第一晶体管432a和多个第二晶体管432b被形成为单个CMOS制造处理的一部分,而不需要附加掩模。 In some embodiments, the first plurality of transistors 432a and a second plurality of transistors 432b are formed as part of a single CMOS fabrication process without the need for additional mask.

[0065] 根据一些实施例,在方法200的202中,在衬底402的第一晶体管区域421a和衬底402的第二晶体管区域421b之上形成第一高压光刻胶431,如图16中所示。 [0065] According to some embodiments, at 202 method 200, a first photoresist 431 is formed over the high voltage transistor region of the first substrate 402 of the second transistor region 421a and 421b of the substrate 402, 16 in FIG. Fig. 在一些实施例中, 衬底402包括硅或锗中的至少一种。 In some embodiments, the substrate 402 comprises at least one of silicon or germanium. 根据一些实施例,衬底402包括外延层、绝缘体上硅(SOI)结构、晶圆、或由晶圆形成的管芯中的至少一种。 According to some embodiments, the substrate 402 comprises an epitaxial layer, at least one silicon-on-insulator (SOI) structure, wafer or die in the wafer formed by.

[0066] 根据一些实施例,在方法200的204中,图案化第一高压光刻胶431,以在第一晶体管区域421a之上形成高压光刻胶431a并且在第二晶体管区域421b之上形成多个高压残留光刻胶431b,从而暴露邻近多个高压残留光刻胶431b的衬底402的多个高压注入区411b,如图17中所示。 [0066] According to some embodiments, at 204 method 200, a first high pressure patterned photoresist 431 to form a transistor on the first region 421a and a high pressure photoresist 431a is formed on the second transistor region 421b a plurality of high-pressure residual photoresist 431b, thereby exposing a plurality of high pressure adjacent the remaining photoresist 402 is a plurality of high-pressure injection region 431b of the substrate 411b, as shown in FIG. 17. 在一些实施例中,多个高压残留光刻胶431b具有约350nm至约450nm之间的第一残留光刻胶宽度413。 In some embodiments, the plurality of high voltage having a first residual photoresist remaining photoresist 431b between about 350nm to about 450nm width 413.

[0067] 根据一些实施例,在方法200的206中,执行高压LDD注入,以将第一高压掺杂物418a注入到多个高压注入区411b中,以形成多个高压浅阱414b,如图17所示。 [0067] According to some embodiments, the method 200 at 206, the high-voltage LDD implantation performed to the first high voltage 418a dopant implanted into the plurality of high pressure injection region 411b, a high pressure to form a plurality of shallow wells 414b, FIG. 17 FIG. 在一些实施例中,第一高压掺杂物418a包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the first high voltage 418a dopant comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第一高压掺杂物418a。 In some embodiments, the selected nominal voltage, in a dose and energy used in the first high-pressure injection device fabrication dopant 418a. 在一些实施例中,对半导体布置400执行第一退火,使得多个高压浅阱414b在多个高压残留光刻胶431b下面迀移。 In some embodiments, a first annealing semiconductor arrangement 400, such that a plurality of shallow high pressure wells 414b in a plurality of high-pressure residual photoresist 431b below Gan shift. 在一些实施例中,高压光刻胶431a防止第一高压掺杂物418a进入高压光刻胶431a下面的衬底402的区域中。 In some embodiments, the photoresist 431a prevents the high pressure region of the first high pressure enters the high pressure dopant photoresist 418a 431a of the substrate 402 below. 在一些实施例中,多个高压残留光刻胶431b类似地防止衬底402免受第一高压掺杂物418a影响。 In some embodiments, a plurality of high-pressure residual photoresist 431b similarly prevent the substrate 402 from the first high-pressure impact dopant 418a. 在一些实施例中,以入射到衬底402的表面402a 的第一角度,注入第一高压掺杂物418a,其中,第一角度基本垂直于衬底402的表面402a。 In some embodiments, the first angle to be incident surface 402a of the substrate 402, a first high pressure dopant implantation 418a, wherein the first angle substantially perpendicular to the surface 402 of the substrate 402a. 在一些实施例中,第一角度包括通过所选额定电压在器件制造中使用的角度。 In some embodiments, the first angle comprises an angle from the selected nominal voltage used in device fabrication.

[0068] 根据一些实施例,在方法200的208中,执行高压口袋注入,以将第二高压掺杂物418b注入到多个高压注入区411b中,以形成多个高压口袋注入区428b,如图18所示。 [0068] According to some embodiments, at 208 method 200, a high-pressure pocket implantation performed to the second high voltage 418b dopant implanted into the plurality of high-pressure injection region 411b, to form a plurality of high-pressure pocket implantation region 428b, such as 18 shown in FIG. 在一些实施例中,第二高压掺杂物418b包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the second high pressure dopant 418b includes at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第二高压掺杂物418b。 In some embodiments, the selected nominal voltage, in a dose and energy used in the second high-pressure injection device fabrication dopant 418b. 在一些实施例中,高压光刻胶431a防止第二高压掺杂物418b进入高压光刻胶431a下面的衬底402的区域中。 In some embodiments, the photoresist 431a to prevent the high-pressure high-pressure region of the second dopant photoresist 431a 418b enters the high pressure below the substrate 402. 在一些实施例中,多个高压残留光刻胶431b类似地防止衬底402免受第二高压掺杂物418b影响。 In some embodiments, a plurality of high-pressure residual photoresist 431b similarly prevent the substrate 402 from the second high-pressure impact dopant 418b. 在一些实施例中,以入射到衬底402的表面402a的第二角度注入第二高压掺杂物418b,其中,第二角度基本垂直于衬底402的表面402a。 In some embodiments, the surface of the substrate 402 to be incident angle 402a of the second high-pressure injection of a second dopant 418b, wherein the second angle is substantially perpendicular to the surface 402 of the substrate 402a. 在一些实施例中, 第二角度包括通过所选额定电压在器件制造中使用的角度。 In some embodiments, the second angle comprises an angle from the selected nominal voltage used in device fabrication. 在一些实施例中,多个高压口袋注入区428b至少部分地在多个高压残留光刻胶431b下面。 In some embodiments, a plurality of high-pressure pocket implantation region 428b in a plurality of at least partially below the high pressure residual photoresist 431b. 在一些实施例中,对半导体布置400执行第二退火,使得多个高压浅阱414b和多个高压口袋注入区428b在多个高压残留光刻胶431b下面迀移。 In some embodiments, the semiconductor 400 disposed second annealing, so that a plurality of shallow high pressure wells 414b and a plurality of high-pressure pocket implantation region 428b in a plurality of high-pressure residual photoresist 431b below Gan shift. 在一些实施例中,诸如通过酸洗或蚀刻中的至少一种,去除高压光刻胶431a和多个高压残留光刻胶431b,如图19所示。 In some embodiments, such as by etching or pickling at least one high pressure removing photoresist residues of the photoresist 431a and 431b a plurality of high voltage, as shown in Fig.

[0069] 根据一些实施例,在方法200的210中,在衬底402的第一晶体管区域421a之上形成多个第一栅极结构430a,并且在衬底402的第二晶体管区域421b之上形成多个第二栅极结构430b,使得多个第二栅极结构430b邻近多个低压浅阱414b,如图23所示。 [0069] According to some embodiments, at 210 method 200, a first plurality of gate structures 430a formed over the first transistor region 421a of the substrate 402, and the region on the second substrate 402 of the transistor 421b forming a second plurality of gate structures 430b, 430b such that a plurality of the second gate structure adjacent the plurality of low voltage shallow wells 414b, as shown in Fig. 转到图19,根据一些实施例,在图23之前,以与以上关于第一层栅极介电材料304描述的相同方式(例如如图3所示),在衬底402之上形成第一层栅极介电材料404。 Turning to Figure 19, in accordance with some embodiments, prior to FIG. 23, in the same manner as above described with respect to a gate 304 of the first layer of dielectric material (e.g., FIG. 3), is formed over a first substrate 402 layer of gate dielectric material 404. 在一些实施例中,以与以上诸如图4所示的关于第一层栅极介电材料304描述的相同方式,从衬底402的第一晶体管区域431a 去除第一层栅极介电材料404,如图20所示。 In some embodiments, in the same manner on the first layer of gate dielectric material 304 described above, such as shown in FIG. 4, removing the first layer of gate dielectric material 404 from the substrate 402 of the first transistor region 431a , as shown in Figure 20. 在一些实施例中,以与以上诸如图5所示的关于低压栅极电介质304a和高压栅极电介质304b的形成描述的相同方式,在第一层栅极介电材料404之上形成第二层栅极介电材料405,以形成低压栅极电介质404a和高压栅极电介质404b,如图21所示。 In some embodiments, in the same manner as above with respect to FIG low-voltage and high-voltage gate dielectric 304a formed gate dielectric is described 304b shown in FIG. 5, a second layer over the first layer of gate dielectric material 404 The gate dielectric material 405, to form low-voltage and high-voltage gate dielectric a gate dielectric 404a 404b, shown in Figure 21. 在一些实施例中,以与以上诸如图6所示的关于该层栅电极材料310描述的相同方式,在低压栅极电介质404a和高压栅极电介质404b之上形成一层栅电极材料410, 如图22所示。 In some embodiments, in the same manner with respect to the gate electrode material layer 310 as described above as shown in FIG. 6, the low-pressure gate dielectric 404a and 404b over the gate dielectric layer of gate electrode material is formed a high pressure 410, such as 22 shown in FIG. 在一些实施例中,图案化该层栅电极材料410、低压栅极电介质404a和高压栅极电介质404b,以同时形成第一晶体管区域421a中的多个第一栅极结构430a和第二晶体管区域421b中的多个第二栅极结构430b,如图23所示。 In some embodiments, patterning the gate electrode material layer 410, the gate low voltage and the high dielectric gate dielectric 404a 404b, to form a first plurality of gate structures 421a 430a of the first transistor and a second transistor region while the region a second plurality of gate structures 421b 430b, as shown in Fig. 在一些实施例中,多个第一栅极结构430a的相应栅极结构具有第一宽度440a,并且多个第二栅极结构430b的相应栅极结构具有第二宽度440b。 In some embodiments, a respective plurality of gate structures 430a of the first gate structure having a first width 440a, and a second plurality of gate structures corresponding gate structure 430b having a second width 440b. 在一些实施例中,第二宽度440b大于第一宽度440a。 In some embodiments, the second width greater than the first width 440b 440a. 在一些实施例中,第二宽度440b大于第一残留光刻胶宽度413,使得多个高压浅阱414b中的至少一些或多个高压口袋注入区428b中的至少一些中的至少一个在多个第二栅极结构430b下面。 In some embodiments, the second width greater than the first remaining photoresist 440b width 413, such that at least some of the plurality of high-pressure or high-pressure pocket implantation region a plurality of shallow wells 414b, 428b in at least some of the at least one of the plurality of a second gate structure 430b below.

[0070] 根据一些实施例,在方法200的212中,在多个第二栅极结构430b和第二晶体管区域421b之上形成低压光刻胶408a,从而暴露多个第一栅极结构430a和邻近多个第一栅极结构430a的多个低压注入区411a,如图24所示。 [0070] According to some embodiments, the method 200 at 212, the depression 408a is formed in the photoresist over the second plurality of gate structures 430b and 421b of the second transistor region, so as to expose a first plurality of gate structures 430a and a first plurality of gate structures adjacent the plurality of low-pressure injection regions 430a 411a, shown in Figure 24. 在一些实施例中,根据一些实施例,在多个第一栅极结构430a、多个第二栅极结构430b以及衬底402之上形成第一低压光刻胶(未不出)。 In some embodiments, in accordance with some embodiments, a first low-pressure photoresist (not not) over a first plurality of gate structures 430a, 430b, and a plurality of the second gate structure 402 of the substrate. 在一些实施例中,图案化第一低压光刻胶,以形成低压光刻胶408a。 In some embodiments, the patterned first photoresist low pressure, the low pressure to form a photoresist 408a.

[0071] 根据一些实施例,在方法200的214中,执行低压LDD注入,以将第一低压掺杂物418c注入到多个低压注入区411a中,以形成多个低压浅阱414a,如图24所示。 [0071] According to some embodiments, at 214 of method 200, the low pressure LDD implantation performed to the first low-pressure 418c dopant implanted into regions 411 a plurality of low-pressure injection, to form a plurality of low-pressure shallow wells 414a, FIG. 24 FIG. 在一些实施例中,第一低压掺杂物418c包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the first low dopant 418c comprising at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第一低压掺杂物418c。 In some embodiments, the selected nominal voltage, in a dose and energy used in device fabrication implantation first low dopant 418c. 在一些实施例中,对半导体布置400执行第三退火,使得多个低压浅阱414a在多个第一栅极结构430a下面迀移。 In some embodiments, the arrangement 400 for performing a third annealing of the semiconductor, so that a plurality of shallow wells 414a Gan low voltage shift below the plurality of first gate structures 430a. 在一些实施例中,低压光刻胶408a防止第一低压掺杂物418c进入低压光刻胶408a下面的区域。 In some embodiments, the low pressure prevents the photoresist 408a 408a into the low pressure region below the first low doped 418c photoresist composition. 在一些实施例中,通过所选额定电压,以在器件制造中使用的第三角度,注入第一低压掺杂物418c。 In some embodiments, the selected nominal voltage, a third angle used in device fabrication, low pressure injection first dopant 418c.

[0072] 根据一些实施例,在方法200的216中,执行低压口袋注入,以将第二低压掺杂物418d注入到多个低压注入区411a中,以形成多个低压口袋注入区428a,如图25所示。 [0072] According to some embodiments, at 216 of method 200, the low-pressure pocket implantation performed to the second low 418d dopant implanted into regions 411 a plurality of low-pressure injection, to form a plurality of low-pressure pocket implantation region 428a, such as 25 shown in FIG. 在一些实施例中,第二低压掺杂物418d包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the second low dopant 418d comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第二低压掺杂物418d。 In some embodiments, the selected nominal voltage, in a dose and energy used in the second low-pressure injection device fabrication dopant 418d. 在一些实施例中,低压光刻胶408a防止第二低压掺杂物418d进入低压光刻胶408a下面的区域中。 In some embodiments, the photoresist 408a prevents the low pressure region of the second low-pressure into the low dopant photoresist 408a 418d below. 在一些实施例中,通过所选额定电压,以在器件制造中使用的第四角度注入第二低压掺杂物418d。 In some embodiments, the selected nominal voltage, at a fourth angle used in device fabrication implantation second low dopant 418d. 在一些实施例中,多个低压口袋注入区428a至少部分地在多个第一栅极结构430a下面。 In some embodiments, a plurality of low-pressure pocket implantation region 428a at least partially in the first plurality of gate structures 430a below. 在一些实施例中,对半导体布置400执行第四退火,使得多个低压浅阱414a和多个低压口袋注入区428a在多个第一栅极结构430a下面迀移。 In some embodiments, the arrangement 400 for performing a fourth semiconductor annealing, so that a plurality of shallow wells 414a and a plurality of low-pressure low-pressure pocket implantation region 428a Gan shift plurality of first gate structures 430a below. 在一些实施例中,诸如通过酸洗或蚀刻中的至少一种,从多个第二栅极结构430a和衬底402去除低压光刻胶408a,如图26所示。 In some embodiments, such as by etching or pickling at least one of a second plurality of gate structures 430a from the substrate 402 and the low pressure is removed the photoresist 408a, as shown in Fig.

[0073] 在一些实施例中,在多个第一栅极结构430a、多个第二栅极结构430b和衬底402之上形成一层侧壁材料(未示出)。 [0073] In some embodiments, the sidewall material to form a layer (not shown) over the plurality of first gate structures 430a, a second plurality of gate structures 402 and the substrate 430b. 在一些实施例中,该层侧壁材料包括氮化物。 In some embodiments, the sidewall material comprises a nitride layer. 在一些实施例中,图案化该层侧壁材料,以同时形成邻近多个第一栅极结构430a的多个第一侧壁隔离物409a和邻近多个第二栅极结构430b的多个第二侧壁隔离物409b。 In some embodiments, the patterned layer of the sidewall material to form a plurality of adjacent the first plurality of the plurality of sidewall spacers 430a and 409a adjacent to a second plurality of gate structures of the first gate structure 430b simultaneously two sidewall spacer 409b.

[0074] 在一些实施例中,根据一些实施例,与相应图案化的光刻胶(未不出)关联地执行低压深阱注入,以将第三低压掺杂物(未示出)注入到多个低压浅阱414a中,以形成第一源极漏极区444a,如图26所示。 [0074] In some embodiments, according to some embodiments, the respective patterned photoresist (not not) performed in association with the low-pressure deep well injection, to the third low dopant (not shown) into a plurality of low pressure shallow wells 414a, to form a first source-drain region 444a, as shown in Fig. 在一些实施例中,第三低压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the third low dopant comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量注入第三低压掺杂物。 In some embodiments, the selected nominal voltage, in a dose and energy used in device fabrication implantation third low dopant. 在一些实施例中,根据一些实施例,与相应图案化的光刻胶(未示出)关联地执行高压深阱注入,以将第三高压掺杂物(未示出)注入到多个高压浅阱414b中,以形成第二源极漏极区444b,如图26所示。 In some embodiments, according to some embodiments, the respective patterned photoresist (not shown) associated with the high pressure deep well implant is performed, a high pressure to a third dopant (not shown) is injected into the plurality of high pressure shallow wells 414b to form second source and drain regions 444b, shown in Figure 26. 在一些实施例中,第三高压掺杂物包括硼、磷、砷、锑、硼、氟化硼、氮或碳中的至少一种。 In some embodiments, the third high pressure dopant comprises at least one of boron, phosphorus, arsenic, antimony, boron, boron fluoride, nitrogen or carbon. 在一些实施例中,通过所选额定电压,以在器件制造中使用的剂量和能量,注入第三高压掺杂物。 In some embodiments, the selected nominal voltage, in a dose and energy used in the device fabrication, the third high pressure dopant implantation.

[0075] 在一些实施例中,假定在形成多个高压浅阱414b和多个高压口袋注入区428b之后,在多个高压浅阱414b和多个高压口袋注入区428b之上形成多个第二栅极结构430b,多个高压浅阱414b、多个高压口袋注入428b或多个第二源极漏极区444b中的至少一个关于相应的第二栅极结构430b不对称。 [0075] In some embodiments, it is assumed that after forming a plurality of shallow wells 414b and a plurality of high-pressure high-pressure pocket implantation region 428b, forming a second plurality of high pressure over the plurality of shallow wells 414b and a plurality of high-pressure pocket implantation region 428b gate structure 430b, a plurality of shallow high pressure wells 414b, 428b or a plurality of high-pressure pocket implantation plurality of second source drain region 444b asymmetric about at least one respective second gate structure 430b. 根据一些实施例,第二栅极结构相对于第二栅极结构一侧上的高压浅阱、高压口袋注入区或第二源极漏极区中的至少一个的重叠度不同于第二栅极结构相对于第二栅极结构另一侧上的高压浅阱、高压口袋注入区或第二源极漏极区中的至少一个的重叠度。 According to some embodiments, a second gate structure with respect to the degree of overlap of the high-pressure different from the second gate electrode on the side of the second shallow-well gate structure, a high-pressure pocket implantation region or the second source-drain region of at least one of configuration with respect to the degree of overlap shallow high pressure wells on the other side of the second gate structure, a high-pressure pocket implantation region or the second source-drain region of at least one. 根据一些实施例,与当第二晶体管被反向偏置时相比,当第二晶体管被正向偏置时,在第二栅极结构周围注入的掺杂物的这种不对称产生不同特征曲线。 According to some embodiments, as compared with when the second transistor is reverse biased when the second transistor is forward biased, in which the second gate structure surrounding the implanted dopant asymmetric produce different characteristics curve.

[0076] 根据一些实施例,一种半导体制造方法包括:形成具有第一工作电压的多个第一晶体管,多个第一晶体管包括在衬底的第一晶体管区域之上的多个第一栅极结构、邻近多个第一栅极结构的多个低压浅阱、以及邻近第一栅极结构的多个低压口袋注入区。 [0076] According to some embodiments, a method of manufacturing a semiconductor comprising: forming a first transistor having a first plurality of operating voltage, a first plurality of transistors comprises a first transistor over a plurality of first gate region of the substrate a plurality of low-pressure pocket implantation region electrode structure, a plurality of low pressure adjacent the shallow well of the first plurality of gate structures, and adjacent the first gate structure. 根据一些实施例,半导体制造方法进一步包括:邻近多个第一晶体管形成具有第二工作电压的多个第二晶体管。 According to some embodiments, a semiconductor manufacturing method further comprising: a first plurality of transistors is formed adjacent to the plurality of second transistors having a second operating voltage. 在一些实施例中,形成多个第二晶体管包括:在多个第一栅极结构之上、在第一晶体管区域之上并且在多个第二栅极结构之上形成第一高压光刻胶,并且多个第二栅极结构在衬底的第二晶体管区域之上,从而暴露邻近多个第二栅极结构的衬底的多个高压注入区和多个第二栅极结构的多个第二栅极顶部。 In some embodiments, a plurality of second transistors comprise: a first gate structure over a plurality of, and forming a first photoresist over a plurality of high voltage gate structure over a second region of the first transistor a plurality of a plurality of high-pressure injection zone, and a second plurality of transistor gate structures over the second region of the substrate, exposing the substrate adjacent to the plurality of second gate structure and a plurality of second gate structure The second top gate. 在一些实施例中,形成多个第二晶体管进一步包括:以第一高能量执行高压LDD注入,以将第一高压掺杂物注入到多个高压注入区中,以形成邻近多个第二栅极结构的多个高压浅阱,并且以第二高能量执行高压口袋注入, 以将第二高压掺杂物注入到多个高压注入区中,以形成邻近多个第二栅极结构的多个高压口袋注入区。 In some embodiments, a plurality of second transistors further comprising: performing a first high-pressure high-LDD implant energy to the dopants into the first high pressure to a plurality of high-pressure injection zone to form a second plurality of adjacent gate a plurality of shallow high pressure wells electrode structure, and performing a second high-pressure pocket implantation at a high energy, high voltage to a second dopant implanted into the plurality of high-pressure injection zone to form a plurality of gate structures adjacent the second plurality high-pressure pocket implantation region.

[0077] 根据一些实施例,一种半导体制造方法包括:在衬底的第一晶体管区域和衬底的第二晶体管区域之上形成第一高压光刻胶,并且图案化第一高压光刻胶,以形成第一晶体管区域之上的高压光刻胶和第二晶体管区域之上的多个高压残留光刻胶,从而暴露邻近多个高压残留光刻胶的衬底的多个高压注入区。 [0077] According to some embodiments, a method of manufacturing a semiconductor comprising: forming a first photoresist on the second high-voltage transistor region of the first transistor and the substrate region of the substrate, and patterning the first resist high pressure to form a high pressure region of the photoresist over the first transistor and a plurality of second high voltage transistor above the remaining photoresist regions, thereby exposing the remaining photoresist adjacent the substrate a plurality of high-pressure high-pressure injection of a plurality of regions. 根据一些实施例,半导体制造方法进一步包括:以第一高能量执行高压LDD注入,以将第一高压掺杂物注入多个高压注入区中,以形成邻近多个高压残留光刻胶的多个高压浅阱,并且以第二高能量执行高压口袋注入,以将第二高压掺杂物注入到多个高压注入区中,以形成邻近多个高压残留光刻胶的多个高压口袋注入区。 According to some embodiments, a semiconductor manufacturing method further comprising: performing a first high-voltage LDD high energy implantation, a first high pressure to a plurality of dopants into the high-pressure injection zone to form a plurality of high pressure adjacent the remaining photoresist plurality shallow high pressure wells, and performing a second high-pressure pocket implantation at a high energy, high pressure to be injected into the plurality of high pressure injection region a second dopant to form a plurality of high pressure near the high pressure residual photoresist plurality of pocket implantation region.

[0078] 根据一些实施例,注入掺杂物的方法包括:在栅极结构之上沉积光刻胶,栅极结构在衬底之上;图案化光刻胶,使得光刻胶在栅极结构的顶面的一部分之上而不是所有部分之上,使得光刻胶的光刻胶宽度小于栅极结构的栅极结构宽度;以及在光刻胶在栅极结构之上时,将第一掺杂物注入衬底中,以在邻近栅极结构的衬底中形成第一掺杂区。 [0078] The method according to some embodiments, implanted dopant comprises: depositing a photoresist over the gate structure, a gate structure over a substrate; patterned photoresist, the photoresist so that the gate structure over a portion of the top surface but not on all portions of the photoresist such that the photoresist width is smaller than the width of the gate structure of the gate structure; and when the photoresist over the gate structure, the first dopant impurities implanted into the substrate to form a first doped region in the substrate adjacent to the gate structure.

[0079] 以上概述了多个实施例的特征,使得本领域技术人员可以更好地理解本公开的多个方面。 [0079] The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. 本领域技术人员将想到,它们可以容易地使用本公开作为用于设计或修改用于实现与在此介绍的实施例相同的目的和/或实现与其相同的优点的其他处理和结构的基础。 Those skilled in the art will occur, they may readily use the present disclosure as a basis for designing or modifying for achieving and / or base thereto to achieve the same advantages of other processes and structures of the objects of the same embodiment described herein. 本领域技术人员还将认识到,这样的等效结构不脱离本公开的精神和范围,并且它们可以在不脱离本公开的精神和范围的情况下,在此作出多种改变、替换和更改。 Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they may be made without departing from the spirit and scope of the present disclosure, this make various changes, substitutions and alterations.

[0080] 在此提供实施例的多种操作。 [0080] In this embodiment provides various operations. 描述一些或所有操作的顺序应该不被解释为暗示这些操作必须是顺序依赖的。 Some or all of the described sequence of operations should not be construed as to imply that these operations are necessarily order dependent. 将想到具有本说明书的益处的可选排序。 Alternatively sort will occur having the benefit of the present specification. 而且,将理解,不是所有操作都必须出现在在此提供的每个实施例中。 Furthermore, it will be appreciated that not all operations are necessarily present in each embodiment provided herein. 而且,将理解,不是所有操作在一些实施例中都是必须的。 Furthermore, it will be appreciated that not all operations in some embodiments, are necessary.

[0081] 将想到,在一些实施例中,例如,为了简单和容易理解的目的,在此描述的层、特征、元件等通过关于另一个的特定尺寸被示出,诸如,结构尺寸或定向,并且其实际尺寸基本不同于图中所示的尺寸。 [0081] A contemplated that in some embodiments, e.g., for purposes of simplicity and ease of understanding, the particular size on the other by layers, features, and other elements described herein is illustrated, such as a size or orientation of the structure, and it is substantially different from the actual size of the dimensions shown in FIG. 另外,例如,多种技术存在用于形成在此所述的层、特征、元件等,诸如,蚀刻技术、注入技术、掺杂技术、旋涂技术、诸如磁控管或离子束溅射的溅射技术、 诸如热生长的生长技术、或者诸如化学气相沉积(CVD)、物理气相沉积(PVD)、等离子体增强化学气相沉积(PECVD)、或原子层沉积(ALD)的沉积技术。 Further, for example, a variety of techniques exist for forming layers, features, and other elements described herein, such as etching techniques, injection techniques, doping techniques, spin coating techniques, such as magnetron sputtering or ion beam sputtering radio technology, such as thermally grown growth techniques, such as chemical vapor deposition or (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition techniques deposition (ALD) of.

[0082] 而且,在此使用"示例性"意味着用作实例、例子、例证等,并且不必须有利。 [0082] Further, as used herein, "exemplary" is meant as an example, instance, illustration, etc., and is not necessarily advantageous. 如在本申请中使用的,"或者"是指包含性"或者"而不是排他性"或者"。 As used in this application, "or" it refers to an inclusive "or" rather than an exclusive "or." 另外,除非另外或者从上下文清楚地指示是单数形式,在本申请和所附权利要求中使用的"一个(a)"和"一个(an)"通常被解释为是指"一个或多个"。 Further, unless otherwise indicated or clear from the context singular form, as used in this application and the appended claims, "a (A)" and "a (AN)" generally be construed to mean "one or more" . 而且,A和B等中的至少一个通常是指A或B或者A和B。 Moreover, A and B, and the like generally refers to at least one of A or B or A and B. 而且, 在某种意义上,使用"包括(include) "、"具有(having) "、"具有(has) "、"具有(with) "或其变体,这样的术语以类似于术语"包括(comprising)"的方式为包含性的。 Further, in a sense, use of "including (the include)", "having (HAVING)", "have (has)", "having (with)" or variants thereof, such terms similar to the term "comprising (comprising) "ways to be inclusive. 而且,除非另外指出,"第一"、"第二"等不旨在暗示时间方面、空间方面、排序等。 Furthermore, unless otherwise indicated, "first", "second", etc. are not intended to imply terms of time, space, sorting and so on. 而是,这样的术语仅用作用于特征、元件、项等的标识符、名称等。 Rather, such terms are used only as to the feature, element, item, etc. identifiers, names, etc. 例如,第一元件和第二元件通常对应于元件A和元件B 或者两个不同或者两个相同元件或同一元件。 For example, the first and second elements generally correspond to the elements A and B or two identical or two different elements or of the same element.

[0083] 而且,虽然关于一个或多个实现示出和描述了本公开,但是基于本说明书和附图的读取和理解,等效更改和修改对于本领域技术人员将发生。 [0083] Further, although with respect to one or more implementations shown and described the present disclosure, the present specification and drawings but based on reading and understanding, equivalent alterations and modifications to the skilled artisan will occur. 本公开包括所有这样的修改和更改,并且仅由以下权利要求的范围限制。 The present disclosure includes all such modifications and alterations and is limited only by the limits of the following claims. 特别是关于由上述组件(例如,元件、资源等) 执行的多种功能,除非另外指出,即使在结构上不等效于所公开的结构,用于描述这样的组件的术语旨在对应于执行所描述的组件的指定功能的任何组件(例如,功能上等效)。 Particularly with regard to the various functions performed by the above described components (e.g., elements, resources, etc.), unless otherwise indicated, even though not structurally equivalent to the disclosed structure in the structure, such terms used to describe the components are intended to correspond, any component of the specified function of the described component (e.g., that is functionally equivalent). 另外, 虽然已经关于多种实现中的仅一种描述了本公开的特定特征,但是当可能期望并且有利于任何给定或特定应用时,这样的特征可以与其他实现的一个或多个其他特征结合。 Additionally, while various implementations on a description of only certain features of the disclosure, but when it may be desirable and advantageous for any given or particular application when such feature may be implemented with one or more other features of other combined.

Claims (20)

  1. 1. 一种半导体制造方法,包括: 形成具有第一工作电压的多个第一晶体管,所述多个第一晶体管包括在衬底的第一晶体管区域之上的多个第一栅极结构、邻近所述多个第一栅极结构的多个低压浅阱、以及邻近所述多个第一栅极结构的多个低压口袋注入区;以及邻近所述多个第一晶体管形成具有第二工作电压的多个第二晶体管,形成所述多个第二晶体管包括: 在所述多个第一栅极结构之上、在所述第一晶体管区域之上并且在多个第二栅极结构之上形成第一高压光刻胶,所述多个第二栅极结构在所述衬底的第二晶体管区域之上,使得暴露邻近所述多个第二栅极结构的所述衬底的多个高压注入区和所述多个第二栅极结构的多个第二栅极顶部; 以第一高能量执行高压LDD注入,以将第一高压掺杂物注入到所述多个高压注入区中, 从而形成邻近所述多个第二 A semiconductor manufacturing method, comprising: forming a first plurality of transistors having a first operating voltage, said first plurality of transistors comprises a first plurality of transistor gate structure over the first region of the substrate, a plurality of low pressure adjacent the shallow well of the first plurality of gate structures, and a plurality of low pressure adjacent to the plurality of pocket implantation region of the first gate structure; and adjacent to the first plurality of transistors are formed having a second work a plurality of voltage of the second transistor, forming the second plurality of transistors comprises: a first gate over the plurality of structures, in the region over the first transistor and a second plurality of gate structures forming a first photoresist on the high voltage, a plurality of second gate structure over the substrate area of ​​the second transistor, such that the plurality of exposed proximate the second gate structure of the multi-substrate a plurality of high-pressure injection region and the second plurality of gate structures of the top of the second gate electrode; performing a first high-voltage LDD implant at high energy, high voltage to a first dopant into said plurality of high-pressure injection zone so as to form adjacent the second plurality 栅极结构的多个高压浅阱;以及以第二高能量执行高压口袋注入,以将第二高压掺杂物注入到所述多个高压注入区中,从而形成邻近所述多个第二栅极结构的多个高压口袋注入区。 A plurality of gate structures shallow high pressure wells; and performing a second high-energy high-pressure pocket implantation, a high pressure to a second dopant into said plurality of high-pressure injection zone, thereby forming a plurality of second gate adjacent the a plurality of high-pressure pocket implantation region pole structure.
  2. 2. 根据权利要求1所述的方法,形成所述多个第一晶体管包括: 在所述第二晶体管区域之上并且在所述多个第二栅极结构之上形成低压光刻胶,使得暴露所述多个第一栅极结构和邻近所述多个第一栅极结构的所述衬底的多个低压注入区; 以第一低能量执行低压LDD注入,以将第一电压掺杂物注入到所述多个低压注入区中, 从而形成所述多个低压浅阱;以及以第二低能量执行低压口袋注入,以将第二低压掺杂物注入到所述多个低压注入区中,从而形成所述多个低压口袋注入区。 2. The method according to claim 1, forming the first plurality of transistors comprising: a low pressure and a photoresist is formed over the second gate structure over the plurality of the second transistor region, so that exposing the plurality of first gate structure and the substrate adjacent to the plurality of the first plurality of gate structures a low pressure injection zone; performing a first low-power low-voltage LDD implantation, doped to a first voltage It was injected into the plurality of low-pressure injection region, thereby forming a plurality of shallow low pressure wells; and performing a second low-pressure pocket implantation energy low, low pressure to a second dopant into said plurality of low-pressure injection zone thereby forming a plurality of low-pressure pocket implantation region.
  3. 3. 根据权利要求1所述的方法,包括: 在所述衬底之上形成第一层栅极介电材料; 从所述衬底的所述第一晶体管区域去除所述第一层栅极介电材料,使得高压栅极电介质的第一部分留在所述衬底的所述第二晶体管区域之上; 在所述衬底之上并且在所述高压栅极电介质的所述第一部分之上形成第二层栅极介电材料,使得低压栅极电介质留在所述衬底的所述第一晶体管区域之上,并且所述高压栅极电介质留在所述衬底的所述第二晶体管区域之上,其中,所述高压栅极电介质包括所述第一部分和来自所述第二层栅极介电材料的第二部分; 在所述低压栅极电介质和所述高压栅极电介质之上形成栅电极材料层;以及图案化所述栅电极材料层、所述低压栅极电介质和所述高压栅极电介质,以同时形成多个第一栅极结构和所述多个第二栅极结构。 3. The method according to claim 1, comprising: forming a first layer of gate dielectric material over the substrate; removing the first layer from the gate of the first transistor region of the substrate a dielectric material, such that the first portion of the high pressure left the gate dielectric over the transistor region of said second substrate; over the substrate and the high pressure over the first portion of the gate dielectric forming the second layer of gate dielectric material, such that the low-voltage gate over the dielectric to remain in the substrate region of a first transistor, and the gate high voltage remaining in the dielectric substrate second transistor over the region, wherein the gate dielectric comprises a high-pressure portion and said first portion from said second gate dielectric layer of a second material; gate dielectric over the low and the high gate dielectric forming a gate electrode material layer; and patterning the gate electrode material layer, the gate low voltage and the high dielectric gate dielectric, to simultaneously form a first plurality of gate structures and said second plurality of gate structures .
  4. 4. 根据权利要求1所述的方法,包括: 在所述多个第一栅极结构、所述多个第二栅极结构和所述衬底之上形成侧壁材料层; 以及图案化所述侧壁材料层,以同时形成邻近所述多个第一栅极结构的多个第一侧壁隔离物和邻近所述第二栅极结构的多个第二侧壁隔离物。 And patterning the; first plurality of said gate structure, said plurality of sidewall material layer formed over the second gate structure and the substrate: 4. The method according to claim 1, comprising said sidewall material layer to simultaneously form a plurality of adjacent to the plurality of first sidewall spacers and a plurality of the second gate adjacent the first gate structure configuration of the second sidewall spacers.
  5. 5. 根据权利要求1所述的方法,执行低压口袋注入包括:通过所选额定电压,注入在器件制造中使用的剂量。 5. The method according to claim 1, performing the low-pressure pocket implantation comprising: a selected rated voltage, implant dose used in device fabrication.
  6. 6. 根据权利要求1所述的方法,所述多个第一晶体管与所述多个第二晶体管的类型不同。 6. The method according to claim 1, said plurality of first type transistors and the second transistors of the plurality of different.
  7. 7. 根据权利要求1所述的方法,执行所述高压LDD注入包括:注入硼、磷、砷、锑、氟化硼、 氮或碳中的至少一种。 7. The method according to claim 1, performing the high-voltage LDD implant comprising: injecting boron, phosphorous, at least one of arsenic, antimony, boron trifluoride, nitrogen or carbon.
  8. 8. 根据权利要求1所述的方法,执行所述高压口袋注入包括:注入硼、磷、砷、锑、氟化硼、氮或碳中的至少一种。 8. The method according to claim 1, comprising performing the high-pressure pocket implantation: boron is implanted, at least one phosphorus, arsenic, antimony, boron trifluoride, nitrogen or carbon.
  9. 9. 一种半导体制造方法,包括: 在衬底的第一晶体管区域和所述衬底的第二晶体管区域之上形成第一高压光刻胶; 图案化所述第一高压光刻胶,以形成所述第一晶体管区域之上的高压光刻胶和所述第二晶体管区域之上的多个高压残留光刻胶,使得暴露邻近所述多个高压残留光刻胶的所述衬底的多个高压注入区; 以第一高能量执行高压LDD注入,以将第一高压掺杂物注入到所述多个高压注入区中, 从而形成邻近所述多个高压残留光刻胶的多个高压浅阱;以及以第二高能量执行高压口袋注入,以将第二高压掺杂物注入到所述多个高压注入区中,从而形成邻近所述多个高压残留光刻胶的多个高压口袋注入区。 A semiconductor manufacturing method comprising: forming a first photoresist over the first high voltage transistor region of the substrate and a second transistor region of the substrate; patterning the first resist high pressure, in order to the photoresist is formed over the first high voltage transistor regions and a plurality of high-pressure residual photoresist on the second transistor region, so that the plurality of high pressure adjacent the exposed residual photoresist of the substrate a plurality of high-pressure injection zone; performing a first high-voltage LDD implant at high energy, high voltage to a first dopant into said plurality of high-pressure injection zone adjacent to the plurality of the plurality of high-pressure residual photoresist to form shallow high pressure wells; and a second high-energy high-pressure pocket implantation performed to inject the high-pressure injection into said plurality of second high dopant region, thereby forming a plurality of high pressure adjacent the plurality of high-pressure residual photoresist pocket implantation region.
  10. 10. 根据权利要求9所述的方法,包括: 形成所述第一晶体管区域中的多个第一栅极结构和所述第二晶体管区域中的多个第二栅极结构; 在所述多个第一栅极结构和所述多个第二栅极结构之上形成第一低压光刻胶; 图案化所述第一低压光刻胶,以在所述第二晶体管区域之上和所述多个第二栅极结构之上形成低压光刻胶,使得暴露所述多个第一栅极结构和邻近所述多个第一栅极结构的所述衬底的多个低压注入区; 以第一低能量执行低压LDD注入,以将第一低压掺杂物注入到所述多个低压注入区中, 从而形成邻近所述多个第一栅极结构的多个低压浅阱;以及以第二低能量执行低压口袋注入,以将第二低压掺杂物注入到所述多个低压注入区中,从而形成邻近所述多个第一栅极结构的多个低压口袋注入区。 10. The method of claim 9, comprising: forming a first plurality of said first gate transistor region and a plurality of structures in the second region a second gate transistor structure; more in the a first gate structure and said plurality of second gate structure formed over a first low-pressure photoresist; patterning the first photoresist low pressure, to above the second transistor and the region a second gate structure is formed over the plurality of low-pressure photoresist is exposed so that the plurality of first gate structure and the substrate adjacent to the plurality of the first plurality of gate structures a low pressure injection zone; to performing a first low-voltage LDD implantation energy low, the low pressure to the first dopant into said plurality of low-pressure injection region, thereby forming a plurality of low pressure adjacent to the plurality of shallow well of the first gate structure; and in the second two low-energy low-pressure pocket implantation performed to the second low dopant into said plurality of low-pressure injection region, thereby forming a plurality of low pressure adjacent to the plurality of pocket implantation region of the first gate structure.
  11. 11. 根据权利要求10所述的方法,包括: 在所述衬底之上形成第一层栅极介电材料; 从所述衬底的所述第一晶体管区域去除所述第一层栅极介电材料,使得高压栅极电介质的第一部分留在所述衬底的所述第二晶体管区域之上; 在所述衬底之上并且在所述高压栅极电介质的所述第一部分之上形成第二层栅极介电材料,使得低压栅极电介质留在所述衬底的所述第一晶体管区域之上,并且所述高压栅极电介质留在所述衬底的所述第二晶体管区域之上,其中,所述高压栅极电介质包括所述第一部分和来自所述第二层栅极介电材料的第二部分; 在所述低压栅极电介质之上和所述高压栅极电介质之上形成一层栅电极材料;以及图案化所述栅电极材料层、所述低压栅极电介质和所述高压栅极电介质,以同时形成所述多个第一栅极结构和所述多个第二栅极结构。 11. The method according to claim 10, comprising: forming a first layer of gate dielectric material over the substrate; removing the first layer from the gate of the first transistor region of the substrate a dielectric material, such that the first portion of the high pressure left the gate dielectric over the transistor region of said second substrate; over the substrate and the high pressure over the first portion of the gate dielectric forming the second layer of gate dielectric material, such that the low-voltage gate over the dielectric to remain in the substrate region of a first transistor, and the gate high voltage remaining in the dielectric substrate second transistor over the region, wherein the gate dielectric comprises a high-pressure portion and said first portion from said second gate dielectric layer of a second material; gate over the low and the high dielectric gate dielectric a layer formed over the gate electrode material; and patterning the gate electrode material layer, the gate low voltage and the high dielectric gate dielectric, to simultaneously form said plurality of gate structures and said first plurality a second gate structure.
  12. 12. 根据权利要求10所述的方法,包括: 在所述多个第一栅极结构、所述多个第二栅极结构和所述衬底之上形成侧壁材料层; 以及图案化所述侧壁材料层,以同时形成邻近所述多个第一栅极结构的多个第一侧壁隔离物和邻近所述多个第二栅极结构的多个第二侧壁隔离物。 12. The method according to claim 10, comprising: a plurality of the first gate structure, said plurality of second gate structure over the substrate and forming a sidewall layer of material; and patterning the said sidewall material layer to simultaneously form a plurality of first gate structures adjacent to the plurality of first sidewall spacers adjacent the gate structure of a second plurality of the plurality of second sidewall spacers.
  13. 13. 根据权利要求10所述的方法,执行所述低压口袋注入包括:通过所选额定电压,注入在器件制造中使用的剂量。 13. The method according to claim 10, performing the low-pressure pocket implantation comprising: a selected rated voltage, implant dose used in device fabrication.
  14. 14. 根据权利要求10所述的方法,所述多个低压口袋注入区与所述多个高压口袋注入区的类型不同。 14. The method according to claim 10, said plurality of different types of low-pressure pocket implantation region and the plurality of high-pressure pocket implantation region.
  15. 15. 根据权利要求9所述的方法, 执行所述高压LDD注入包括:注入硼、磷、砷、锑、氟化硼、氮或碳中的至少一种;和/或执行所述高压口袋注入包括:注入硼、磷、砷、锑、氟化硼、氮或碳中的至少一种。 15. The method as claimed in claim 9, performing the high-voltage LDD implant comprising: boron is implanted, at least one phosphorus, arsenic, antimony, boron trifluoride, nitrogen, and carbon; and / or execution of the high-pressure pocket implantation comprising: implantation of boron, phosphorous, at least one of arsenic, antimony, boron trifluoride, nitrogen or carbon.
  16. 16. 根据权利要求9所述的方法, 执行所述高压LDD注入包括:以基本垂直于所述衬底的表面的角度注入所述第一高压掺杂物;和/或执行所述高压口袋注入包括:以基本垂直于所述衬底的表面的角度注入所述第二高压掺杂物。 16. The method according to claim 9, performing the high-voltage LDD implant comprising: an angle substantially perpendicular to the substrate surface of the first high-pressure injection dopant; and / or execution of the high-pressure pocket implantation comprising: an angle substantially perpendicular to the substrate surface of the second high-pressure injection dopant.
  17. 17. 一种注入掺杂物的方法,包括: 在第一栅极结构和第二栅极结构之上沉积光刻胶,所述第一栅极结构和所述第二栅极结构位于衬底之上; 图案化所述光刻胶,使得所述光刻胶在所述第一栅极结构的顶面而不是所述第二栅极结构的顶面之上,使得所述光刻胶的光刻胶宽度小于所述第一栅极结构和所述第二栅极结构的栅极结构宽度之和;以及在所述光刻胶在所述第一栅极结构之上时,将第一掺杂物注入到所述衬底中,以邻近所述第二栅极结构在所述衬底中形成第一掺杂区。 17. A method of dopant implantation, comprising: depositing a photoresist over the first gate structure and second gate structure, the first gate structure and second gate structure located between the substrate above; patterning the photoresist, the photoresist such that the top surface of the first gate structure instead of over the top surface of said second gate structure, such that the photoresist the photoresist is smaller than the width of the first gate structure and second gate structure and the gate structure width; and when the photoresist over the first gate structure, the first implanting dopant into the substrate, to the second gate structure formed adjacent to a first doped region in the substrate.
  18. 18. 根据权利要求17所述的方法,包括: 在所述光刻胶在所述第一栅极结构之上时,将第二掺杂物注入到所述衬底中,以邻近所述第二栅极结构在所述衬底中形成第二掺杂区。 18. The method according to claim 17, comprising: when in the photoresist over the first gate structure, the second dopant into said substrate, adjacent to the first two gate structure is formed second doped region in the substrate.
  19. 19. 根据权利要求18所述的方法, 注入所述第一掺杂物包括:注入磷、砷、硼、氮或碳中的至少一种;和/或注入所述第二掺杂物包括:注入磷、砷、硼、氮或碳中的至少一种。 19. The method of claim 18, said first implanted dopant comprising: injecting at least one phosphorus, arsenic, boron, nitrogen, and carbon; and / or implanting the second dopant comprises: implanting phosphorus, arsenic, at least one of boron, nitrogen or carbon.
  20. 20. 根据权利要求17所述的方法, 注入所述第一掺杂物包括:以基本垂直于所述衬底的顶面的角度注入所述第一掺杂物;或注入所述第一掺杂物包括:以基本不垂直于所述衬底的顶面的角度注入所述第一掺杂物。 20. The method of claim 17, said first implanted dopant comprising: an angle substantially perpendicular to the top surface of the substrate, said first implanted dopant; or implanting the first dopant debris comprising: a top surface at an angle substantially perpendicular to the substrate, said first implanted dopant.
CN 201410095738 2013-03-15 2014-03-14 And forming a semiconductor arrangement CN104051344B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US201361800767 true 2013-03-15 2013-03-15
US61/800,767 2013-03-15
US14/184,900 2014-02-20
US14184900 US9437494B2 (en) 2013-03-15 2014-02-20 Semiconductor arrangement and formation thereof

Publications (2)

Publication Number Publication Date
CN104051344A true CN104051344A (en) 2014-09-17
CN104051344B true CN104051344B (en) 2017-05-10

Family

ID=51504013

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201410095738 CN104051344B (en) 2013-03-15 2014-03-14 And forming a semiconductor arrangement

Country Status (1)

Country Link
CN (1) CN104051344B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254487A (en) * 1992-05-13 1993-10-19 Nec Corporation Method of manufacturing high and low voltage CMOS transistors on a single chip
CN1366710A (en) * 2000-04-06 2002-08-28 Apd半导体公司 Method of fabricating power rectifier device to vary operating parameters and resulting device
CN1384547A (en) * 2001-05-02 2002-12-11 三菱电机株式会社 Semiconductor device and its manufacture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5254487A (en) * 1992-05-13 1993-10-19 Nec Corporation Method of manufacturing high and low voltage CMOS transistors on a single chip
CN1366710A (en) * 2000-04-06 2002-08-28 Apd半导体公司 Method of fabricating power rectifier device to vary operating parameters and resulting device
CN1384547A (en) * 2001-05-02 2002-12-11 三菱电机株式会社 Semiconductor device and its manufacture

Also Published As

Publication number Publication date Type
CN104051344A (en) 2014-09-17 application

Similar Documents

Publication Publication Date Title
US6927453B2 (en) Metal-oxide-semiconductor device including a buried lightly-doped drain region
US7078776B2 (en) Low threshold voltage semiconductor device
US7081395B2 (en) Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
US7741138B2 (en) Semiconductor device and fabricating method thereof
US20110133292A1 (en) FinFETs with Multiple Fin Heights
US8163619B2 (en) Fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone
US20050029601A1 (en) Structure and method of making strained semiconductor cmos transistors having lattice-mismatched source and drain regions
US20050247926A1 (en) Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
US20110312145A1 (en) Source and drain feature profile for improving device performance and method of manufacturing same
US20090047768A1 (en) Formation of shallow junctions by diffusion from a dielectric doped by cluster or molecular ion beams
US20090096036A1 (en) Semiconductor device and method of manufacturing the same
US20100244106A1 (en) Fabrication and structure of asymmetric field-effect transistors using L-shaped spacers
US20080283926A1 (en) Method for integrating silicon germanium and carbon doped silicon within a strained cmos flow
US20060024873A1 (en) Method of incorporating stress into a transistor channel by use of a backside layer
US20060043430A1 (en) Transistor having an asymmetric source/drain and halo implantation region and a method of forming the same
US6392274B1 (en) High-voltage metal-oxide-semiconductor transistor
US20070210301A1 (en) Semiconductor devices and methods of manufacturing thereof
US20080121997A1 (en) Multi-gate semiconductor device and method for forming the same
US20050242399A1 (en) MOSFET with electrostatic discharge protection structure and method of fabrication
US20120217583A1 (en) Semiconductor device and method for forming the same
US20120139051A1 (en) Source/drain extension control for advanced transistors
US20120132957A1 (en) High performance strained source-drain structure and method of fabricating the same
US20080303060A1 (en) Semiconductor devices and methods of manufacturing thereof
US20120292637A1 (en) Dual Cavity Etch for Embedded Stressor Regions
US20120267715A1 (en) High voltage semiconductor device and method for fabricating the same

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
GR01