CN102337541A - Etching method used in process of manufacturing conical through silicon via (TSV) - Google Patents

Etching method used in process of manufacturing conical through silicon via (TSV) Download PDF

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CN102337541A
CN102337541A CN2011102886691A CN201110288669A CN102337541A CN 102337541 A CN102337541 A CN 102337541A CN 2011102886691 A CN2011102886691 A CN 2011102886691A CN 201110288669 A CN201110288669 A CN 201110288669A CN 102337541 A CN102337541 A CN 102337541A
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etching
tsv
step
stage
front side
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CN2011102886691A
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徐高卫
罗乐
陈骁
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中国科学院上海微系统与信息技术研究所
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Priority to CN2011102886691A priority Critical patent/CN102337541A/en
Publication of CN102337541A publication Critical patent/CN102337541A/en

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Abstract

The invention relates to an etching method used in the process of manufacturing a conical through silicon via (TSV). The method is characterized by comprising the following steps of: depositing a SiO2 layer on the front side of a silicon wafer, and photoetching to remove SiO2 from a graph and expose silicon on the lower side; putting into a special treatment steel (STS) etching machine, and performing first-step etching on the front side of the silicon wafer, wherein an etching stage and a passivation stage are performed alternately in the first-step etching process so as to obtain a vertical deep hole with the depth of 50 to 200 micrometers; and performing second-step etching on the front side of the silicon wafer, and thus obtaining a conical deep hole in an inverted trapezoid shape. The etching method is high in maneuverability and is suitable for industrial production, the process cost of the TSV of a wafer can be expected to be reduced, and the electroplating filling yield of the TSV is improved.

Description

一种制作锥形穿硅通孔时采用的刻蚀方法 A method of making an etching method used when the tapered TSV

技术领域 FIELD

[0001] 本发明涉及一种制作锥形穿硅通孔(Through Silicon Via,TSV)时所使用的刻蚀方法,所述的刻蚀方法可操作性强,适合于工业化生产,不仅降低制作晶圆TSV的工艺成本,而且提高了TSV的电镀填充的成品率。 [0001] The present invention relates to a method for the tapered etching through silicon vias (Through Silicon Via, TSV) used in production, the etching method may be workable, suitable for industrial production, not only reducing the manufacturing crystalline round the TSV process cost, but also increase the yield of filling the TSV plating.

背景技术 Background technique

[0002] 为了满足超大规模集成电路(VLSI)发展的需要,新颖的3D堆叠式封装技术应运而生。 [0002] In order to meet the need for very large scale integration (VLSI) development, innovative 3D stacked packaging technology came into being. 它用最小的尺寸和最轻的重量,将不同性能的芯片和多种技术集成到单个封装体中, 是一种通过在芯片和芯片之间、晶圆和晶圆之间制造垂直电学导通,实现芯片之间互连的最新的封装互连技术,与以往的IC封装键合和使用凸点的叠加技术不同,所述的封装互连技术是采用TSV(Thrc)Ugh Silicon Via,穿硅通孔)代替了2D_Cu互连,能够使芯片在三维方向堆叠的密度最大,外形尺寸最小,并且大大改善芯片速度和低功耗的性能。 It is with the smallest size and the lightest weight, the performance of the chips and various different technologies into a single package, by between a chip and the chip, producing vertical electrical conduction between the wafer and the wafer , the interconnection between the chip package interconnect the latest technology, the conventional IC package and bonding using bumps overlay techniques, the technique is the use of package interconnect TSV (thrc) Ugh silicon Via, through silicon vias) instead 2D_Cu interconnection can be made the maximum and minimum dimensions of the chip stack density in three dimensions, and greatly improve the performance of the chip speed and low power consumption. 因此,日月光公司集团研发中心总经理唐和明博士在Chartered2007技术研讨会上将TSV称为继线键合(Wire Bonding)、载带自动焊(TAB)和倒装芯片(FC)之后的第四代封装技术。 Thus, general manager of the company D Center Dr. Tang Huoming ASE Chartered2007 Seminars on the following referred TSV wire bonds (Wire Bonding), after the tape automated bonding (TAB) and flip chip carrier (FC) of the fourth-generation package technology.

[0003] 为了实现IC器件的TSV晶圆级封装,需要完成几个重要工艺技术的开发。 [0003] In order to realize TSV wafer level packaged IC devices, it is necessary to complete the development of several important technology. (1)通孔制备,采用DRIE在晶圆上制备高深宽比的Si通孔;⑵通孔电镀,在通孔侧壁上淀积SW2 绝缘层后,通过种子层电镀金属Cu使充满整个Si通孔;(3)化学机械抛光(CMP),采用CMP 将过量的Cu研磨掉后继续研磨晶圆可以获得不同厚度TSV圆片;(4)圆片与圆片或芯片与圆片之间的精确对准后的键合工艺。 (1) Preparation of the through hole, the through hole Si DRIE prepared using high aspect ratio on a wafer; ⑵ through-hole plating, the insulating layer is deposited SW2 on the sidewalls of the via, through the seed layer so that the plated metal fills the Si Cu the through-hole; (3) a chemical mechanical polishing (CMP), using the excess Cu CMP polishing after grinding off the wafer continues to be obtained with different thickness TSV wafer; (4) with the wafer and the wafer or chip wafer after the bonding process accurate alignment. 在上述几个重要工艺当中,TSV的刻蚀是很关键的一个工序。 In the process among the several important, TSV etching is a critical step. 考虑到成本,精度控制等因素,一般倾向于使用干法刻蚀来制作TSV。 Considering the cost, precision control and other factors, generally we tend to make the use of dry etching TSV. 刻蚀过程比较复杂,不同的三维IC中通孔的分布位置、密度和尺寸(包括孔深和孔径)是不同的。 The etching process is complex, the distribution of the through-holes in different positions of the IC dimensional, density and size (including pore size and hole depth) is different. 通孔技术需要能满足对轮廓形状的控制(包括控制倾斜度、形状、粗糙度、过刻蚀等),同时又要求工艺能具有可靠性、实用性和重复性,最后,成本也要能被合理控制。 Through-hole technology to meet the need to control the shape of the contour (including tilt control, shape, roughness, over etching), while the process requirements can have reliable, practical, and reproducible, finally, the cost should be reasonable control. TSV的制作一般使用BOSCH工艺刻蚀,这是一种基于等离子刻蚀的深硅刻蚀工艺。 TSV typically produced using BOSCH etching process, which is a deep silicon etch process is based on plasma etching. 在刻蚀过程中通过快速循环切换刻蚀和沉积,即在每个刻蚀循环周期中,暴露的硅被各向同性刻蚀,再沉积一层聚合物来保护,然后聚合物被分解去除,暴露的硅再被蚀刻,周而复始,直至程序结束。 In the etching process is switched by flash etch and deposition cycles, i.e. at each cycle the etching, the exposed silicon is isotropically etched, and then depositing a layer of polymer to protect, then the polymer is decomposed and removed, the exposed silicon is then etched, again and again, until the end of the program. 从而实现深度刻蚀,而且通孔侧边非常垂直。 In order to achieve the etching depth, and the through hole is perpendicular to the sides. 垂直式通孔有利于提升通孔的数量和密度,但是对于TSV这种具有垂直侧壁、高深宽比的结构,后续的绝缘层、阻挡层和种子层的沉积,以及TSV 电镀工艺都很难达到要求,具有极高的工艺难度,增加了制作成本。 Vertical lift through Kongyou Li in number and density of through-holes, but for such a TSV having vertical sidewalls, high aspect ratio structures, the subsequent insulating layer, a barrier layer and seed layer deposition, and electroplating processes are difficult to TSV meet the requirements, with a high difficulty of the process, increased production costs. 后续沉积工艺较难控制。 Subsequent deposition process is difficult to control. 比如薄膜的沉积,由于垂直型的TSV孔径很小,深度很大,因此传统的沉积工艺只能沉积在TSV开口处,而在TSV较深处的侧壁和底部很难沉积;在TSV电镀方面,由于电镀液的Cu2+在TSV的开口处扩散移动速度明显大于TSV孔深处的速度,因此电镀速度的差异使得铜更多沉积在垂直TSV的开口处,从而导致TSV开口被铜填充堵死,而孔内形成空洞。 For example the deposited film, since the vertical type TSV small aperture, the depth is large, thus only a conventional deposition process is deposited TSV openings, while the deeper sidewalls and bottom of the TSV hardly deposited; TSV plating in terms of , Cu2 + since the opening of the TSV plating solution is significantly greater than the speed of the moving speed of the diffusion depths of the TSV hole, so that the difference of plating speed of copper deposition in the more vertical the TSV opening, resulting in blocked TSV openings are filled with copper, formation of voids and pores.

发明内容 SUMMARY

[0004] 为了能够降低TSV的制作工艺难度,解决TSV刻蚀后的后续工艺的实现,本发明的 [0004] In order to reduce the difficulty of the production process of the TSV, implementations that solve TSV subsequent process after the etching, the present invention

3目的在于提供一种制作锥形(倒梯形)TSV的工艺方法,所述的锥形实际是倒梯形,即上面大下面小的一种锥形。 A third object is to provide a production conical (inverted trapezoidal shape) of the TSV process, said cone is actually an inverted trapezoid, i.e., a little below the top cone large.

[0005] 本发明的技术方案是:制作锥形TSV的刻蚀分两步,首先沉积一层1. 5_3μπι的SiO2层,将光刻后SiA作为刻蚀掩膜,然后进行第一步刻蚀,即采用BOSCH刻蚀工艺形成垂直侧壁的深孔,BOSCH工艺的方法是首先进行钝化,通入一定流的量C4F4气体6秒钟,形成钝化层,然后通入一定流量的气体SF6, 5秒钟去除钝化层,并进行Si基材的刻蚀,在刻蚀的步骤中,附着在先前附着层上的部分侧壁聚合物,也就是先前C4F4气体离化后产生的C、CF2 或C2F4等粒子,在硅表面沉积形成聚合物,而形成的聚合物是一种可调整的侧壁钝化层, 该钝化层在非垂直离子碰撞侧壁的影响下,脱离侧壁再次移动,重新在更深的侧壁上附着。 [0005] aspect of the present invention are: production of a two-step tapered TSV etching, the first layer of SiO2 is deposited 1. 5_3μπι will SiA after photolithography as an etch mask, then etching the first step , i.e. BOSCH etching process using deep vertical sidewalls are formed, the method BOSCH process is first passivated, leads to a certain amount of C4F4 gas stream 6 seconds, forming a passivation layer, and then a constant flow rate into gas SF6 , 5 seconds, the passivation layer is removed, and the Si substrate is etched, the etching step, the attachment in the previous section C sidewall polymer on the adhesive layer, i.e. after previously generated ionization C4F4 gas, or C2F4 CF2 polymer particles, formed polymer is deposited on the silicon surface, is formed by an adjustable sidewall passivation layer, the passivation layer under the influence of a collision in a non-vertical sidewall ionic, again from the side wall moving deeper reattached sidewall. 这样,侧壁上的聚合物薄膜不断地被驱赶向下附着,从而形成一个局部的各向异性刻蚀。 Thus, the polymer film on the side wall is constantly driven downward attached, thereby forming a partial anisotropic etching. BOSCH技术就是通过钝化/刻蚀交替进行来实现垂直深孔的刻蚀,整个工艺参数是在STS干法刻蚀机上设置的,BOSCH工艺进行的时间决定了钝化/刻蚀交替的次数,并且与刻蚀的深孔深度成正比关系。 BOSCH technique is through the passivation / etching alternately deep vertical etching is achieved, the entire process parameters is provided in the STS dry etching machine, time determines the BOSCH process for passivating / etching times alternately, and proportional to the depth of the deep hole etching. 然后进行第二步刻蚀,只通入刻蚀气体SF6,由于刻蚀气体含量沿着孔开口处向孔底部方向逐渐减少,随着刻蚀时间的不同,可以实现不同比例的锥形形貌。 Then the second step etching, the etching gas of SF6 into only, since the etching gas content gradually decreases toward the bottom of the bore hole opening direction, with the etching time can be achieved in different ratios tapered morphology .

[0006] 本发明的有益效果:该发明工艺简单而能够实现后续的高质量的薄膜沉积和电镀工艺,避免了上述工艺因为垂直侧壁TSV而重新大量研发的成本,并且该发明工艺可操作性强,适合于工业化生产,不仅降低制作晶圆TSV的工艺成本,而且提高了TSV的电镀填充的成品率。 [0006] Advantageous effects of the present invention: the invention process can be realized simply and subsequent high quality film deposition and electroplating processes, because the above-described process to avoid the cost of re-vertical sidewalls of the TSV considerable research and development, and the operability of the inventive process , suitable for industrial production, the production cost of the process not only reduces the TSV wafer, and improving the yield of filling the TSV plating.

附图说明 BRIEF DESCRIPTION

[0007] 图1是SiA做掩膜、刻蚀前的硅片截面构造图。 [0007] FIG. 1 is a SiA as the mask, the wafer before the etching cross-sectional structure of FIG.

[0008] 图2是进行完第一步刻蚀后获得垂直深孔的硅片截面构造图。 [0008] FIG. 2 is obtained deep vertical etching of the silicon wafer After the first step in cross-sectional configuration of FIG.

[0009] 图3是进行完第二部刻蚀后获得锥形孔的硅片截面构造图。 [0009] FIG. 3 is obtained tapered bore After etching the second wafer portion cross-sectional structure of FIG.

具体实施方式 Detailed ways

[0010] 为了能使本发明的优点和积极效果得到充分体现,下面结合附图和实施例对本发明进一步地说明。 [0010] In order to make the advantages and positive effects of the invention are fully reflected, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0011] 在图1中,在硅片101正面沉积一层3丨02层102,厚度1. 5_3 μ m,SiO2层的厚度取决于需要刻蚀的深孔的深度50-200 μ m,然后光刻图片,将光刻后露出的SW2通过RIE刻蚀去除,露出下面的硅。 [0011] In FIG. 1, 101 in depositing a layer of silicon front layer 3 Shu 02 102, the thickness of 1. 5_3 μ m, depending on the required thickness of the SiO2 layer is etched deep depth of 50-200 μ m, and a lithographic image, the exposed lithographic after SW2 is removed by RIE etching, to expose the underlying silicon.

[0012] 在图2中,放入STS刻蚀机中,对硅片101正面进行第一步刻蚀,刻蚀出深度为50-200 μ m的深孔103,刻蚀的具体参数为: [0012] In FIG. 2, into STS etcher, the first step 101 of the wafer front surface is etched, an etch depth of 50-200 μ m deep hole 103, etching is specific parameters:

[0013] 1.刻蚀阶段:SF6的气体流量为130SCCm ;O2的气体流量为13sCCm ;Coil的功率为600W ;Platen的功率为20W ;压力为^mt ;刻蚀阶段的时间为6s。 [0013] The etching stage 1: SF6 gas flow rate was 130 seem; O2 gas flow rate is 13sCCm; Coil power is 600W; Platen power is 20W; pressure ^ mt; etching stage time was 6s.

[0014] 2.钝化阶段=SF6的气体流量为0 ;C4F8的气体流量为85SCCm ;Coil的功率为600W ; Platen的功率为OW ;压力为17mt ;钝化阶段的时间为k。 [0014] 2. The passivation stage is SF6 gas flow rate = 0; C4F8 gas flow rate was 85SCCm; Coil power is 600W; Platen power is OW; pressure 17mt; passivation stage time to be k.

[0015] 这个步骤中刻蚀阶段与钝化阶段是交替进行的,第一步的总时间为30min-140min,可以获得50-200 μ m深度的TSV,该步的工艺参数适用于各种不同孔径的TSV。 [0015] In this step, the passivation stage etching stage is carried out alternately, the first step in the total time of 30min-140min, 50-200 μ m can be obtained the TSV depth, the process parameters applicable to a variety of different steps TSV aperture. [0016] 在图3中,对硅片101正面进行第二步刻蚀,刻蚀出锥形孔104,刻蚀的具体参数为: [0016] In FIG. 3, the second step 101 of the wafer front surface is etched, etched tapered hole 104, etching is specific parameters:

[0017] SF6的气体流量为130sccm ;O2的气体流量为13sccm ;Coil的功率为700W ;Platen 的功率为20W;压力为12mt ;第二步的总时间为5-17min,可以实现不同比例的锥形形貌, 5min刻蚀时间可以实现TSV的上孔径是其下孔径的1. 2-1. 3倍,随着刻蚀时间的延长,其比例增大,直至刻蚀时间达到17min,比例增大到最大值2-2. 2倍,刻蚀时间继续延长,锥形形貌基本不再发生变化,该步的工艺参数适用于各种不同孔径的TSV。 Gas flow rate [0017] SF6 was 130 seem; O2 gas flow rate is 13sccm; Coil power is 700W; Platen power is 20W; pressure 12mt; Step total time of 5-17min, the taper can be achieved in different proportions shaped morphology, 5min etching time may be implemented on a TSV aperture is 1. 2-1. 3-fold lower aperture, with the extension of the etching time, the proportion of which increases until the etching time reaches 17min, the ratio by 2-2 large maximum 2 times the etching time is further extended, tapered appearance no longer change substantially, the process parameters applicable to the various steps of the TSV aperture.

Claims (5)

1. 一种制作锥形穿硅通孔时采用的刻蚀方法,其特征在于首先在硅片正面沉积一层SiO2,然后光刻去除图形中的SiO2,露出下面的硅。 An etching method used when making TSV tapered, characterized in that first a layer of SiO2 is deposited on the wafer front side, and then removing the lithographic pattern in SiO2, to expose the underlying silicon. 放入STS刻蚀机中,对硅片正面进行第一步刻蚀,第一步刻蚀的过程中刻蚀阶段和钝化阶段交替进行,从而获得出深度为50-200 μ m 的垂直深孔;然后对硅片正面进行第二步刻蚀,刻蚀出具有倒梯形的锥形形貌的深孔。 Into the STS etcher, the wafer front side of the first step etching, the etching process of the first step and in the etching phase alternating passivation stage, to obtain a depth of 50-200 μ m deep vertical hole; then a second step of etching the wafer front side, has a conical etched deep topography of an inverted trapezoidal.
2.按权利要求1所述的方法,具体步骤是:(1)在硅片正面沉积一层SiO2,厚度1. 5-3 μ m,然后光刻,将光刻后露出的SW2通过RIE刻蚀去除,露出下面的硅。 2. The method according to claim 1, the specific steps are: (1) depositing a layer of SiO2 on the wafer front side, a thickness of 1. 5-3 μ m, and then photolithography, the exposed lithographic after SW2 engraved by RIE removing the etching, the underlying silicon is exposed. (2)然后将硅片放入STS刻蚀机中,对硅片正面进行第一步刻蚀,刻蚀出深度为50-200 μ m的深孔,在所述的这个步骤中刻蚀阶段与钝化阶段是交替进行的,第一步的总时间为40min-140min,获得50-200 μ m 深度的TSV。 (2) The wafer is then placed in STS etcher, the wafer front side of the first step etching, the etching depth of 50-200 μ m deep hole, this etching stage in said step the passivation stage is carried out alternately, the first step in the total time of 40min-140min, to obtain 50-200 TSV μ m depth. (3)对硅片正面进行第二步刻蚀,刻蚀出锥形孔,刻蚀的具体参数为=SF6的气体流量为130sccm ;O2的气体流量为13sccm ;Coil的功率为700W ;Platen的功率为20W ;压力为12mt ; 第二步的总时间为5-17min,实现TSV的上孔径是其下孔径的1. 2-2. 2倍。 (3) the second step of the wafer front surface is etched, etched tapered bore, specific parameters of the etching gas flow rate was 130 seem = SF6; O2 gas flow rate is 13sccm; Coil power is 700W; Platen of power is 20W; pressure 12mt; Step total time of 5-17min, the aperture is implemented TSV 1. 2-22 fold lower aperture.
3.按权利要求2所述的方法,其特征在于所述的对硅片正面进行的第一步刻蚀时刻蚀的具体参数为:①刻蚀阶段=SF6的气体流量为130sCCm ;O2的气体流量为13sCCm ;Coil的功率为600W ; Platen的功率为20W ;压力为^mt ;刻蚀阶段的时间为6s ;②钝化阶段=SF6的气体流量为0 ;C4F8的气体流量为85sCCm ;Coil的功率为600W ; Platen的功率为OW ;压力为17mt ;钝化阶段的时间为k。 3. The method according to claim 2, characterized in that the specific parameters of the first step of etching said etched silicon wafer front surface as follows: ① etching stage for the SF6 gas flow rate = 130 seem; of O2 gas flow 13sCCm; Coil power is 600W; Platen power is 20W; pressure ^ mt; 6S etching stage of time; passivating gas flow rate stage ② = SF6 is 0; C4F8 gas flow rate was 85sCCm; Coil of power 600W; Platen power is OW; pressure 17mt; passivation stage time to be k.
4.按权利要求2所述的方法,其特征在于第二步刻蚀时,5min刻蚀时间实现TSV的上孔径是其下孔径的1. 2-1. 3倍;随刻蚀时间延长,其比例增大,直至刻蚀时间达17min,TSV 的上孔径与下孔径的比例增加至最大值2-2. 2倍;刻蚀时间继续延长,锥形形貌基本不再发生变化。 4. The method according to claim 2, characterized in that the etching of the second stage, 5min etching time is implemented on a TSV aperture 1. 2-13 fold lower aperture;. With prolonged etching, proportion increases until the etching time was 17min, the ratio of the pore size and increase the aperture to a maximum of TSV 2-22 times; the etching time is further extended, tapered appearance substantially no longer changes.
5.按权利要求1或2所述的方法,其特征在于第一步刻蚀过程采用BOSCH刻蚀工艺形成垂直侧壁的深孔。 5. The method according to claim 12, characterized in that the first step of the etching process using an etching process of forming the deep BOSCH vertical sidewalls.
CN2011102886691A 2011-09-23 2011-09-23 Etching method used in process of manufacturing conical through silicon via (TSV) CN102337541A (en)

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US10050155B2 (en) 2010-09-18 2018-08-14 Fairchild Semiconductor Corporation Micromachined monolithic 3-axis gyroscope with single drive
US9856132B2 (en) 2010-09-18 2018-01-02 Fairchild Semiconductor Corporation Sealed packaging for microelectromechanical systems
US9278846B2 (en) 2010-09-18 2016-03-08 Fairchild Semiconductor Corporation Micromachined monolithic 6-axis inertial sensor
US9278845B2 (en) 2010-09-18 2016-03-08 Fairchild Semiconductor Corporation MEMS multi-axis gyroscope Z-axis electrode structure
US9586813B2 (en) 2010-09-18 2017-03-07 Fairchild Semiconductor Corporation Multi-die MEMS package
US10065851B2 (en) 2010-09-20 2018-09-04 Fairchild Semiconductor Corporation Microelectromechanical pressure sensor including reference capacitor
US9488693B2 (en) 2012-04-04 2016-11-08 Fairchild Semiconductor Corporation Self test of MEMS accelerometer with ASICS integrated capacitors
US10060757B2 (en) 2012-04-05 2018-08-28 Fairchild Semiconductor Corporation MEMS device quadrature shift cancellation
US9618361B2 (en) 2012-04-05 2017-04-11 Fairchild Semiconductor Corporation MEMS device automatic-gain control loop for mechanical amplitude drive
US9444404B2 (en) 2012-04-05 2016-09-13 Fairchild Semiconductor Corporation MEMS device front-end charge amplifier
US9625272B2 (en) 2012-04-12 2017-04-18 Fairchild Semiconductor Corporation MEMS quadrature cancellation and signal demodulation
US9802814B2 (en) 2012-09-12 2017-10-31 Fairchild Semiconductor Corporation Through silicon via including multi-material fill
US9425328B2 (en) 2012-09-12 2016-08-23 Fairchild Semiconductor Corporation Through silicon via including multi-material fill
CN103663344B (en) * 2012-09-12 2017-02-15 快捷半导体(苏州)有限公司 Improved through silicon via including multi-material fill
CN103663344A (en) * 2012-09-12 2014-03-26 快捷半导体(苏州)有限公司 Improved through silicon via including multi-material fill
CN103811331A (en) * 2012-11-08 2014-05-21 中微半导体设备(上海)有限公司 Etching method of etching hole having inclined side wall
CN103811331B (en) * 2012-11-08 2016-12-21 中微半导体设备(上海)有限公司 A kind of lithographic method with sloped sidewall etched hole
CN104671193A (en) * 2013-12-03 2015-06-03 北京北方微电子基地设备工艺研究中心有限责任公司 Deep silicon etching method
CN105329840A (en) * 2014-06-16 2016-02-17 北京北方微电子基地设备工艺研究中心有限责任公司 Inclined hole etching method
CN107994055A (en) * 2017-11-10 2018-05-04 武汉华星光电半导体显示技术有限公司 Bent display panel and preparation method thereof
CN108461465A (en) * 2018-05-03 2018-08-28 复旦大学 A kind of through-silicon via structure and preparation method thereof

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