CN104671193A - Deep silicon etching method - Google Patents
Deep silicon etching method Download PDFInfo
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- CN104671193A CN104671193A CN201310643211.2A CN201310643211A CN104671193A CN 104671193 A CN104671193 A CN 104671193A CN 201310643211 A CN201310643211 A CN 201310643211A CN 104671193 A CN104671193 A CN 104671193A
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Abstract
The invention provides a deep silicon etching method. The method comprises the following steps: arranging a silicon wafer which is coated with photoresist into a chamber of an etching device, and acquiring the silicon wafer with a steep deep groove shape by adopting a Bosh etching process; then removing the photoresist remaining on the surface of the silicon wafer; and finally, carrying out top opening etching on the silicon wafer in the chamber of the etching device, thereby acquiring the silicon wafer with a V-shaped top. By adopting the deep silicon etching method, the prepared silicon wafer is in a shape that a V-shaped opening is formed in the top, the middle part and the bottom part are steep and the bottom is smooth; moreover, the method is simple in steps and easy to realize.
Description
Technical field
The present invention relates to plasma processing techniques field, particularly relate to a kind of dark silicon etching method.
Background technology
MEMS (Micro Electric-Mechanical System, microelectromechanical systems) to refer in micron dimension Design and manufacture, is integrated with many elements, and is suitable for the mass-produced system of low cost.In 21 century, MEMS is the forward position high-tech with strategic importance, is one of the leading industry in future.It has very wide application prospect with the advantage of its microminiaturization in the industries such as automobile, electronics, household electrical appliances, electromechanics and military field.The main flow process technology of current MEMS is etching technics.Wherein dry etching section anisotropy can realize the conversion of Micropicture, meets more and more less dimensional requirement, has become requisite lithographic method in sub-micron and deep sub-micron technique.
The basic process of plasma etching is (for sense coupling): spray into the process gas needed for chip manufacture by the nozzle of board central upper; Pass into radio-frequency power supply in board upper coil makes the process gas spraying into chamber interior excite as plasma simultaneously; Pass into radio-frequency power supply at the electrostatic chuck of supporting wafers, produce bias voltage, make the surface of plasma bombardment wafer, thus on wafer, etch required figure.Product in etching process is taken away by molecular pump and dry pump.Dry pump is the fore pump of molecular pump.In etching process, reaction can be released or be absorbed heat, therefore needs bottom electrostatic chuck to connect cooler to keep temperature, ensures the uniformity of etching.
The deep etching of silicon is etching technics common in current MEMS, based on different application, there is different requirements to the etch topography of silicon, to meet other follow-up process requirements.
In the deep etching of silicon, for obtaining top V-type opening, middle part and bottom is steep, bottom is smooth pattern, generally adopt single step etching method.Its main feature is: by regulating lower electrode power (Bias Radio Frequency, BRF) different lateral pattern is obtained: adopt higher BRF can obtain more straight sidewall profile, adopt lower BRF can obtain the sidewall profile comparatively tilted.Typical manufacturing process is: pressure is 33mT, and upper electrode power is 500W, and lower electrode power is 100W, and the process gas passed into is SF
6and O
2, and SF
6flow is 105sccm, O
2flow is 68sccm, and etch period is 600s.Fig. 1 is the scanning electron microscope (SEM) photograph that the more typical silicon using above-mentioned typical manufacturing process to obtain cuts open sheet, as seen from the figure, this technique effectively cannot control the pattern of opening, etching bottom lateral feature dimensions is shunk serious, and along with the prolongation of etch period, etching can stop, and can not form middle part and bottom is steep, bottom is smooth pattern.
Summary of the invention
Based on the problems referred to above, the invention provides a kind of dark silicon etching method, top V-type opening, middle part and bottom is steep, bottom is smooth pattern can be obtained.
The present invention adopts following technical scheme:
A kind of dark silicon etching method, comprises the steps:
The silicon wafer scribbling photoresist is put into the chamber of etching apparatus, adopt Bosh etching technics, obtain the silicon wafer with steep deep trench pattern;
There is described in removal the remaining photoresist of silicon wafer surface of steep deep trench pattern;
In the chamber of described etching apparatus, open top etching is carried out to the silicon wafer removing photoresist, obtain the silicon wafer with V-type top pattern.
Wherein in an embodiment, in Bosh etching process, in the chamber of described etching apparatus, pressure is 60mT ~ 80mT.
Wherein in an embodiment, described Bosh etching technics comprises deposition steps and etching step, and the two hockets; The gas passed in described deposition steps is C
4f
8, flow is 180sccm ~ 200sccm; The gas passed in described etching step is SF
6, flow is 200sccm ~ 220sccm.
Wherein in an embodiment, the upper electrode power that described deposition steps adopts is 300W ~ 5000W, and lower electrode power is 0W; The upper electrode power that described etching step adopts is 300W ~ 5000W, and lower electrode power is 10W ~ 30W.
Wherein in an embodiment, adopt chemical reagent to soak or there is described in ultrasonic removal the remaining photoresist of silicon wafer surface of steep deep trench pattern.
Wherein in an embodiment, acetone is adopted to soak the silicon wafer surface remaining photoresist described in removal with steep deep trench pattern, comprise the following steps: the described silicon wafer with steep deep trench pattern is soaked 2min in acetone soln, takes out rear washed with de-ionized water, then use N
2air gun dries up.
Wherein in an embodiment, described opening etching adopts single step etching, and in described single step etching process, in the chamber of described etching apparatus, pressure is 140mT ~ 160mT.
Wherein in an embodiment, the gas passed in described single step etching is SF
6and O
2mist, and SF
6flow be 500sccm ~ 800sccm, O
2flow be 50sccm ~ 60sccm.
Wherein in an embodiment, in described single step etching, the upper electrode power of employing is 300W ~ 5000W, and lower electrode power is 10W ~ 50W.
Wherein in an embodiment, in described deposition steps, in the chamber of described etching apparatus, pressure is 70mT, and upper electrode power is 2000W, and lower electrode power is 0W, the C passed into
4f
8flow be 200sccm, sedimentation time is 2s;
In described etching step, in the chamber of described etching apparatus, pressure is 70mT, and upper electrode power is 2500W, and lower electrode power is 10W, the SF passed into
6flow be 200sccm, etch period is 5s;
Described deposition steps and etching walk alternate cycles 100 times;
In described single step etching, in the chamber of described etching apparatus, pressure is 150mT, and upper electrode power is 2500W, and lower electrode power is 30W, the SF passed into
6flow be 700sccm, the O passed into
2flow be 50sccm, etch period is 120s.
Dark silicon etching method of the present invention, after the wafer scribbling photoresist is put into etching apparatus, main point three steps are carried out, and the first step controls etching depth and vertical profile, and second step cleans, the 3rd step opening etching, the top pattern needed for acquisition.This method ensure that the silicon wafer obtained has top V-type opening, middle part and bottom is steep, bottom is smooth pattern; And step is simple, easily realizes.
Accompanying drawing explanation
Fig. 1 is the silicon wafer one embodiment scanning electron microscope (SEM) photograph utilizing prior art lithographic method to obtain;
Fig. 2 is the flow chart of the present invention's dark silicon etching method one embodiment;
Fig. 3 is the scanning electron microscope (SEM) photograph adopting the silicon wafer that dark silicon etching method obtains shown in Fig. 2.
Detailed description of the invention
The present invention is described in detail below in conjunction with embodiment.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.
Dark silicon etching method of the present invention uses sense coupling machine to complete, and main technological steps is as follows:
S100: the chamber silicon wafer scribbling photoresist being put into etching apparatus, adopts Bosh etching technics, obtains the silicon wafer (photoresist in this step of the present invention is graphical) with steep deep trench pattern;
S200: remove the remaining photoresist of silicon wafer surface that S100 obtains, to ensure next step open top etching;
S300: carry out open top etching to the silicon wafer that S200 obtains in the chamber of etching apparatus, obtains the silicon wafer with V-type top pattern.
Dark silicon etching method of the present invention, adopts Bosh etching technics, first etches steep deep trench, and recycling single-step method etches the opening of V-type; Ensure that the silicon wafer obtained has top V-type opening, middle part and bottom is steep, bottom is smooth pattern; And the method step is simple, easily realizes.
As a kind of embodiment, Bosh etching technics comprises deposition steps and etching step.The gas passed in deposition steps is preferably C
4f
8, C
4f
8generate the deep trench sidewall surfaces of polymer deposits at silicon wafer, and then oppose side wall is protected; The gas passed in etching step is preferably SF
6, under top electrode radio-frequency power supply, SF
6be activated into plasma, plasma, under the effect of bottom electrode radio-frequency power supply, carries out bombardment etching to silicon wafer.Deposition steps and etching step hocket, and form anisotropic etching, until reach required etching depth.
In deposition steps, C
4f
8flow be 120sccm ~ 200sccm, preferred 180sccm ~ 200sccm; In etching step, SF
6flow be 200sccm ~ 300sccm, preferred 200sccm ~ 220sccm.Larger C
4f
8flow rates in the protection of etched sidewall, to prevent isotropic etching, ensure etching groove steep, simultaneously larger SF
6flow rates is in raising etch rate.
As a kind of embodiment, in Bosh etching technics etching process, the pressure in the chamber of etching apparatus is higher, is generally 50mT ~ 100mT, is preferably 60mT ~ 80mT.Higher pressure is conducive to the ionization level increasing gas, and then increases etch rate.
In Bosh etching technics, the mist passing into reaction chamber ionizes as plasma by top electrode radio-frequency power supply, and bottom electrode radio-frequency power supply article on plasma carries out the surface accelerating to bombard silicon wafer.As a kind of embodiment, the upper electrode power that deposition steps adopts is 300W ~ 5000W, and lower electrode power is 0W; The upper electrode power that etching step adopts is 300W ~ 5000W, and lower electrode power is 10W ~ 60W, preferred 10W ~ 30W.Generally, the generation of higher upper electrode power meeting accelerate plasma, and then accelerate etch rate; And too high lower electrode power can increase the energy of plasma, can cause the damage of etching surface, therefore, lower electrode power is starkly lower than upper electrode power.
Because acetone has good dissolubility for photoresist, as a kind of embodiment, in S200, chemical reagent is adopted to soak or the ultrasonic remaining photoresist of silicon wafer surface removed S100 and obtain.Preferably, the remaining photoresist of silicon wafer surface adopting acetone immersion removal S100 to obtain, comprises the following steps: the silicon wafer obtained by S100 soaks 2min in acetone soln, takes out rear washed with de-ionized water, then use N
2air gun dries up silicon wafer.
As a kind of embodiment, the open top of silicon wafer adopts single step etching, uses higher pressure, is generally 120mT ~ 180mT, preferred 140mT ~ 160mT in process.Higher pressure is conducive to the raising of gas ionization rate in the chamber of etching apparatus, increases etch rate in the same way simultaneously, is conducive to the open top of silicon wafer.
As a kind of embodiment, the gas passed in single step etching is SF
6and O
2mist, and SF
6flow be 500sccm ~ 800sccm, O
2flow be 40sccm ~ 80sccm, preferred 50sccm ~ 60sccm.Compared with the O of large discharge
2be conducive to the protection of the deep trench sidewall of silicon wafer, avoid sidewall damage.
As a kind of embodiment, it is 300W ~ 5000W that single step etches the upper electrode power adopted, and lower electrode power is 10W ~ 50W.In the etching of carrying out opening pattern, the selection of lower electrode power can be carried out according to required open top pattern.Lower lower electrode power is conducive to isotropic etching, makes top pattern rounder and more smooth.
Dark silicon etching method of the present invention, after the wafer scribbling photoresist is put into etching apparatus, main point three steps are carried out, and the first step controls etching depth and steep pattern, and second step cleans, the 3rd step opening etching, the top pattern needed for acquisition.Describe in detail below in conjunction with a specific embodiment.
Embodiment 1
See Fig. 2, it is the flow chart of the present invention's dark silicon etching one embodiment.First the silicon wafer scribbling photoresist is put into sense coupling machine, adopt Bosh etching technics, deposition steps and etching step hocket.
Concrete technology parameter is: in deposition steps, and in the chamber of etching apparatus, pressure is 70mT, and upper electrode power is 2000W, and lower electrode power is 0W, the C passed into
4f
8flow be 200sccm, deposition steps each step time be 2s; In etching step, in the chamber of etching apparatus, pressure is 70mT, and upper electrode power is 2500W, and lower electrode power is 10W, the SF passed into
6flow be 200sccm, etching step each step time be 5s; Deposition steps and etching walk alternate cycles 100 times, obtain the steep deep trench that etching depth is 90 μm.
Then the remaining photoresist of silicon wafer surface is removed, to ensure next step opening.Specific practice is: silicon wafer is soaked 2min in acetone soln, takes out rear washed with de-ionized water, then uses N
2air gun dries up silicon wafer.
Finally opening etching is carried out to silicon wafer, obtain the silicon wafer with V-type top pattern.Utilize single step to etch, and adopt following technological parameter: in the chamber of etching apparatus, pressure is 150mT, upper electrode power is 2500W, and lower electrode power is 30W, the SF passed into
6flow be 700sccm, the O passed into
2flow be 50sccm, etch period is 120s.
Fig. 3 is the scanning electron microscopic picture of silicon wafer obtained after adopting said method etching, and its etching depth is 90 μm, has top V-type opening, middle part and bottom is steep, bottom is smooth pattern.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a dark silicon etching method, is characterized in that, comprises the steps:
The silicon wafer scribbling photoresist is put into the chamber of etching apparatus, adopt Bosh etching technics, obtain the silicon wafer with steep deep trench pattern;
There is described in removal the remaining photoresist of silicon wafer surface of steep deep trench pattern;
In the chamber of described etching apparatus, open top etching is carried out to the silicon wafer removing photoresist, obtain the silicon wafer with V-type top pattern.
2. dark silicon etching method according to claim 1, is characterized in that, in Bosh etching process, in the chamber of described etching apparatus, pressure is 60mT ~ 80mT.
3. dark silicon etching method according to claim 2, is characterized in that, described Bosh etching technics comprises deposition steps and etching step, and the two hockets;
The gas passed in described deposition steps is C
4f
8, flow is 180sccm ~ 200sccm;
The gas passed in described etching step is SF
6, flow is 200sccm ~ 220sccm.
4. dark silicon etching method according to claim 3, is characterized in that, the upper electrode power that described deposition steps adopts is 300W ~ 5000W, and lower electrode power is 0W;
The upper electrode power that described etching step adopts is 300W ~ 5000W, and lower electrode power is 10W ~ 30W.
5. dark silicon etching method according to claim 4, is characterized in that, adopts chemical reagent to soak or has the remaining photoresist of silicon wafer surface of steep deep trench pattern described in ultrasonic removal.
6. dark silicon etching method according to claim 5, is characterized in that, adopts acetone to soak the silicon wafer surface remaining photoresist described in removal with steep deep trench pattern, comprises the following steps:
The described silicon wafer with steep deep trench pattern is soaked 2min in acetone soln, takes out rear washed with de-ionized water, then dry up with N2 air gun.
7. dark silicon etching method according to claim 6, is characterized in that, described opening etching adopts single step etching;
In described single step etching process, in the chamber of described etching apparatus, pressure is 140mT ~ 160mT.
8. dark silicon etching method according to claim 7, is characterized in that, the gas passed in described single step etching is SF
6and O
2mist, and SF
6flow be 500sccm ~ 800sccm, O
2flow be 50sccm ~ 60sccm.
9. dark silicon etching method according to claim 8, is characterized in that, in described single step etching, the upper electrode power of employing is 300W ~ 5000W, and lower electrode power is 10W ~ 50W.
10. dark silicon etching method according to claim 9, is characterized in that,
In described deposition steps, in the chamber of described etching apparatus, pressure is 70mT, and upper electrode power is 2000W, and lower electrode power is 0W, the C passed into
4f
8flow be 200sccm, sedimentation time is 2s;
In described etching step, in the chamber of described etching apparatus, pressure is 70mT, and upper electrode power is 2500W, and lower electrode power is 10W, the SF passed into
6flow be 200sccm, etch period is 5s;
Described deposition steps and etching walk alternate cycles 100 times;
In described single step etching, in the chamber of described etching apparatus, pressure is 150mT, and upper electrode power is 2500W, and lower electrode power is 30W, the SF passed into
6flow be 700sccm, the O passed into
2flow be 50sccm, etch period is 120s.
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Cited By (4)
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| CN106564855A (en) * | 2015-10-08 | 2017-04-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
| CN106847689A (en) * | 2015-12-03 | 2017-06-13 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of deep silicon etching technique |
| CN112164650A (en) * | 2020-09-27 | 2021-01-01 | 西安微电子技术研究所 | Inverted trapezoid-shaped groove etching process method |
| CN114664648A (en) * | 2022-03-15 | 2022-06-24 | 浙江大学 | Silicon etching method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106564855A (en) * | 2015-10-08 | 2017-04-19 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Deep silicon etching method |
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| CN112164650A (en) * | 2020-09-27 | 2021-01-01 | 西安微电子技术研究所 | Inverted trapezoid-shaped groove etching process method |
| CN114664648A (en) * | 2022-03-15 | 2022-06-24 | 浙江大学 | Silicon etching method |
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Application publication date: 20150603 |