CN102315134A - Method for flipping chip by quickly raising and reducing temperature - Google Patents
Method for flipping chip by quickly raising and reducing temperature Download PDFInfo
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- CN102315134A CN102315134A CN2010102212088A CN201010221208A CN102315134A CN 102315134 A CN102315134 A CN 102315134A CN 2010102212088 A CN2010102212088 A CN 2010102212088A CN 201010221208 A CN201010221208 A CN 201010221208A CN 102315134 A CN102315134 A CN 102315134A
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- drop
- temperature rise
- wafer
- rapid temperature
- base material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/38—Effects and problems related to the device integration
- H01L2924/381—Pitch distance
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Abstract
The invention discloses a method for flipping a chip by quickly raising and reducing a temperature. The method comprises the following steps of: arranging at least one chip, at least one bonding material piece and an encapsulation base material of a positioning jig; conveying the positioning jig into a reaction cavity body of a quick temperature raising and reducing device; heating the chip, the bonding material piece and the encapsulation base material by using a heating source of the quick temperature raising and reducing device, and making the chip, the bonding material piece and the encapsulation base material produce different temperatures according to a temperature partitioned and layered control characteristic of the device, wherein the thermal expansion difference of the chip, the bonding material piece and the encapsulation base material is smaller than a default value at the heating temperature, and the bonding material piece can be melted at the heating temperature so as to bond the chip and the encapsulation base material; and cooling the chip, the bonding material piece and the encapsulation base material so as to finish a chip flipping process. Due to a proper temperature gradient, the problems of atom dislocation and staggering, caused by different thermal deformation values, of welding points can be solved.
Description
Technical field
The present invention relates to a kind of crystal method that covers, especially utilize localization tool and rapid temperature rise and drop system to cover brilliant method to reach rapid temperature rise and drop.
Background technology
In the prior art; Flip chip assembly process generally adopts boiler tube or reflow stove (reflow) that wafer, grafting material spare and encapsulation base material are carried out for a long time evenly heating simultaneously; Utilize the fusing point that improves temperature to grafting material spare; And then joint wafer and encapsulation base material, to accomplish flip chip assembly process.Yet; The shortcoming of above-mentioned prior art is that heat treatment time is oversize, between wafer and substrate, produces too much accumulation of heat, causes layers of material to produce negative effects such as solder joint dislocation, difference row, residual stress because of thermal coefficient of expansion is different; Make that the electrical quality of product is not good, noise is excessive; And heating and cooling time that boiler tube is required are tediously long, not only increase heat budget and produce required cost, and output also can't significantly promote.In addition; Along with the technological trend of future to high packaging density demand; Like further reduction wafer package size, will certainly be difficult to reach binding purpose more because of the influence of different heat expansion coefficient between different materials, especially; The geometry that hot residual stress produced between wafer and base plate for packaging is asymmetric, will cause in wafer and the encapsulation base material in order to the solder joint of fitting difference row, short circuit take place, sky connects or grafting material spare follow hypodynamic problem.
Therefore; Need a kind of can produce temperature required temperature gradient so that wafer and substrate heat up and the cooling state under; All tool is identical expands with heat and contract with cold deflection and can not take place stress-retained or cause the rapid temperature rise and drop of the crooked deformation of product to cover brilliant method, to solve above-mentioned prior art problems.
Summary of the invention
Main purpose of the present invention is providing a kind of rapid temperature rise and drop to cover crystal method, and said method step comprises: settle the encapsulation base material at least one wafer, at least one grafting material spare and the localization tool; Localization tool is sent in the reaction cavity of rapid temperature rise and drop device; Utilize the heating source of rapid temperature rise and drop device respectively wafer, grafting material spare and encapsulation base material to be heated; Make wafer, grafting material spare and encapsulation base material produce different temperatures difference; Make wafer, grafting material spare and the thermal expansion amount difference of encapsulation base material under heating-up temperature less than default value, wherein grafting material spare can melt under heating-up temperature and in order to the gluing wafer and encapsulate base material; Carry out cooling procedure, make wafer, grafting material spare and encapsulation base material be bonded with each other, cover brilliant processing procedure with completion.
Owing to can form suitable temperature gradient and difference at wafer, grafting material and encapsulation base material; Therefore; Can dwindle the deflection difference between different thermal expansion coefficient material; With solve dislocation, difference row, short circuit possible between wafer and encapsulation base material, sky connects and material is followed hypodynamic problem, further improve wafer and encapsulate the electrical quality between base material.
Description of drawings
Fig. 1 covers the flow chart of crystal method for rapid temperature rise and drop of the present invention.
Fig. 2 covers the sketch map of the localization tool of crystal method for rapid temperature rise and drop of the present invention.
Fig. 3 covers the rapid temperature rise and drop schematic representation of apparatus of crystal method for rapid temperature rise and drop of the present invention.
Fig. 4 A is the temperature time history plot of layers of material under the SOP pattern.
Fig. 4 B is the temperature time history plot of layers of material under the SPIKE pattern.
When heating for prior art, Fig. 5 causes the sketch map of difference row, short circuit because of heat is swollen.
Fig. 6 is prior art sketch map because of contracting in the base material and causing deflection, sky to connect after cooling.
Fig. 7 is a preferred embodiment sketch map of the present invention.
Embodiment
Those skilled in the art below cooperate Figure of description that execution mode of the present invention is done more detailed explanation, so that can implement after studying this specification carefully according to this.
Consult Fig. 1, cover the flow chart of crystal method for rapid temperature rise and drop of the present invention.In addition, consult Fig. 2, cover the sketch map of the localization tool of crystal method for rapid temperature rise and drop of the present invention for clearly demonstrating characteristic of the present invention, please cooperating.
As shown in Figure 1; Rapid temperature rise and drop of the present invention covers crystal method to be begun by step S10; At least one wafer 10, at least one grafting material spare 20 and encapsulation base material 30 are placed in the localization tool 40; Wherein the structure of localization tool 40 is as shown in Figure 2, and localization tool 40 comprises tool base 41, positioning auxiliary device 43 and tool loam cake 45.Encapsulation base material 30 is placed between tool base 41 and the positioning auxiliary device 43 and fixes.Positioning auxiliary device 43 has at least one perforation 44, is used as the location hole 44 of 20 of wafer 10 and grafting material spares, and each location hole 44 is in order to ccontaining corresponding grafting material spare 20.Each wafer 10 is placed on the corresponding grafting material spare 20.Tool loam cake 45 covers wafer 10 and positioning auxiliary device 43.
Be noted that; In Fig. 2, tool loam cake 45 covers the positioning auxiliary device 43 of two wafers 10 and part, just in order to the convenient instance that characteristics of the present invention are described; Be not in order to limit scope of the present invention; Therefore, the present invention can comprise use than the tool loam cake 45 of small size covering single wafer 10, or use larger area tool loam cake 45 to cover two above wafers 10.
Above-mentioned grafting material spare 20 can comprise terne metal, and such as 63% plumbous and 37% tin, or high terne metal, greater than 90%, or lead-free SAC alloy is in order to reduce required process temperatures such as lead tolerance.
Cooperate and consult Fig. 3; Cover the rapid temperature rise and drop schematic representation of apparatus of crystal method for rapid temperature rise and drop of the present invention; To show that rapid temperature rise and drop of the present invention covers the employed rapid temperature rise and drop device 50 of crystal method, wherein rapid temperature rise and drop device 50 comprises reaction cavity 51, carries pusher 52, heating source 53, gas supply source 55 and gathering-device 57.
Then get into step S20; Utilize rapid temperature rise and drop device 50 with the ccontaining localization tool 40 that includes wafer 10, grafting material spare 20 and encapsulation base material 30; That is localization tool 40 is sent in the reaction cavity 51 of rapid temperature rise and drop device 50, and mat carries pusher 52 with the airtight reaction cavity 51 of living.
In step S30; Utilize 53 pairs of localization tools 40 of heating source of rapid temperature rise and drop device 50 to heat; Use heated chip 10, grafting material spare 20 and encapsulation base material 30, so that 20 fusings of grafting material spare and gluing or applying (bonding) wafer 10 and encapsulation base material 30 and be combined into one.
In the present embodiment, grafting material spare 20 is between wafer 10 and encapsulation base material 30.Can be by the direct wafer 10 of the radiant energy that heating source 53 is produced, heating grafting material spare 20; Or use the vibration frictional heat energy that wafer 10 is heated; Then wafer 10 conducts heat to grafting material spare 20 and it is reached open that promptly the beginning cools off behind the liquid phase melting temperature; Therefore; The temperature of wafer 10 is higher than the temperature of grafting material spare 20, and the temperature of grafting material spare 20 is higher than the temperature that encapsulates base material 30, uses the formation temperature gradient.Because heating source 53 tool transient heating effects; Can make wafer 10, grafting material spare 20 and encapsulation base material 30 keep required temperature gradient; And then make 20 moments of grafting material spare reach fusing point; Such as 260 ℃, and fusing and gluing wafer 10 and encapsulation base material 30, and encapsulation base material 30 still keeps relatively low temperature.
Consult Fig. 4 A and Fig. 4 B; Be respectively the temperature time history plot of layers of material under immersion (SOP), spine (SPIKE) pattern; And Fig. 5 and Fig. 6 are consulted in cooperation; Cause the sketch map that differs from row, short circuit because of heat is swollen when wherein Fig. 5 heats for prior art, Fig. 6 is prior art sketch map because of contracting in the base material and causing deflection, sky to connect after cooling.The thermal expansion of general wafer 10 is greater than the thermal expansion of encapsulation base material 30; The heating-up temperature of Fig. 5 is 300 ℃; The temperature of Fig. 6 is for being cooled to 25 ℃ of normal temperature, and element numbers A1 represents wafer size, and element numbers δ A1 represents the wafer distortion amount; Element numbers B2 representative encapsulation base material size, element numbers δ B2 representative encapsulation base material deflection.Therefore utilize above-mentioned temperature gradient; The thermal expansion that can keep wafer 10, reach encapsulation base material 30 is in preset range; Such as 0.1%; Make wafer 10 keep aliging with the relative link position of encapsulation base material 30, avoiding producing dislocation because of thermal coefficient of expansion is different during with 30 heating of encapsulation base material and cooling at wafer 10, difference row, short circuit, sky connects and follow hypodynamic problem.
In step S40, cooling wafer 10, grafting material spare 20 and encapsulation base material 30 are to accomplish mat grafting material spare 20 connecting wafers 10 and the brilliant fabrication process of covering that encapsulates base material 30 at last.
Cooperate and consult Fig. 7; The characteristics that rapid temperature rise and drop of the present invention covers crystal method are, utilize suitable temperature gradient between wafer 10, grafting material spare 20 and the encapsulation base material 30, make each layer expand with heat and contract with cold deflection much at one; To reduce the thermal dilation difference between wafer and the encapsulation base material; Avoid taking place stress-retained or product flexural deformation, thereby wafer can be alignd with the encapsulation base material really and be connected or fit, use the raising yield.
The above is merely in order to explain preferred embodiment of the present invention; Be not that attempt is done any pro forma restriction to the present invention according to this; Therefore, all have in that identical creation spirit is following do relevant any modification of the present invention or change, all must be included in the category that the invention is intended to protect.
Claims (10)
1. a rapid temperature rise and drop covers crystal method; Mat one a location tool and a rapid temperature rise and drop device are to cover brilliant processing procedure; This localization tool comprises a tool base, a positioning auxiliary device and at least one tool loam cake; This rapid temperature rise and drop device comprises that at least a reaction cavity, carries a pusher and a heating source, is characterized in that this rapid temperature rise and drop covers crystal method and may further comprise the steps:
At least one wafer, at least one grafting material spare and an encapsulation base material are placed in this localization tool; Wherein, this encapsulation base material is sandwiched between this tool base and this positioning auxiliary device, and this at least one wafer is positioned on this tool base; This positioning auxiliary device has at least one perforation; In order to ccontaining this at least one grafting material spare, this at least one wafer is placed on this at least one grafting material spare, and this at least one tool loam cake covers this at least one wafer and this positioning auxiliary device;
Utilize this carrying pusher that this localization tool is sent in this reaction cavity, so that should carry pusher to this reaction cavity;
Utilize this this localization tool of heating source heating; Use this at least one wafer of heating, this at least one grafting material spare and this encapsulation base material; So that this at least one wafer, this at least one grafting material spare and this encapsulation base material tool different temperature difference and form a temperature gradient, and this at least one grafting material spare is melted and this at least one wafer of gluing reaches this encapsulation base material to be combined into one; And
Cool off this localization tool, use this at least one wafer of cooling, this at least one grafting material spare and this encapsulation base material, cover brilliant processing procedure with completion.
2. rapid temperature rise and drop as claimed in claim 1 covers crystal method; It is characterized in that; This at least one grafting material spare comprises one of them of terne metal, high terne metal and lead-free SAC alloy or lead-free alloy, and the lead tolerance of this high terne metal is greater than 90%.
3. rapid temperature rise and drop as claimed in claim 1 covers crystal method, it is characterized in that, this heating source comprise infrared ray, Supersonic involve the induction high-frequency one of them.
4. rapid temperature rise and drop as claimed in claim 1 covers crystal method; It is characterized in that; This rapid temperature rise and drop device further comprises a gas supply source and a gathering-device; This gas supply source provides the required gas of this reaction cavity and imports in this reaction cavity, and this gathering-device is in order to collect the gas in this reaction cavity.
5. rapid temperature rise and drop as claimed in claim 1 covers crystal method, it is characterized in that, this grafting material spare also can be bond materials such as tin ball or electroforming metal, in order to the mode of joint wafer and substrate, is all the embodiment of this patent.
6. rapid temperature rise and drop as claimed in claim 4 covers crystal method, it is characterized in that, the required gas of this reaction cavity comprises inert gas or process gas.
7. rapid temperature rise and drop as claimed in claim 1 covers crystal method, it is characterized in that, this reaction cavity makes it meet unlike material response characteristic person for the airtight or open environment of vacuum, normal pressure or malleation can be provided.
8. rapid temperature rise and drop as claimed in claim 1 covers crystal method, it is characterized in that, said process conditions comprises that reaction cavity vacuumizes earlier before processing procedure, and vacuum breaker in processing procedure or behind the processing procedure utilizes atmospheric pressure to increase wafer engaging force person.
9. rapid temperature rise and drop as claimed in claim 1 covers crystal method, it is characterized in that, localization tool can only comprise a tool base, a location is auxiliary puts, and directly utilizes the heating source heated chip, reaches the purpose person that contact engages.
10. rapid temperature rise and drop as claimed in claim 1 covers crystal method, it is characterized in that said process conditions can be selected immersion pattern or spine pattern according to material behavior.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102212088A CN102315134B (en) | 2010-07-08 | 2010-07-08 | Method for flipping chip by quickly raising and reducing temperature |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102212088A CN102315134B (en) | 2010-07-08 | 2010-07-08 | Method for flipping chip by quickly raising and reducing temperature |
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| Publication Number | Publication Date |
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| CN102315134A true CN102315134A (en) | 2012-01-11 |
| CN102315134B CN102315134B (en) | 2013-05-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2010102212088A Active CN102315134B (en) | 2010-07-08 | 2010-07-08 | Method for flipping chip by quickly raising and reducing temperature |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109813752A (en) * | 2019-02-20 | 2019-05-28 | 重庆理工大学 | A kind of method for evaluating reliability of Electronic Packaging microbonding point |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020072149A1 (en) * | 2000-10-04 | 2002-06-13 | Koji Yoshida | Method for manufacturing a semiconductor device |
| US20020109238A1 (en) * | 2002-04-17 | 2002-08-15 | Celerity Research Pte. Ltd. | Pitch compensation in flip-chip packaging |
| CN1913115A (en) * | 2005-08-11 | 2007-02-14 | 三星Techwin株式会社 | Method and apparatus for flip-chip bonding |
| CN101071777A (en) * | 2006-05-11 | 2007-11-14 | 富士通株式会社 | Method of manufacturing a semiconductor device |
| CN201289856Y (en) * | 2008-10-21 | 2009-08-12 | 技鼎股份有限公司 | Equipment for rapidly cooling and heating for preparation of photoelectric semiconductor |
-
2010
- 2010-07-08 CN CN2010102212088A patent/CN102315134B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020072149A1 (en) * | 2000-10-04 | 2002-06-13 | Koji Yoshida | Method for manufacturing a semiconductor device |
| US20020109238A1 (en) * | 2002-04-17 | 2002-08-15 | Celerity Research Pte. Ltd. | Pitch compensation in flip-chip packaging |
| CN1913115A (en) * | 2005-08-11 | 2007-02-14 | 三星Techwin株式会社 | Method and apparatus for flip-chip bonding |
| CN101071777A (en) * | 2006-05-11 | 2007-11-14 | 富士通株式会社 | Method of manufacturing a semiconductor device |
| CN201289856Y (en) * | 2008-10-21 | 2009-08-12 | 技鼎股份有限公司 | Equipment for rapidly cooling and heating for preparation of photoelectric semiconductor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109813752A (en) * | 2019-02-20 | 2019-05-28 | 重庆理工大学 | A kind of method for evaluating reliability of Electronic Packaging microbonding point |
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| CN102315134B (en) | 2013-05-01 |
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Addressee: Liu Jun Document name: Notice of Conformity |