201201294201201294
V 六、發明說明： * 【發明所屬之技術領域】 本發明係有關-髓晶方法’尤其是_定位治具及快速升 降溫系統以達成快速升降溫覆晶的方式。 【先前技術】 在習用技術中’覆晶封裝製程—般雜職管或回焊爐 (reflow)對晶片、接合材料件及封裝基材同時進行長時間的均勻加 熱’利用提高溫度至接合材料件触點，進而接合晶片盘封裝某 材’以完成覆晶封裝製程。然而，上述習用技術的缺财於熱^ • 理時間太長，在晶片與基板間產生過多的熱量累積，導致各声材 料因熱膨脹係數不同而產生娜錯位、差排、殘留應力等負面效 應，使得產品的電性品質不佳’雜訊過大；且爐f所需的加熱與 冷卻時間冗長’不僅增加熱預算與生產·成本，產量亦無法大 幅提升。此外，隨著未來對高封裝密度f求的技術趨勢，如進一 步縮減晶片封裝尺寸，勢必會因不同材料間不同熱雜係數之影 響而更加難以達成結合目的，尤其是，晶片與封裝基板間的熱殘 留應力所產生㈣何獨稱，料致⑼與雜緒中用以進行 # 私轉歸生録、短路、空接或接合狀接著力不足的 問題。 因此，需要-種能產生所需溫度溫差梯度以使晶片與基板在 升/皿與降溫狀_下’皆具相同的熱脹冷縮變形量而不會發生應力 殘留或致使產品f曲形變的快速升降溫覆晶的方法，以解決上述 習用技術的問題。 【發明内容】 本發明之主要目的在提供一種快速升降溫覆晶方法，係包 201201294 括.安置至少一晶片、至少一接合材料件及定位治具中的封裝基 材；將定位治具傳送至快速升降溫裝置的反應腔體中；利用快速 升降溫輕的加熱齡珊“、接合·件及職基材進行加 熱，使彳于晶片、接合材料件及封裝基材產生不同溫度差異，使得 晶片、接合材料件及職基材在加熱溫度下的鱗脹量差異小於 預设值，其巾接合材料件可在加熱溫度下疏朋轉接晶片及 封裝基材；断冷㈣程，使得“、接合材料件無裝紐相 互接合，以完成覆晶製程。V. DESCRIPTION OF THE INVENTION: * TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of - a medullary crystal method, particularly a locating fixture and a rapid rise and lower temperature system for achieving rapid rise and fall temperature flipping. [Prior Art] In the conventional technology, the flip-chip packaging process-like miscellaneous tube or reflow furnace simultaneously performs uniform heating for a long time on the wafer, the bonding material member and the packaging substrate. The contacts, in turn, bond the wafer package to a material to complete the flip chip packaging process. However, the above-mentioned conventional technology lacks the heat for a long time, and excessive heat is generated between the wafer and the substrate, resulting in negative effects such as dislocation, poor displacement, and residual stress due to different thermal expansion coefficients of the acoustic materials. The electrical quality of the product is not good, 'the noise is too large; and the heating and cooling time required for the furnace f is long', which not only increases the thermal budget and production cost, but also increases the output. In addition, with the future trend of high packaging density f, such as further reducing the size of the chip package, it is bound to be more difficult to achieve the purpose of bonding due to the different thermal coefficient between different materials, especially between the wafer and the package substrate. (4) What is the name of the heat residual stress? (4) It is used in (9) and miscellaneous to solve the problem of #私转归录, short circuit, empty connection or insufficient bonding force. Therefore, it is required to produce a temperature gradient of the desired temperature so that the wafer and the substrate have the same thermal expansion and contraction deformation in the lift/dish and the temperature-reducing shape without stress residual or causing the product f to be deformed. A method of rapidly raising and lowering the temperature to cover the above-mentioned conventional techniques. SUMMARY OF THE INVENTION The main object of the present invention is to provide a rapid rise and fall temperature flip chip method, the kit 201201294 includes: arranging at least one wafer, at least one bonding material member, and a packaging substrate in the positioning fixture; and transmitting the positioning fixture to In the reaction chamber of the rapid temperature rise and fall device; using the rapid heating and cooling of the light age, the joints and the substrate are heated to make different temperature differences between the wafer, the bonding material and the package substrate, so that the wafer The difference in the amount of swell of the joining material member and the working substrate at the heating temperature is less than a preset value, and the material of the towel joining material can be used to transfer the wafer and the packaging substrate at a heating temperature; the cold (four) process makes ", The joining material pieces are joined to each other without a button to complete the flip chip process.
由於可在晶>1、接合材料及雜基材職適#的溫度梯度與 差異，因此’可縮小不同鋪脹係數材·之變形量差異，以解 決晶片與封錄材間可能的錯位、絲、 力不足的問題，™j細細的電㈣ 【實施方式】 以下配合圖式及元件舰縣發明之實财式做更詳細和 明’俾使熟習該項技藝者在研讀本觸雜能據以實施。 參閱第i，本發·速升降溫覆晶方法的流程圖。此外 本發_特徵，請配合參㈣二圖，本發明快速剌 /皿覆日日方法的定位治具之示意圖。 如第-_示，本發_快速升降溫覆晶方法制步驟si( :二將至少U 1G、至少—接合材料件2q及规基材㈣ ;疋位治具4〇中，其中定位治具4〇的結構 姑編、糊购似治具上蓋仏 定H〇係安置於治具底座41與定位輔助裳置43之間而固 疋。疋_«置43具枝少—訊 料件20間的定位孔44_ ”作^ 10與接合材 母個疋位孔44係用以容置相對應的接合 201201294 材料件20。每個晶片ι〇安置於相對應的接合材料件2〇上。治具 上盡45覆盖住晶片10及定位輔助裝置43。 要注意的是，在第二圖中，治具上蓋45覆蓋住二個晶片1〇 及部分的定_助裝置43，只是用財便制本發3麟點的實例 而已，並非用以限定本發明的範圍，因此，本發明可包括使用較 小面積的治具上盍45以覆蓋住單一晶片〗〇,或使用較大面積的治 具上蓋45以覆蓋住二個以上晶片10。 上述的接合材料件20可包括鉛錫合金，比如63%鉛與37〇/〇Because of the temperature gradients and differences in the crystals, the bonding materials, and the miscellaneous materials, the difference in the amount of deformation of the different spreading factors can be reduced to solve the possible misalignment between the wafer and the sealing material. The problem of insufficient wire and force, TMj's fine electricity (4) [Embodiment] The following is a more detailed and clear description of the real and financial styles of the invention and the ship's inventions, so that those skilled in the art can study the touch energy. According to the implementation. Refer to the i, the flow chart of the method of the present invention. In addition, the hair _ feature, please cooperate with the reference (4) and the second figure, the schematic diagram of the positioning fixture of the present invention. As shown in the first -_, the present invention _ rapid lifting temperature flip chip method steps si (: two will at least U 1G, at least - joint material 2q and gauge substrate (four); clamp fixture 4 ,, which positioning fixture The structure of the 4 〇 姑 、 糊 糊 糊 糊 糊 糊 糊 糊 糊 糊 糊 治 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 安置 « 安置 安置 « « « « « « The positioning hole 44_" is used as a member to receive the corresponding bonding material 201201294. Each wafer is placed on the corresponding bonding material member 2's. The wafer 10 and the positioning aid 43 are covered by the upper portion 45. It should be noted that in the second figure, the upper cover 45 of the fixture covers the two wafers 1 and a portion of the fixing device 43. The invention is not intended to limit the scope of the present invention. Therefore, the present invention may include the use of a smaller area of the upper surface of the jig 45 to cover a single wafer, or the use of a larger area of the upper cover. 45 to cover more than two wafers 10. The bonding material member 20 described above may include a tin-lead alloy such as 63% lead and 37 〇/〇.
錫’或高船錫合金，比如含船量大於9〇%，或不含錯的錫銀銅合 金’用以降低所需製程溫度。 配令、芩閲第 马，伏迷开降溫覆晶方法的快速升降溫 裝置之示意圖，示本發縣速升降溫覆晶方法所制的快速 升降溫裝置50，其中快速升降溫裝置5〇係包括反應腔體m、承 載推送裝Ϊ 52、加絲53、氣體供絲％及收集裝置57。 反應腔體51為用以容置定位治具4〇的空腔，且承載推送裝 置52係用以推送定位治具4〇並密閉住反應腔體$卜加熱源幻具 有快速瞬間加熱作用，可包括紅外線或超音波或絲電㈣變頻 波由氣體供應源55提供反應腔體M所需的氣體並導入反應腔體 51 ’比如惰性氣體，而收集裝置57铜以收航應腔體Μ中 的軋體。 接著進人步驟S2G，利職速鱗溫裝置加容置包含有盖 呈40^合材料件2〇及封裝基材3〇的定位治具40，亦即定位％ ::梦罢削运至快速升降溫裳置5G的反應腔體51中，並藉承載啦 运裝置52崎絲腔體5卜 治具4〇=S3G巾’ 快速升降溫裝置％的加熱源53對定相 〜彳了加熱’藉以加熱晶)WG、接合材料件2()及封裝基柄 201201294 30’以使接合材料件20熔化並黏接或貼合(b〇nding)晶片1〇及封裝 基材30而結合成一體。 在本實施例中，接合材料件2〇位於晶片10與封裝基材3〇之 間。可藉由加熱源53所產生之輻射能直接穿透晶片10，加熱接合 材料件20 ;或使用振動摩擦熱能對晶片1〇進行加熱，接著晶片 1 〇將熱傳導至接合材料件20使其達到液相熔點溫度後開即始進行 冷卻’因此’晶片10的溫度高於接合材料件2〇的溫度，而接合 材料件20的溫度又高於封裝基材3〇的溫度，藉以形成溫度梯度。 由於加熱源53具瞬間加熱作用，可使得晶片丨〇、接合材料件2〇 及封裝基材30維持所需的溫度梯度，進而使接合材料件2〇瞬間 達到熔點，比如260°C，並熔化而黏接晶片丨〇及封裝基材3〇 ,而 且封裝基材30仍保持相對較低溫。 參閱第四A圖及第四b圖，分別為浸泡(s〇p) '尖刺(SPIKE) 模式下各層材料之溫度隨時間變化的曲線圖，並配合參閱第五圖 及第六圖，其中第五圖為習知技術加熱時因熱膨造成差排、短路 的示意圖，第六圖為習知技術在冷卻後因基材内縮導致撓曲、空 接的示意圖。一般晶片10的熱膨脹係大於封裝基材3〇的熱膨脹， 第五圖的加熱溫度為3〇〇。〇，第六圖的溫度為冷卻至25°c常溫， 且元件符號A1代表晶片大小，元件符號δΑ1代表晶片變形量，元 件符號Β2代表封裝基材大小，元件符號δΒ2代表封裝基材變形 量。因此利用上述的溫度梯度，可保持晶片1〇、及封裝基材3〇的 熱膨脹在預設範圍内，比如〇.1%，使得晶片1〇與封裝基材3〇的 相對連接位置保持對齊，以避免因熱膨脹係數不同而在晶片1〇與 封裝基材30加熱及冷卻時產生錯位，差排、短路'空接與接著力 不足的問題。 最後在步驟S40中，冷卻晶片1〇、接合材料件2〇及封裝基 201201294 材30，以完成藉接合材料件2〇連接晶片1〇與封裝基材％的覆晶 製程處理。 配合參閱第七®，本發縣速升降溫覆晶方法的特點在於， 利用晶片1G、接讀料件2〇及封裝騎3()之㈣當的溫度梯度， 使各層.熱脹冷縮變形量幾乎相同，以降低晶片及封裝基材之間的 熱膨脹差異，避免發生應力殘留或產品料變形，因而使晶片與 封裝基材能確實對齊而連接或貼合，藉以提高良率。 以上所述者僅為用以解釋本發明之較佳實施例，並非企圖據以對 本發明做任何形式上之關，是以，凡有在_之個精神下所作有 關本發明之任何修飾或變更，皆減包括在本發日㈣圖倾之範嘴。 【圖式簡單說明】 第一圖為本發明快速升降溫覆晶方法的流程圖。 第二圖為本發明快速升降溫覆晶方法的定位治具之示意圖。 第三圖為本發明快速升降溫覆晶方法的快速升降溫裝置之示意 圖。 第四A圖為s〇p模式下各層材料之溫度隨時間變化的曲線圖。 第四B圖為SPIKE模式下各層材料之溫度隨時間變化的曲線圖。 第五圖為習知技術加熱時因熱膨造成差排、短路的示意圖。 第六圖為習知技術在冷卻後因基材内縮導致撓曲、空接的示意圖。 第七圖為本發明之較佳實施例示意圖。 【主要元件符號說明】 S10步驟 S20步驟 S30步驟 S40步驟 7 201201294 ίο晶片 20接合材料件 30封裝基材 40定位治具 41治具底座 43定位輔助裝置 44定位孔(穿孔） 45治具上蓋 50快速升降溫裝置 51反應腔體 53加熱源 55氣體供應源 57收集裝置 A1晶片大小 δΑΙ晶片變形量 Β2封裝基材大小 δΒ2封裝基材變形量Tin' or high ship tin alloys, such as tin-silver-copper alloys containing more than 9% by volume or without errors, are used to reduce the required process temperature. Schematic diagram of the rapid lifting and lowering device with the order, the reading of the horse, the ventilating and cooling method, and the rapid lifting and lowering device 50 made by the method of the rapid rise and fall of the county, the rapid lifting and lowering device 5 The reaction chamber m, the carrying push device 52, the wire 53, the gas supply wire %, and the collecting device 57 are included. The reaction chamber 51 is a cavity for accommodating the positioning fixture 4, and the carrying push device 52 is used for pushing the positioning fixture 4〇 and sealing the reaction chamber. The heating source has a rapid instant heating effect. Including infrared or ultrasonic or silk (four) frequency conversion wave is supplied by gas supply source 55 to the reaction chamber body 51 and introduced into the reaction chamber 51 'such as inert gas, and the collection device 57 copper to hang in the chamber Rolling body. Then, the step S2G is entered, and the positioning fixture 40 containing the cover material 40〇 and the package substrate 3〇 is arranged, which means that the positioning % :: dream is cut to fast Lifting and warming is placed in the reaction chamber 51 of 5G, and by the carrying device 52, the silk chamber 5, the fixture, 4 〇 = S3G towel, the rapid heating device, the heating source 53, the phasing, the heating, The crystal WG, the bonding material member 2 (), and the package base member 201201294 30' are used to fuse the bonding material member 20 to melt and bond or bond the wafer 1 and the package substrate 30. In the present embodiment, the bonding material member 2 is located between the wafer 10 and the package substrate 3A. The radiant energy generated by the heat source 53 can directly penetrate the wafer 10, heat the bonding material member 20; or heat the wafer 1 using vibrational friction heat, and then the wafer 1 〇 conducts heat to the bonding material member 20 to reach the liquid The temperature of the wafer 10 is cooled immediately after the melting point of the phase, so that the temperature of the wafer 10 is higher than the temperature of the bonding material member 2, and the temperature of the bonding material member 20 is higher than the temperature of the package substrate 3, thereby forming a temperature gradient. Since the heating source 53 has an instantaneous heating effect, the wafer crucible, the bonding material member 2, and the encapsulating substrate 30 can be maintained at a desired temperature gradient, so that the bonding material member 2 〇 instantaneously reaches a melting point, such as 260 ° C, and is melted. The wafer and the package substrate are bonded, and the package substrate 30 remains relatively low temperature. Refer to the fourth and fourth b-graphs, respectively, for the immersion (s〇p) 'spike (SPIKE) mode, the temperature of each layer of the material as a function of time, and with reference to the fifth and sixth figures, The fifth figure is a schematic diagram of the differential arrangement and short circuit caused by thermal expansion during heating by the prior art. The sixth figure is a schematic diagram of the deflection and empty connection caused by the shrinkage of the substrate after cooling. Generally, the thermal expansion of the wafer 10 is greater than the thermal expansion of the package substrate 3, and the heating temperature of the fifth diagram is 3 Torr. 〇, the temperature of the sixth graph is cooled to 25 ° C normal temperature, and the symbol A1 represents the wafer size, the component symbol δ Α 1 represents the wafer deformation amount, the component symbol Β 2 represents the package substrate size, and the component symbol δ Β 2 represents the package substrate deformation amount. Therefore, by using the above temperature gradient, the thermal expansion of the wafer 1 and the package substrate 3〇 can be maintained within a preset range, such as 〇.1%, so that the relative positions of the wafer 1〇 and the package substrate 3〇 are kept aligned. In order to avoid misalignment when the wafer 1 and the package substrate 30 are heated and cooled due to the difference in thermal expansion coefficient, there is a problem that the gap and the short circuit are insufficiently connected and insufficient. Finally, in step S40, the wafer 1 , the bonding material 2 and the package substrate 201201294 are cooled to complete the flip chip process of joining the wafer 1 and the package substrate by the bonding material 2 . In conjunction with the seventh edition, the method of the speed rise and fall flip chip of the county is characterized by using the temperature gradient of the wafer 1G, the reading material 2〇 and the package riding 3() to make the layers expand and contract. The amount is almost the same to reduce the difference in thermal expansion between the wafer and the package substrate, to avoid stress residual or deformation of the product material, thereby enabling the wafer and the package substrate to be properly aligned and connected or bonded, thereby improving the yield. The above is only a preferred embodiment for explaining the present invention, and is not intended to be in any form to modify the present invention. Any modification or alteration of the present invention made in the spirit of the present invention. , all are included in the mouth of this day (four). BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a flow chart of the method for rapid rise and fall of the invention. The second figure is a schematic view of the positioning fixture of the fast rising and falling temperature flip chip method of the present invention. The third figure is a schematic view of the rapid temperature rise and fall device of the rapid rise and fall temperature flip chip method of the present invention. The fourth A graph is a graph of the temperature of each layer of material in s〇p mode as a function of time. Figure 4B is a graph of temperature versus time for each layer of material in SPIKE mode. The fifth figure is a schematic diagram of the differential arrangement and short circuit caused by thermal expansion during heating by the prior art. The sixth figure is a schematic diagram of the prior art, which is deflected and vacant due to shrinkage of the substrate after cooling. Figure 7 is a schematic view of a preferred embodiment of the present invention. [Main component symbol description] S10 Step S20 Step S30 Step S40 Step 7 201201294 ί0 wafer 20 bonding material member 30 package substrate 40 positioning jig 41 jig base 43 positioning auxiliary device 44 positioning hole (perforation) 45 jig upper cover 50 fast Temperature rise and fall device 51 reaction chamber 53 heat source 55 gas supply source 57 collection device A1 wafer size δ ΑΙ wafer deformation Β 2 package substrate size δ Β 2 package substrate deformation