CN109192672A - A kind of sintering method of silicon chip - Google Patents
A kind of sintering method of silicon chip Download PDFInfo
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- CN109192672A CN109192672A CN201811030374.2A CN201811030374A CN109192672A CN 109192672 A CN109192672 A CN 109192672A CN 201811030374 A CN201811030374 A CN 201811030374A CN 109192672 A CN109192672 A CN 109192672A
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- silicon chip
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- weld tabs
- auri
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L21/607—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving the application of mechanical vibrations, e.g. ultrasonic vibrations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
- H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
- H01L2021/60015—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using plate connectors, e.g. layer, film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
Abstract
This application provides a kind of sintering methods of silicon chip, the back side of silicon chip be silicon based substrates directly as former state it is exposed and without deposit back metal electrode in the case where, combining closely for silicon chip and the gold silicon eutectic of the contact surface of auri weld tabs is realized using sintering temperature and low and ultrasonic activation, and make auri weld tabs that fusing occur simultaneously and realize welded connecting with metallic conduction piece, the silicon chip of no back metal electrode is bound tightly together with metallic conduction piece by auri weld tabs to realize；And the application is easy to operate, high production efficiency, good reliability, suitable for the sintering of various shells, small area chip, realizes the safe and reliable and efficient of production.
Description
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly, to a kind of sintering method of silicon chip.
Background technique
For power device, good Mechanical Contact between chip and package casing is thermally contacted and is in electrical contact and is
Guarantee the premise that power device works normally.Poor contact can be such that device thermal resistance increases, and heat dissipation is uneven, influence electric current in device
In distribution, destroy the thermal stability and long-term reliability of device, or even burn device.
Eutectic sintering process has that high mechanical strength, thermal resistance is small, stability is good, high reliability, thus in power device
It is widely used in the chip package of part.
For a long time, for the sintering of low-power device and monolithic integrated circuit, the country adopts always traditional pipeline nitrogen hydrogen and burns
The sintering processing of knot, such sintering processing are harsher to raw material and process conditions requirement, while the operation to operator
Skill requirement is very high, causes production efficiency and finished product rate lower.
With the needs that product batch produces, finds and a kind of be more convenient efficient, simple and practical chip sintering method and become
The problem of those skilled in the art's urgent need to resolve.
Summary of the invention
The purpose of the present invention is to provide a kind of sintering methods of silicon chip.
In order to solve the above technical problems, technical solution provided by the invention are as follows:
A kind of sintering method of silicon chip, comprising the following steps:
1) when heating platform is in constant temperature, by be used for encapsulate shell be placed in the heating platform full of protective gas into
Row preheating and constant temperature heat preservation, sintering temperature control between 360 DEG C~380 DEG C；
2) the metallic conduction on piece being placed into auri weld tabs in shell；
3) silicon chip is placed on the auri weld tabs, the back side of the silicon chip is that silicon based substrates are directly exposed as former state
And without back metal electrode；
4) ultrasonic bonding: the soldering tip in ultrasonic brazing unit is pressed on the upper surface of the silicon chip makes the gold
Base weld tabs melts, and the gold element in element silicon and the auri weld tabs in the silicon based substrates is by diffuseing to form gold silicon eutectic
Body removes ultrasonic brazing unit to realize combining closely for the silicon chip and metallic conduction piece after the completion；
5) product after the completion of step 4) ultrasonic bonding is removed from the heating platform, it is then former by ladder cooling
It is then cooled to room temperature, so far sintering process is completed.
Preferably, in step 1), the protective gas is the mixed gas of nitrogen and hydrogen, wherein N2Gas flow is
13L/min~17L/min, H2Gas flow is 300mL/min~450mL/min.
Preferably, in step 2), the auri weld tabs is golden antimony alloy weld tabs or golden gallium alloy weld tabs, with a thickness of 30 μm~
40 μm, the element composition and its mass percent content of the gold antimony alloy weld tabs are Au99.97%Sb0.03%, the gold gallium
The element of alloy weld tabs forms and its mass percent content is Au99.97%Ga0.03%.
Preferably, in step 2), the metallic conduction piece is molybdenum sheet.
Preferably, one layer of gold is coated in step 3), on the exposed surface of the silicon based substrates at the back side of the silicon chip in advance.
Preferably, in step 4), ultrasonic electric current is the 10 μ A of μ A~30, and ultrasonic time is 8s~20s, and ultrasonic pressure is
300mN~350mN.
This application provides a kind of sintering methods of silicon chip, are that silicon based substrates are directly exposed as former state at the back side of silicon chip
And without making the silicon in silicon based substrates first using sintering temperature and low and ultrasonic activation in the case where depositing back metal electrode
The plain gold element with the auri weld tabs realizes the silicon chip and metallic conduction by diffuseing to form gold silicon eutectic body
Piece is combined closely；
The present invention is mainly suitable for gold silicon eutectic sintering, utilize 363 DEG C (2.85% of eutectic point temperature of gold silicon eutectic body
Si), the sintering temperature of selection should be slightly less than this temperature, and in view of heat is lossy in transmittance process, thus
Sintering temperature selection, which applies certain ultrasonic activation at 360 DEG C~380 DEG C, and when sintering, in real work makes silicon chip and gold
The contact surface of base weld tabs reaches gold-silicon eutectic point, and silicon atom is just diffused into gold, reaches the composition of gold silicon eutectic body and beginning
Fusing, subsequent auri weld tabs start to melt, and the liquid phase forward position of subsequent gold silicon eutectic body enters real in the auri weld tabs after fusing
Existing silicon chip is combined closely with the gold silicon eutectic of the contact surface of auri weld tabs, and auri weld tabs is in sintering temperature and low and ultrasonic wave
The lower generation fusing of vibration is realized with metallic conduction piece to be welded to connect, so that back metal electricity will not had by auri weld tabs by realizing
The silicon chip of pole is bound tightly together with metallic conduction piece；
The back side of silicon chip is that silicon based substrates are directly exposed as former state, the application is in this feelings without depositing back metal electrode
The sintering that silicon chip is directly carried out under condition had both avoided back metal electrode to element silicon in low-temperature sintering and ultrasonic bonding
The obstruction spread to auri weld tabs, directly exposed directly contact with auri weld tabs of silicon based substrates are conducive to element silicon to external diffusion and gold
Element forms gold silicon eutectic body, and eliminates the processing and fabricating of back metal electrode, simplifies the production technology of silicon chip, reduces
The cost of manufacture of silicon chip；
And ultrasonic activation is conducive to drive the bubble in fusing solder out of, improves welding rate, reduces thermal resistance；
And the application is easy to operate, high production efficiency, good reliability, suitable for the sintering of various shells, small area chip,
Realize the safe and reliable and efficient of production.
Detailed description of the invention
Fig. 1 is a kind of operation principle schematic diagram of the sintering method of silicon chip provided in an embodiment of the present invention.
In figure: 1 metallic conduction piece, 2 auri weld tabs, 3 silicon chips, 4 soldering tips.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
Member's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that, term " center ", " axial direction ", " radial direction ", " longitudinal direction ", " transverse direction ",
" length ", " width ", "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outside", " clockwise ", " inverse
The orientation or positional relationship of the instructions such as hour hands ", "vertical", "horizontal" is to be based on the orientation or positional relationship shown in the drawings, and is only
For the convenience of describing the present invention and simplifying the description, rather than the device or element of indication or suggestion meaning must have specific side
Position is constructed and operated in a specific orientation, therefore is not considered as limiting the invention.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature "upper" or "lower",
It may include that the first and second features directly contact, also may include that the first and second features are not direct contacts but pass through it
Between other characterisation contact.Moreover, fisrt feature includes the first spy above the second feature " above ", " above " and " above "
Sign is in the surface and oblique upper of second feature, or is merely representative of first feature horizontal height higher than second feature.First is special
Sign includes fisrt feature in the underface and obliquely downward of second feature under the second feature " below ", " below " and " below ", or only
Only indicate that first feature horizontal height is less than second feature.
Referring to Fig.1, Fig. 1 is a kind of operation principle schematic diagram of the sintering method of silicon chip provided in an embodiment of the present invention.
This application provides a kind of sintering methods of silicon chip, comprising the following steps:
1) when heating platform is in constant temperature, by be used for encapsulate shell be placed in the heating platform full of protective gas into
Row preheating and constant temperature heat preservation, sintering temperature control between 360 DEG C~380 DEG C；
2) auri weld tabs 2 is placed on the metallic conduction piece 1 in shell；
3) silicon chip 3 is placed on the auri weld tabs 2, the back side of the silicon chip 3 is the direct original sample of silicon based substrates
It is exposed and without back metal electrode；
4) ultrasonic bonding: the soldering tip 4 in ultrasonic brazing unit is pressed on the upper surface of the silicon chip 3 described in making
Auri weld tabs 2 melts, and the gold element in element silicon and the auri weld tabs 2 in the silicon based substrates is by diffuseing to form gold silicon
Eutectic removes ultrasonic brazing unit to realize combining closely for the silicon chip 3 and metallic conduction piece 1 after the completion；
5) product after the completion of step 4) ultrasonic bonding is removed from the heating platform, it is then former by ladder cooling
It is then cooled to room temperature, so far sintering process is completed.
In one embodiment of the invention, silicon aoxidizes during heating in order to prevent, and sintering is often (few in nitrogen
The hydrogen of amount) protection in carry out, thus in step 1), the protective gas is the mixed gas of nitrogen and hydrogen, wherein N2
Gas flow is 13L/min~17L/min, H2Gas flow is 300mL/min~450mL/min.
In one embodiment of the invention, in step 2), the auri weld tabs is golden antimony alloy weld tabs or golden gallium alloy
Weld tabs, with a thickness of 30 μm~40 μm, the element composition and its mass percent content of the gold antimony alloy weld tabs are Au99.97%
Sb0.03%, the element composition and its mass percent content of the gold gallium alloy weld tabs are Au99.97%Ga0.03%.
In one embodiment of the invention, in step 2), the metallic conduction piece 1 is molybdenum sheet.
In one embodiment of the invention, there is oxide layer since the original sample exposed backside of silicon chip 3 is easy to generate, can hinder
Hinder the formation of gold silicon eutectic body, in order to prevent the interference of oxide layer, in step 3), the siliceous lining at the back side of the silicon chip 3
One layer of gold is coated on the exposed surface at bottom in advance.
In one embodiment of the invention, in step 4), ultrasonic electric current be the 10 μ A of μ A~30, ultrasonic time be 8s~
20s, ultrasonic pressure are 300mN~350mN.
This application provides a kind of sintering methods of silicon chip, are that silicon based substrates are directly outer as former state at the back side of silicon chip 3
Reveal and without making the silicon in silicon based substrates using sintering temperature and low and ultrasonic activation in the case where depositing back metal electrode
Gold element in element and the auri weld tabs 2 realizes the silicon chip 3 and metal by diffuseing to form gold silicon eutectic body
Conductive sheet 1 is combined closely；
The present invention is mainly suitable for gold silicon eutectic sintering, utilize 363 DEG C (2.85% of eutectic point temperature of gold silicon eutectic body
Si), the sintering temperature of selection should be slightly less than this temperature, and in view of heat is lossy in transmittance process, thus
In real work sintering temperature selection at 360 DEG C~380 DEG C, and be sintered when apply certain ultrasonic activation make silicon chip 3 with
The contact surface of auri weld tabs 2 reaches gold-silicon eutectic point, and silicon atom is just diffused into gold, reaches the composition of gold silicon eutectic body and opens
Begin to melt, subsequent auri weld tabs 2 starts to melt, and the liquid phase forward position of subsequent gold silicon eutectic body enters the auri weld tabs 2 after fusing
Middle realization silicon chip 3 is combined closely with the gold silicon eutectic of the contact surface of auri weld tabs 2, and auri weld tabs 2 is in sintering temperature and low
Welded connecting is realized with metallic conduction piece 1 with fusing occurs under ultrasonic activation, so that realizing will not have by auri weld tabs 2
The silicon chip 3 of back metal electrode is bound tightly together with metallic conduction piece 1；
The back side of silicon chip 3 is that silicon based substrates are directly exposed as former state, the application is in this feelings without depositing back metal electrode
The sintering that silicon chip 3 is directly carried out under condition had both avoided back metal electrode to element silicon in low-temperature sintering and ultrasonic bonding
The middle obstruction spread to auri weld tabs 2, directly exposed directly contact with auri weld tabs 2 of silicon based substrates are conducive to element silicon to external diffusion
Gold silicon eutectic body is formed with gold element, and eliminates the processing and fabricating of back metal electrode, simplifies the production work of silicon chip 3
Skill reduces the cost of manufacture of silicon chip 3；
And ultrasonic activation is conducive to drive the bubble in fusing solder out of, improves welding rate, reduces thermal resistance；
And the application is easy to operate, high production efficiency, good reliability, suitable for the sintering of various shells, small area chip,
Realize the safe and reliable and efficient of production.
For a further understanding of the present invention, below with reference to embodiment to a kind of sintering method of silicon chip provided by the invention
It is described in detail, protection scope of the present invention is not limited by the following examples.
Embodiment 1
A kind of sintering method of silicon chip, comprising the following steps:
1) when heating platform is in constant temperature, by be used for encapsulate shell be placed in the heating platform full of protective gas into
Row preheating and constant temperature heat preservation, sintering temperature control between 360 DEG C~380 DEG C；
In step 1), the protective gas is the mixed gas of nitrogen and hydrogen, wherein N2Gas flow is 15L/min, H2
Gas flow is 400mL/min；
2) auri weld tabs 2 is placed on the metallic conduction piece 1 in shell；
In step 2), the auri weld tabs is golden antimony alloy weld tabs, with a thickness of 35 μm, the element of the gold antimony alloy weld tabs
Composition and its mass percent content are Au99.97%Sb0.03%；
In step 2), the metallic conduction piece 1 is molybdenum sheet；
3) silicon chip 3 is placed on the auri weld tabs 2, the back side of the silicon chip 3 is the direct original sample of silicon based substrates
It is exposed and without back metal electrode；
In step 3), one layer of gold is coated on the exposed surface of the silicon based substrates at the back side of the silicon chip 3 in advance；
4) ultrasonic bonding: the soldering tip 4 in ultrasonic brazing unit is pressed on the upper surface of the silicon chip 3 described in making
Auri weld tabs 2 melts, and the gold element in element silicon and the auri weld tabs 2 in the silicon based substrates is by diffuseing to form gold silicon
Eutectic removes ultrasonic brazing unit to realize combining closely for the silicon chip 3 and metallic conduction piece 1 after the completion；
In step 4), ultrasonic electric current be the 10 μ A of μ A~30, ultrasonic time be 8s~20s, ultrasonic pressure be 300mN~
350mN；
5) product after the completion of step 4) ultrasonic bonding is removed from the heating platform, it is then former by ladder cooling
It is then cooled to room temperature, so far sintering process is completed.
The method and apparatus of the not detailed description of the present invention are the prior art, are repeated no more.
Principle and implementation of the present invention are described for specific embodiment used herein, above embodiments
Illustrate to be merely used to help understand method and its core concept of the invention.It should be pointed out that for the common skill of the art
, without departing from the principle of the present invention, can be with several improvements and modifications are made to the present invention for art personnel, these change
It is also fallen within the protection scope of the claims of the present invention into modification.
Claims (6)
1. a kind of sintering method of silicon chip, which comprises the following steps:
1) when heating platform is in constant temperature, the shell for being used to encapsulate is placed in the heating platform full of protective gas and is carried out in advance
Heat and constant temperature heat preservation, sintering temperature control between 360 DEG C~380 DEG C；
2) the metallic conduction on piece being placed into auri weld tabs in shell；
3) silicon chip is placed on the auri weld tabs, the back side of the silicon chip is the silicon based substrates directly exposed and nothing of original sample
Back metal electrode；
4) ultrasonic bonding: the soldering tip in ultrasonic brazing unit is pressed on the upper surface of the silicon chip welds the auri
Piece fusing, the gold element in element silicon and the auri weld tabs in the silicon based substrates by diffuse to form gold silicon eutectic body from
And realize combining closely for the silicon chip and metallic conduction piece, ultrasonic brazing unit is removed after the completion；
5) product after the completion of step 4) ultrasonic bonding is removed from the heating platform, then by ladder cooling principle drop
It warms to room temperature, so far sintering process is completed.
2. the sintering method of silicon chip according to claim 1, which is characterized in that in step 1), the protective gas is
The mixed gas of nitrogen and hydrogen, wherein N2Gas flow is 13L/min~17L/min, H2Gas flow be 300mL/min~
450mL/min。
3. the sintering method of silicon chip according to claim 1, which is characterized in that in step 2), the auri weld tabs is
Golden antimony alloy weld tabs or golden gallium alloy weld tabs, with a thickness of 30 μm~40 μm, the element composition and its matter of the gold antimony alloy weld tabs
Amount relative content is Au99.97%Sb0.03%, the element composition and its mass percent content of the gold gallium alloy weld tabs
For Au99.97%Ga0.03%.
4. the sintering method of silicon chip according to claim 1, which is characterized in that in step 2), the metallic conduction piece
For molybdenum sheet.
5. the sintering method of silicon chip according to claim 1, which is characterized in that in step 3), the back of the silicon chip
One layer of gold is coated on the exposed surface of the silicon based substrates in face in advance.
6. the sintering method of silicon chip according to claim 1, which is characterized in that in step 4), ultrasonic electric current is 10 μ A
~30 μ A, ultrasonic time are 8s~20s, and ultrasonic pressure is 300mN~350mN.
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| CN201811030374.2A CN109192672A (en) | 2018-09-05 | 2018-09-05 | A kind of sintering method of silicon chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811030374.2A CN109192672A (en) | 2018-09-05 | 2018-09-05 | A kind of sintering method of silicon chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114054928A (en) * | 2021-12-23 | 2022-02-18 | 亚洲硅业(青海)股份有限公司 | Silicon core welding device and silicon core welding method |
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|---|---|---|---|---|
| JPH0778896A (en) * | 1993-07-12 | 1995-03-20 | Sumitomo Electric Ind Ltd | Hermetic sealing of semiconductor module |
| CN102601477A (en) * | 2012-02-29 | 2012-07-25 | 深圳市因沃客科技有限公司 | Microwelding eutectic method for LED chips |
| CN105977173A (en) * | 2016-05-20 | 2016-09-28 | 北京华航无线电测量研究所 | High-penetration-rate semiconductor bare chip manual eutectic welding method |
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2018
- 2018-09-05 CN CN201811030374.2A patent/CN109192672A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0778896A (en) * | 1993-07-12 | 1995-03-20 | Sumitomo Electric Ind Ltd | Hermetic sealing of semiconductor module |
| CN102601477A (en) * | 2012-02-29 | 2012-07-25 | 深圳市因沃客科技有限公司 | Microwelding eutectic method for LED chips |
| CN105977173A (en) * | 2016-05-20 | 2016-09-28 | 北京华航无线电测量研究所 | High-penetration-rate semiconductor bare chip manual eutectic welding method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114054928A (en) * | 2021-12-23 | 2022-02-18 | 亚洲硅业(青海)股份有限公司 | Silicon core welding device and silicon core welding method |
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Application publication date: 20190111 |