CN104716059B - A kind of chip-stacked use intermetallic compound bonding method of three-dimension packaging and bonding structure - Google Patents
A kind of chip-stacked use intermetallic compound bonding method of three-dimension packaging and bonding structure Download PDFInfo
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- CN104716059B CN104716059B CN201510069934.5A CN201510069934A CN104716059B CN 104716059 B CN104716059 B CN 104716059B CN 201510069934 A CN201510069934 A CN 201510069934A CN 104716059 B CN104716059 B CN 104716059B
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Abstract
The invention discloses a kind of chip-stacked use intermetallic compound bonding method of three-dimension packaging and structure, methods described includes heating the metal salient point of solder and solder both sides reacts to form the process of intermetallic compound to carry out soldering, during the heating, thermograde is formed between the metal salient point of the solder both sides.The three-dimension packaging that is prepared using methods described is chip-stacked to use intermetallic compound bonding structure, and the metal salient point is monocrystalline or during with preferred orientation, and the intermetallic compound of the formation has single-orientated along thermograde direction.Introducing thermograde during present invention bonding promotes metallic atom to occur thermophoresis, accelerates formation, the growth of compound between interface metal, significantly improves bonding efficiency；Intermetallic compound is continuously grown from the relatively low cold end of temperature to the of a relatively high hot junction of temperature, can be prevented effectively from the metallic compound to be formed and hole occurs.
Description
Technical field
The invention belongs to Electronic Packaging three-dimensional integration technology field, be related to a kind of chip-stacked bonding method of three-dimension packaging and
Structure, more particularly to a kind of chip-stacked use intermetallic compound bonding method of three-dimension packaging and structure.
Background technology
As electronic encapsulation device constantly pursues high-frequency high-speed, multi-functional, high-performance and small size, it is desirable to Electronic Packaging skill
Art can realize higher integration density and smaller package dimension, and encapsulating structure is gradually developed from two dimension to three-dimensional.It is many
Layer stacked chips bonding is one of core technology in three-dimensional electronics package.Using silicon hole (Through Silicon Via,
TSV) technique and micro convex point (μ-bump) technique, it is possible to achieve the three-dimensional interconnection between chip or between chip and substrate, make up
The limitation of conventional semiconductor chip two dimension wiring.There is this interconnection mode three-dimensional to stack that density is big, profile after encapsulation
The advantages of size is small, circuit reliability is high, improves the speed of service of chip and reduces power consumption, realize a system or some function
It is integrated in three-dimensional structure.
Being presently used for the chip-stacked bonding techniques of three-dimension packaging mainly includes：By wafer in Direct Bonding, vacuum environment
Contact float, under a certain pressure high annealing completion；Adhesive bond, is bonded using polymer viscose；Metal diffusion bond
Close, the prefabricated metal salient point in wafer, certain pressure is annealed with a temperature of；Solder bump is bonded, on the basis of metal salient point
Prefabricated solder layer, at a certain temperature backflow carries out soldering reaction, realizes the bonding method of metallurgical connection, is used widely.
Chip-stacked bonding in existing three-dimensional packaging technology has the disadvantage that：Direct Bonding and metal are diffusion interlinked
Bonding temperature is high, and because the thermal expansion coefficient difference of layers of material easily causes greatly wafer warpage, bonding pressure great Yi makes very thin
There is crackle in chip (tending to less than 50 μm), and para-linkage surface smoothness requires high and adds technology difficulty, and bonding time is long,
It is less efficient；The bonding strength of adhesive bond is low, and polymer is easily deteriorated during product military service, and reduction is on active service reliable
Property；Although solder bump bonding can avoid compound and solder, metal between above mentioned problem, the interface metal generated during bonding convex
Point forms the heterogeneous connection of multiple solutions, produces cavity or crackle during military service on interface because of atom counterdiffusion, reduction military service can
By property, solder is low-melting alloy in addition, and limiting solder bump bonding can only be on active service at a lower temperature.Existing patent is used
Make solder realize with the method that the abundant soldering reaction of metal salient point generation is completely reformed into intermetallic compound to be bonded, but have the disadvantage
The soldering reaction time is long, and producing efficiency is low, and the intermetallic compound orientation of formation is random, and the shape easily in intermetallic compound
Into cavity.
The content of the invention
Have present invention solves the technical problem that being to provide a kind of bonding efficiency height, intermetallic compound along thermograde direction
There are the chip-stacked use intermetallic compound bonding method of single-orientated three-dimension packaging and structure.
The technical solution adopted by the present invention is as follows,
A kind of three-dimension packaging is chip-stacked to use intermetallic compound bonding method, including to solder and the metal of solder both sides
Salient point is heated to react to form the process of intermetallic compound to carry out soldering, during the heating, in the pricker
Thermograde is formed between the metal salient point for expecting both sides.
The metal salient point to solder and solder both sides is heated to react to form change between metal to carry out soldering
The process of compound, it is described during solder total overall reaction formation intermetallic compound.
The species of metal salient point and solder of the present invention be this area carry out soldering react to be formed intermetallic compound lead to
Material, wherein, the metal salient point is preferably one kind in Cu, Ni, Au or Ag, and the structure of metal salient point is monocrystalline, selected
Excellent orientation or polycrystalline structure；The solder is preferably Sn, In, SnAg, SnCu, SnBi, SnPb, SnAu, SnIn, SnAgCu
Or one kind in InAg.
Preferably, the metal salient point is monocrystalline or preferred orientation Cu, and solder is one kind in Sn, In or SnCu.
Preferably, the metal salient point is monocrystalline or preferred orientation Ni, and solder is one kind in Sn or In.
Preferably, the metal salient point is monocrystalline or preferred orientation Au, and solder is one kind in Sn, In or SnAu.
Preferably, the metal salient point is monocrystalline or preferred orientation Ag, and solder is one kind in Sn, In, SnAg or InAg.
The form of metal salient point of the present invention can be the bonding structure chip-stacked for three-dimension packaging in can be with pricker
Material forms any form of intermetallic compound.
The temperature of the relatively low side metal salient point of temperature for forming thermograde is higher than the temperature of solder fusing point, is preferably
Higher than 20-30 DEG C of solder fusing point.
It is the temperature difference between metal salient point that the thermograde, which is defined as Δ T/ Δs d, the Δ T, and the Δ d is metal
The distance between salient point.
The thermograde is not less than 20 DEG C/cm；Preferably thermograde is 20~200 DEG C/cm；
More preferably 20~50 DEG C/cm；
More preferably 50~60 DEG C/cm；
More preferably 60~80 DEG C/cm；
More preferably 80~90 DEG C/cm；
More preferably 90~165 DEG C/cm；
More preferably 165~175 DEG C/cm.
In the present invention, during being heated under conditions of thermograde presence to carry out soldering reaction, gold
Category salient point and solder material, thermograde and reaction temperature be influence intermetallic compound growth rate and structure it is most main
Factor is wanted, other factorses influence is smaller；The growth rate of intermetallic compound increases with the increase of thermograde.Therefore, originally
Invention is not limited to the structure in following two kinds of embodiments.
According to one embodiment of the invention, the chip-stacked use intermetallic compound bonding method bag of three-dimension packaging
Include following steps：
Step one：First substrate is provided, the first metal salient point is prepared on first substrate, it is convex in first metal
The first solder layer is prepared on point；Second substrate is provided, the second metal salient point is prepared on second substrate, in second gold medal
The second solder layer is prepared on category salient point；
Step 2：First solder layer and the second solder layer are contacted into placement face-to-face, an assembly is formed；
Step 3：First metal salient point, the first solder layer, the second solder layer, the second metal salient point are heated
Processing is to carry out soldering reaction, during the heating, and temperature ladder is formed between the first metal salient point and the second metal salient point
The second metal salient point is pointed in degree, the direction of thermograde by the first metal salient point, until the first solder layer and the second solder layer are complete
React to form intermetallic compound in portion.
According to another embodiment of the invention, the three-dimension packaging is chip-stacked to use intermetallic compound bonding method
Comprise the following steps：
Step one '：First substrate is provided, the first metal salient point is prepared on first substrate, in first metal
The first solder layer is prepared on salient point；Second substrate is provided, the second metal salient point is prepared on second substrate；
Step 2 '：First solder layer and the second metal salient point are contacted into placement face-to-face, an assembly is formed；
Step 3 '：First metal salient point, the first solder layer, the second metal salient point are heated to carry out
Soldering is reacted, and during the heating, thermograde, thermograde are formed between the first metal salient point and the second metal salient point
Direction by the first metal salient point point to the second metal salient point, until the first solder layer total overall reaction formation intermetallic compound.
In the present invention, the temperature of the first metal salient point is set to be less than the second metal salient point temperature to form the temperature by solder layer
Gradient is spent, wherein, the temperature of the first metal salient point is higher than the temperature of solder fusing point, preferably more than 20-30 DEG C of solder fusing point.
The thermograde is defined as Δ T/ Δs d, the Δ T under the second metal salient point upper surface and the first metal salient point
The temperature difference on surface, the Δ d is the distance between the second metal salient point upper surface and first metal salient point lower surface.
In two kinds of embodiments of the present invention, make the temperature of the first metal salient point less than the second metal salient point temperature with
Form thermograde.The presence of thermograde can cause the generation of thermophoresis phenomenon.Thermophoresis is in thermograde (2 temperature
Poor Δ T and distance between two points Δ d ratio, the i.e. lower atomic migration process occurred of Δ T/ Δs d) effects.From Material Thermodynamics and dynamic
Mechanics viewpoint sees that the thermophoresis of metallic atom is mass transfer occur under certain temperature gradient effect, by diffusion control
Process, its mechanism is that the electronics of high-temperature region has higher scattering energy, and driving metallic atom is determined along the direction that temperature is reduced
To diffusive migration, the mass transfer of metallic atom is produced.Because the size of interconnection structure in three-dimensional packaging technology is small, even if mutually
Even structure memory can also form larger thermograde in less temperature difference.For example, the temperature of 10 μm of interconnection bonding welding point both sides
When degree difference is 0.1 DEG C, the thermograde formed is up to 100 DEG C/cm.The thermograde of formation can trigger a large amount of metals
Atom carries out fast transferring, diffusion from the of a relatively high hot junction of temperature to the relatively low cold end of temperature, so as to substantially speed up cold
The growth of compound between the interface metal of end, and make intermetallic compound of a relatively high to temperature from the relatively low cold end of temperature
Hot junction continuously grows, so as to be prevented effectively from the appearance for the metallic compound Hole to be formed.
Heater in the present invention is that can form the heater of thermograde.
First metal salient point and the second metal salient point can be prepared by technological means commonly used in the art, for example, by electroplating,
The method of sputtering, vapour deposition or evaporation is prepared, with identical arrangement figure；
First solder layer or the second solder layer can be prepared by technological means commonly used in the art, for example, by electroplating, splashing
The method penetrated, be vapor-deposited or be deposited is prepared.
Preferably, the thickness of first metal salient point is 1~20 μm；Solder layer gross thickness (refers in embodiment one
The thickness sum of first solder layer and the second solder layer, refers to the thickness of the first solder layer in embodiment two) it is 0.5~50 μ
m；The thickness of second metal salient point finishes to be formed after intermetallic compound with solder total overall reaction in reacting in soldering, and second
Metal salient point still has residue to be defined.
First substrate is chip or wafer, and the second substrate is chip or wafer, and the first substrate and the second substrate can be with
It is identical can also be different.
The intermetallic compound of the formation can be different because of the material species of solder layer used and contain (or without) last phase,
Last phase is Ag3Sn, richness Pb phases or richness Bi phases.Can be contained using which kind of solder layer (or without) last phase, art
Technical staff is that can determine whether according to prior art.
The three-dimension packaging that is prepared using the above method is chip-stacked to use intermetallic compound bonding structure, first metal
Salient point is monocrystalline or during with preferred orientation, and the intermetallic compound of the formation has single-orientated along thermograde direction.
Beneficial effects of the present invention are as follows：
During bonding introduce thermograde promote metallic atom occur thermophoresis, accelerate interface metal between compound formation,
Growth, significantly improves bonding efficiency；Intermetallic compound is connected from the relatively low cold end of temperature to the of a relatively high hot junction of temperature
Continuous growth, can be prevented effectively from the metallic compound to be formed and hole occur；Metal salient point is using monocrystalline or with preferred orientation gold
Belong to material, select suitable solder, the intermetallic compound of formation have along thermograde direction it is single-orientated, so as to improve
The mechanical property and service reliability of bonding welding point.
This method need not apply pressure when being bonded, and the intermetallic compound bonding welding point formed has well thermally-stabilised
Property；It is bonded using traditional soldering reflux temperature, technological temperature is low；It is good with existing semiconductor and packaging technology compatibility,
Technique is simple, and reliability is high.
Brief description of the drawings
Fig. 1 is the composite unit structure schematic diagram of step 2 formation in embodiment of the present invention one；
Fig. 2 be embodiment of the present invention two in step 2 ' formed composite unit structure schematic diagram；
The intermetallic compound bonding structure schematic diagram that Fig. 3 is prepared for the present invention；
The intermetallic compound bonding structure schematic diagram with last phase that Fig. 4 is prepared for the present invention；
Fig. 5 is the Cu that is formed under the conditions of the embodiment of the present invention 56Sn5The EBSD (EBSD) of intermetallic compound
Photo；
Fig. 6 is (250 DEG C of intermetallic compound growth speed and conventional brazing backflow under the conditions of the embodiment of the present invention 1,2 and 3
Isothermal aging) under the conditions of intermetallic compound growth speed comparison diagram.
Description of reference numerals：The substrates of 10- first, the metal salient points of 20- first, the solder layers of 22- first, the substrates of 30- second,
The metal salient points of 40- second, the solder layers of 42- second, 50- intermetallic compounds, 52- last phases.
Embodiment
With reference to specific drawings and examples, the invention will be further described, and following embodiments are not limited in any way
The system present invention.
Embodiment 1
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Cu first of 5 μ m-thicks are electroplated on first substrate of chip 10
The array of salient point 20, electroplates the first solder layers of Sn 22 of 5 μ m-thicks on first metal salient points of Cu 20；The substrate of chip second is provided
30, the array of the second metal salient points of Cu 40 of 15 μ m-thicks is electroplated on second substrate of chip 30, it is convex in the metals of Cu second
The second solder layers of Sn 42 of 5 μ m-thicks are electroplated on point 40；It is in minute surface that the first metal salient points of Cu 20 and the second metal salient points of Cu 40, which have,
Symmetrical array pattern；
Step 2：The first solder layers of Sn 22 and the second solder layers of Sn 42 are aligned one by one, contact face-to-face is placed, and forms one
Individual assembly, as shown in Figure 1；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Cu 20
Reach 250 DEG C and less than the temperature of the second metal salient points of Cu 40, i.e., in the first metal salient points of Cu 20 and the second metal salient points of Cu 40
Between form 20 DEG C/cm thermograde, until to occur soldering after melting anti-for the first solder layers of Sn 22 and the second solder layers of Sn 42
Cu should be completely reformed into6Sn5Intermetallic compound 50, realizes that the intermetallic compound of chip to chip is bonded, as shown in Figure 3.
As shown in Figure 6, intermetallic compound growth speed is notable under 20 DEG C/cm temperature gradient conditions in the present embodiment
More than the intermetallic compound growth speed under the conditions of conventional brazing backflow (250 DEG C of isothermal agings).
Embodiment 2
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Cu first of 5 μ m-thicks are electroplated on first substrate of chip 10
The array of salient point 20, electroplates the first solder layers of Sn 22 of 10 μ m-thicks on first metal salient points of Cu 20；Wafer second is provided to serve as a contrast
Bottom 30, electroplates the array of the second metal salient points of Cu 40 of 25 μ m-thicks, in the metals of Cu second on second substrate of wafer 30
The second solder layers of Sn 42 of 10 μ m-thicks are electroplated on salient point 40；It is in mirror that the first metal salient points of Cu 20 and the second metal salient points of Cu 40, which have,
The symmetrical array pattern in face；
Step 2：The first solder layers of Sn 22 and the second solder layers of Sn 42 are aligned one by one, contact face-to-face is placed, and forms one
Individual assembly, as shown in Figure 1；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Cu 20
Reach 250 DEG C and less than the temperature of the second metal salient points of Cu 40, i.e., in the first metal salient points of Cu 20 and the second metal salient points of Cu 40
Between formed 40 DEG C/cm thermograde, until Sn the first solder layers 22 and the second solder layer 42 fusing after occur soldering reaction
It is completely reformed into Cu6Sn5Intermetallic compound 50, realizes that the intermetallic compound of chip to wafer is bonded, as shown in Figure 3.
As shown in Figure 6, intermetallic compound growth speed is notable under 40 DEG C/cm temperature gradient conditions in the present embodiment
More than the intermetallic compound growth speed under the conditions of conventional brazing backflow (250 DEG C of isothermal agings).
Embodiment 3
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of wafer 10 is provided, the metals of Cu first of 5 μ m-thicks are electroplated on first substrate of wafer 10
The array of salient point 20, electroplates the first solder layers of Sn 22 of 30 μ m-thicks on first metal salient points of Cu 20；Wafer second is provided to serve as a contrast
Bottom 30, electroplates the array of the second metal salient points of Cu 40 of 30 μ m-thicks on second substrate of wafer 30；The first metal salient points of Cu 20
Have with the second metal salient points of Cu 40 is in the symmetrical array pattern of minute surface；
Step 2：The first solder layers of Sn 22 and the second metal salient points of Cu 40 are aligned one by one, contact face-to-face is placed, and is formed
One assembly, as shown in Figure 2；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Cu 20
Reach 250 DEG C and less than the temperature of the second metal salient points of Cu 40, i.e., in the first metal salient points of Cu 20 and the second metal salient points of Cu 40
Between formed 50 DEG C/cm thermograde, until the first solder layers of Sn 22 melt after occur soldering reaction is completely reformed into Cu6Sn5
Intermetallic compound 50, realizes that the intermetallic compound of wafer to wafer is bonded, as shown in Figure 3.
As shown in Figure 6, intermetallic compound growth speed is notable under 50 DEG C/cm temperature gradient conditions in the present embodiment
More than the intermetallic compound growth speed under the conditions of conventional brazing backflow (250 DEG C of isothermal agings).
Embodiment 4
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Cu first of 1 μ m-thick are sputtered on first substrate of chip 10
The array of salient point 20, sputters the first solder layers of In 22 of 0.5 μ m-thick on first metal salient points of Cu 20；Chip second is provided to serve as a contrast
Bottom 30, the array of the second metal salient points of Cu 40 for 1 μ m-thick that is vapor-deposited on second substrate of chip 30；The metal salient points of Cu first
It is in the symmetrical array pattern of minute surface that the second metal salient points of 20 and Cu 40, which have,；
Step 2：The first solder layers of In 22 and the second metal salient points of Cu 40 are aligned one by one, contact face-to-face is placed, and is formed
One assembly, as shown in Figure 2；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Cu 20
Reach 180 DEG C and less than the temperature of the second metal salient points of Cu 40, i.e., in the first metal salient points of Cu 20 and the second metal salient points of Cu 40
Between formed 55 DEG C/cm thermograde, until the first solder layers of In 22 melt after occur soldering reaction is completely reformed into Cu-In
Intermetallic compound 50, realizes that the intermetallic compound of chip to chip is bonded, as shown in Figure 3.
Embodiment 5
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the monocrystalline Cu first of 1 μ m-thick is sputtered on first substrate of chip 10
The array of metal salient point 20, sputters the first solder layers of SnCu 22 of 0.5 μ m-thick on first metal salient points of monocrystalline Cu 20；There is provided
The second substrate of chip 30, electroplates the array of the second metal salient points of polycrystalline Cu 40 of 30 μ m-thicks on second substrate of chip 30,
The second solder layers of SnCu 42 of 30 μ m-thicks are electroplated on second metal salient points of polycrystalline Cu 40；The He of the first metal salient points of monocrystalline Cu 20
It is in the symmetrical array pattern of minute surface that the second metal salient points of polycrystalline Cu 40, which have,；
Step 2：The first solder layers of SnCu 22 and the second solder layers of SnCu 42 are aligned one by one, contact face-to-face is placed, shape
Into an assembly, as shown in Figure 1；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the first metal salient points of monocrystalline Cu 20
Temperature reaches 250 DEG C and less than the temperature of the second metal salient points of polycrystalline Cu 40, i.e., in the first metal salient points of monocrystalline Cu 20 and polycrystalline
60 DEG C/cm thermograde is formed between the second metal salient points of Cu 40, until the first solder layers of SnCu 22 and the solders of SnCu second
Soldering reaction occurs after the fusing of layer 42 and is completely reformed into Cu6Sn5 intermetallic compounds 50, realizes that chip is changed between the metal of chip
Compound is bonded, as shown in Figure 3.
As shown in Figure 5, under 60 DEG C/cm thermograde effect, the Cu formed on monocrystalline Cu6Sn5Intermetallic
Thing has single-orientated.
Embodiment 6
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Cu first of 1 μ m-thick are deposited on first substrate of chip 10
The array of salient point 20, electroplates the first solder layers of SnPb 22 of 30 μ m-thicks on first metal salient points of Cu 20；Chip second is provided
Substrate 30, electroplates the array of the second metal salient points of Cu 40 of 20 μ m-thicks on second substrate of chip 30；The metal salient points of Cu first
It is in the symmetrical array pattern of minute surface that the second metal salient points of 20 and Cu 40, which have,；
Step 2：The first solder layers of SnPb 22 and the second metal salient points of Cu 40 are aligned one by one, contact face-to-face is placed, shape
Into an assembly, as shown in Figure 2；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Cu 20
Reach 220 DEG C and less than the temperature of the second metal salient points of Cu 40, i.e., in the first metal salient points of Cu 20 and the second metal salient points of Cu 40
Between formed 70 DEG C/cm thermograde, until the first solder layers of SnPb 22 melt after occur soldering reaction is completely reformed into
Cu6Sn5Intermetallic compound 50 and richness Pb last phases 52, realize that the intermetallic compound of chip to chip is bonded, as shown in Figure 4.
Embodiment 7
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Cu first of 2 μ m-thicks are electroplated on first substrate of chip 10
The array of salient point 20, electroplates the first solder layers of SnAgCu 22 of 50 μ m-thicks on first metal salient points of Cu 20；Chip the is provided
Two substrates 30, electroplate the array of the second metal salient points of Cu 40 of 50 μ m-thicks on second substrate of chip 30；The metals of Cu first are convex
It is in the symmetrical array pattern of minute surface that point 20 and the second metal salient points of Cu 40, which have,；
Step 2：The first solder layers of SnAgCu 22 and the second metal salient points of Cu 40 are aligned one by one, contact face-to-face is placed,
An assembly is formed, as shown in Figure 2；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Cu 20
Reach 250 DEG C and less than the temperature of the second metal salient points of Cu 40, i.e., in the first metal salient points of Cu 20 and the second metal salient points of Cu 40
Between formed 80 DEG C/cm thermograde, until the first solder layers of SnAgCu 22 melt after occur soldering reaction is completely reformed into
Cu6Sn5Intermetallic compound 50 and Ag3Sn last phases 52, realize that the intermetallic compound of chip to chip is bonded, such as Fig. 4 institutes
Show.
Embodiment 8
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Ni first of 4 μ m-thicks are electroplated on first substrate of chip 10
The array of salient point 20, electroplates the first solder layers of SnBi 22 of 20 μ m-thicks on first metal salient points of Ni 20；Chip second is provided
Substrate 30, electroplates the array of the second metal salient points of Ni 40 of 20 μ m-thicks, in the gold medals of Ni second on second substrate of chip 30
The second solder layers of SnBi 42 of 20 μ m-thicks are electroplated on category salient point 40；The first metal salient points of Ni 20 and the second metal salient points of Ni 40 have
In the symmetrical array pattern of minute surface；
Step 2：The first solder layers of SnBi 22 and the second solder layers of SnBi 42 are aligned one by one, contact face-to-face is placed, shape
Into an assembly, as shown in Figure 1；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Ni 20
Reach 170 DEG C and less than the temperature of the second metal salient points of Ni 40, i.e., in the first metal salient points of Ni 20 and the second metal salient points of Ni 40
Between form 85 DEG C/cm thermograde, until after melting pricker occurs for the first solder layers of SnBi 22 and the second solder layers of SnBi 42
Weldering reaction is completely reformed into Ni3Sn4Intermetallic compound 50 and richness Bi last phases 52, realize chip to the intermetallic of chip
Thing is bonded, as shown in Figure 4.
Embodiment 9
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the gold medals of Ni first of 10 μ m-thicks are electroplated on first substrate of chip 10
Belong to the array of salient point 20, the first solder layers of In 22 of 25 μ m-thicks are electroplated on first metal salient points of Ni 20；Chip second is provided
Substrate 30, electroplates the array of the second metal salient points of Ni 40 of 50 μ m-thicks, in the gold medals of Ni second on second substrate of chip 30
The second solder layers of In 42 of 25 μ m-thicks are electroplated on category salient point 40；The first metal salient points of Ni 20 and the second metal salient points of Ni 40, which have, is in
The symmetrical array pattern of minute surface；
Step 2：The first solder layers of In 22 and the second solder layers of In 42 are aligned one by one, contact face-to-face is placed, and forms one
Individual assembly, as shown in Figure 1；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Ni 20
Reach 200 DEG C and less than the temperature of the second metal salient points of Ni 40, i.e., in the first metal salient points of Ni 20 and the second metal salient points of Ni 40
Between form 90 DEG C/cm thermograde, until to occur soldering after melting anti-for the first solder layers of In 22 and the second solder layers of In 42
Ni-In intermetallic compounds 50 should be completely reformed into, realize that the intermetallic compound of chip to chip is bonded, as shown in Figure 3.
Embodiment 10
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the monocrystalline Au first of 1 μ m-thick is sputtered on first substrate of chip 10
The array of metal salient point 20, electroplates the first solder layers of SnAu 22 of 1 μ m-thick on first metal salient points of monocrystalline Au 20；Core is provided
The second substrate of piece 30, electroplates the array of the second metal salient points of Au 40 of 3 μ m-thicks on second substrate of chip 30, in the Au
The second solder layers of SnAu 42 of 1 μ m-thick are electroplated on two metal salient points 40；The first metal salient points of monocrystalline Au 20 and the metals of Au second are convex
It is in the symmetrical array pattern of minute surface that point 40, which has,；
Step 2：SnAu the first solder layers 22 and the second solder layer 42 are aligned one by one, contact face-to-face is placed, and forms one
Individual assembly, as shown in Figure 1；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the first metal salient points of monocrystalline Au 20
Temperature reaches 300 DEG C and less than the temperature of the second metal salient points of Au 40, i.e., in the first metal salient points of monocrystalline Au 20 and the gold medals of Au second
130 DEG C/cm thermograde is formed between category salient point 40, until being sent out after SnAu the first solder layers 22 and the fusing of the second solder layer 42
Raw soldering reaction is completely reformed into Au-Sn intermetallic compounds 50, realizes that the intermetallic compound of chip to chip is bonded, such as schemes
Shown in 3.
Embodiment 11
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Au first of 1 μ m-thick are sputtered on first substrate of chip 10
The array of salient point 20, sputters the first solder layers of In 22 of 2 μ m-thicks on first metal salient points of Au 20；The substrate of chip second is provided
30, the array of the second metal salient points of Au 40 of 2 μ m-thicks is sputtered on second substrate of chip 30；The first metal salient points of Au 20 and Au
It is in the symmetrical array pattern of minute surface that second metal salient point 40, which has,；
Step 2：The first solder layers of In 22 and the second metal salient points of Au 40 are aligned one by one, contact face-to-face is placed, and is formed
One assembly, as shown in Figure 2；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Au 20
Reach 180 DEG C and less than the temperature of the second metal salient points of Au 40, i.e., in the first metal salient points of Au 20 and the second metal salient points of Au 40
Between formed 165 DEG C/cm thermograde, until the first solder layers of In 22 melt after occur soldering reaction is completely reformed into Au-
In intermetallic compounds 50, realize that the intermetallic compound of chip to chip is bonded, as shown in Figure 3.
Embodiment 12
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the metals of Ag first of 2 μ m-thicks are sputtered on first substrate of chip 10
The array of salient point 20, electroplates the first solder layers of InAg 22 of 10 μ m-thicks on first metal salient points of Ag 20；Chip second is provided
Substrate 30, electroplates the array of the second metal salient points of Ag 40 of 20 μ m-thicks on second substrate of chip 30；The metal salient points of Ag first
It is in the symmetrical array pattern of minute surface that the second metal salient points of 20 and Ag 40, which have,；
Step 2：The first solder layers of InAg 22 and the second metal salient points of Ag 40 are aligned one by one, contact face-to-face is placed, shape
Into an assembly, as shown in Figure 2；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the temperature of the first metal salient points of Ag 20
Reach 200 DEG C and less than the temperature of the second metal salient points of Ag 40, i.e., in the first metal salient points of Ag 20 and the second metal salient points of Ag 40
Between formed 170 DEG C/cm thermograde, until the first solder layers of InAg 22 melt after occur soldering reaction is completely reformed into
Ag-In intermetallic compounds 50, realize that the intermetallic compound of chip to chip is bonded, as shown in Figure 3.
Embodiment 13
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of chip 10 is provided, the monocrystalline Ag first of 1 μ m-thick is sputtered on first substrate of chip 10
The array of metal salient point 20, electroplates the first solder layers of SnAg 22 of 10 μ m-thicks on first metal salient points of monocrystalline Ag 20；There is provided
The second substrate of chip 30, electroplates the array of the second metal salient points of Ag 40 of 30 μ m-thicks on second substrate of chip 30；Monocrystalline Ag
It is in the symmetrical array pattern of minute surface that first metal salient point 20 and the second metal salient points of Ag 40, which have,；
Step 2：The first solder layers of SnAg 22 and the second metal salient points of Ag 40 are aligned one by one, contact face-to-face is placed, shape
Into an assembly, as shown in Figure 2；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the first metal salient points of monocrystalline Ag 20
Temperature reaches 200 DEG C and less than the temperature of the second metal salient points of Ag 40, i.e., in the first metal salient points of monocrystalline Ag 20 and the gold medals of Ag second
175 DEG C/cm thermograde is formed between category salient point 40, is reacted all until after melting soldering occurs for the first solder layers of SnAg 22
It is changed into Ag3Sn intermetallic compounds 50, realize that the intermetallic compound of chip to chip is bonded, as shown in Figure 3.
Embodiment 14
Three-dimension packaging of the present invention is chip-stacked to be realized with intermetallic compound bonding method by following concrete technology steps：
Step one：The first substrate of wafer 10 is provided, the preferred orientation Cu of 5 μ m-thicks is electroplated on first substrate of wafer 10
The array of first metal salient point 20, electroplates the solder layers of Sn first of 25 μ m-thicks on first metal salient points of preferred orientation Cu 20
22；The second substrate of wafer 30 is provided, the array of the second metal salient points of Cu 40 of 50 μ m-thicks is electroplated on second substrate of wafer 30,
The second solder layers of Sn 42 of 25 μ m-thicks are electroplated on second metal salient points of Cu 40；The He of the first metal salient points of preferred orientation Cu 20
It is in the symmetrical array pattern of minute surface that the second metal salient points of Cu 40, which have,；
Step 2：The first solder layers of Sn 22 and the second solder layers of Sn 42 are aligned one by one, contact face-to-face is placed, and forms one
Individual assembly, as shown in Figure 1；
Step 3：The assembly of the formation of heating stepses two simultaneously carries out soldering backflow, makes the metal salient points of preferred orientation Cu first
20 temperature reaches 260 DEG C and less than the temperature of the second metal salient points of Cu 40, i.e., in the He of the first metal salient points of preferred orientation Cu 20
200 DEG C/cm thermograde is formed between the second metal salient points of Cu 40, until the first solder layers of Sn 22 and the second solder layers of Sn 42
Soldering reaction occurs after fusing and is completely reformed into Cu6Sn5Intermetallic compound 50, realizes wafer to the intermetallic compound of wafer
Bonding, as shown in Figure 3.
Comparative example 1
In this comparative example, set and heat using the temperature for carrying out soldering reaction as 250 DEG C, do not form thermograde, i.e.,
Conventional brazing backflow (isothermal aging) under the conditions of reacted, other steps, material and process conditions etc. with the phase of embodiment 1
Together.
The intermetallic compound growth speed of this comparative example is as shown in 250 DEG C of isothermal aging curve maps in Fig. 6.
Claims (6)
1. a kind of three-dimension packaging is chip-stacked to use intermetallic compound bonding method, including convex to the metal of solder and solder both sides
Point is heated to react to form the process of intermetallic compound to carry out soldering, it is characterised in that during the heating,
Thermograde is formed between the metal salient point of the solder both sides,
The metal salient point is one kind in monocrystalline or preferred orientation Cu, Ni, Au, Ag, wherein,
When the metal salient point is monocrystalline or preferred orientation Cu, solder is one kind in Sn, In or SnCu；
When the metal salient point is monocrystalline or preferred orientation Ni, solder is one kind in Sn or In；
When the metal salient point is monocrystalline or preferred orientation Au, solder is one kind in Sn, In or SnAu；
When the metal salient point is monocrystalline or preferred orientation Ag, solder is one kind in Sn, In, SnAg or InAg；
The intermetallic compound has single-orientated along thermograde direction.
2. three-dimension packaging according to claim 1 is chip-stacked to use intermetallic compound bonding method, it is characterised in that institute
Thermograde is stated not less than 20 DEG C/cm.
3. three-dimension packaging according to claim 2 is chip-stacked to use intermetallic compound bonding method, it is characterised in that institute
Thermograde is stated for 20-200 DEG C/cm.
4. three-dimension packaging according to claim any one of 1-3 is chip-stacked to use intermetallic compound bonding method, it is special
Levy and be, the described method comprises the following steps：
Step one：First substrate (10) is provided, the first metal salient point (20) is prepared on first substrate (10), described
The first solder layer (22) is prepared on one metal salient point (20)；Second substrate (30) is provided, prepared on second substrate (30)
Second metal salient point (40), the second solder layer (42) is prepared on second metal salient point (40)；
Step 2：By the first solder layer (22) and the second solder layer (42), contact is placed face-to-face, forms an assembly；
Step 3：To first metal salient point (20), the first solder layer (22), the second solder layer (42), the second metal salient point
(40) heated and react to form intermetallic compound (50) to carry out soldering, during the heating, in the first metal
Thermograde is formed between salient point (20) and the second metal salient point (40), the direction of thermograde is referred to by the first metal salient point (20)
To the second metal salient point (40).
5. three-dimension packaging according to claim any one of 1-3 is chip-stacked to use intermetallic compound bonding method, it is special
Levy and be, the described method comprises the following steps：
Step one '：First substrate (10) is provided, the first metal salient point (20) is prepared on first substrate (10), described
The first solder layer (22) is prepared on first metal salient point (20)；Second substrate (30) is provided, made on second substrate (30)
Standby second metal salient point (40)；
Step 2 '：By the first solder layer (22) and the second metal salient point (40), contact is placed face-to-face, forms an assembly；
Step 3 '：First metal salient point (20), the first solder layer (22), the second metal salient point (40) are carried out at heating
Reason reacts to form intermetallic compound (50) to carry out soldering, during the heating, makes the temperature of the first metal salient point (20)
Less than the temperature formation thermograde of the second metal salient point (40), the direction of thermograde points to the by the first metal salient point (20)
Two metal salient points (40).
6. the three-dimension packaging of the method preparation described in claim 4 or 5 is chip-stacked to use intermetallic compound bonding structure, it is special
Levy and be, first metal salient point (20) is for monocrystalline or with preferred orientation, intermetallic compound (50) edge of the formation
Thermograde direction has single-orientated.
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| CN105171168B (en) * | 2015-07-13 | 2018-03-30 | 哈尔滨工业大学深圳研究生院 | A kind of High-temperature Packaging Cu6Sn5The orientation interconnecting method of base monocrystalline Lead-Free Solder Joint |
| CN105834541A (en) * | 2016-06-04 | 2016-08-10 | 北京工业大学 | Preparing method for low-temperature-connection and high-temperature-use Cu/Sn/Cu brazing interface and structure |
| CN106735663B (en) * | 2017-01-17 | 2019-05-28 | 大连理工大学 | The preparation method and structure of compound thin space microbonding point between a kind of all-metal |
| CN108663402A (en) * | 2018-03-14 | 2018-10-16 | 北京工业大学 | A kind of miniature solder joint thermophoresis test method |
| CN109813752A (en) * | 2019-02-20 | 2019-05-28 | 重庆理工大学 | A kind of method for evaluating reliability of Electronic Packaging microbonding point |
| CN110744163B (en) * | 2019-11-11 | 2022-04-19 | 重庆理工大学 | Heat migration resistant micro welding spot structure and preparation method thereof |
| CN112317972B (en) * | 2020-09-30 | 2021-07-20 | 厦门大学 | Low-temperature rapid manufacturing method of unidirectional high-temperature-resistant welding joint |
| CN114433971B (en) * | 2021-12-20 | 2023-07-25 | 中国电子科技集团公司第二十九研究所 | Method for carrying out stacking welding with assistance of magnetic vibration particles |
| WO2023179845A1 (en) * | 2022-03-22 | 2023-09-28 | Huawei Digital Power Technologies Co., Ltd. | Semiconductor power entity and method for producing such entity by hybrid bonding |
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