A kind of InAlN/GaN HEMT device that etch stop layer is arranged
Technical field
The present invention relates to a kind of InAlN/GaN HEMT device that etch stop layer is arranged.
Background technology
InAlN/GaN HEMT device has broad application prospects.The HEMT device not only has great application prospect in high temperature resistant digital circuit, and has very big application potential and good circuit compatibility in microwave high power device and circuit, therefore studies the HEMT device and has very important significance.
The surface distance raceway groove of InAlN/GaN HEMT device barrier layer InAlN is nearer, and more greatly, it is also bigger that living resistance is omitted in the source to the raceway groove influence, forms raceway groove simultaneously at the InAlN/GaN place.Also have report to adopt the dry etching grooving to make enhanced AlGaN/GaN HEMT device, but do not adopt the etching termination tech, etching depth can't accurately be controlled, and the rate of finished products of device is low.The device manufacture method of introducing in the document among the IEEE " High Performance E-mode InAIN/GaN HEMTs:Interface States from Subthreshold Slopes ", because barrier layer is very thin, when this kind method is made device, the difficult control of grid grooving technology etching depth, cause a large amount of waste products easily, simultaneously dry method grooving etching also can cause ion bombardment and the damage that produces, causes device performance degeneration.Conventional InAlN/GaN HEMT device does not have etch stop layer and cap layer, and vertically etching depth can't accurately be controlled, and the rate of finished products that device is made is lower, and device performance is relatively poor; And the surface distance raceway groove is nearer, and is bigger to the raceway groove influence.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of InAlN/GaN HEMT device that etch stop layer is arranged.
For solving the problems of the technologies described above, the technical solution used in the present invention is:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged is characterized in that, comprising:
Si, SiC, Sapphire or GaN substrate; AlN nucleating layer on substrate; GaN channel layer on nucleating layer; In on channel layer
XThe AlN barrier layer, 0<X<1; In on barrier layer
XGaN or In
XThe AlGaN etch stop layer, 0<X<1; In on etch stop layer
XAlN cap layer, 0<X<1; The source electrode and the drain electrode that contact with etch stop layer or cap layer; The groove metal gate electrode or the insulated gate electrodes that contact with etch stop layer.Source region, drain region can flutedly can not have groove.
Insulating material in the insulated gate electrodes comprises SiO
2And Si
3N
4
Also be included in resilient coating and back of the body barrier layer between nucleating layer and the channel layer, resilient coating is below back of the body barrier layer, and the material of resilient coating is GaN, and the material of back of the body barrier layer is Al
XGaN, 0<X<1.
Also be included in the separator between channel layer and the barrier layer, the material of separator is AlN.
Also be included in the protective dielectric layer that the protection other materials is not corroded on the cap layer, the protective medium material comprises SiO
2And Si
3N
4
Adopt the beneficial effect that technique scheme produced to be:
1, the present invention has increased etch stop layer, and its advantage is 1), make vertically to be etched on the etch stop layer and stop automatically, realize the accurate control of etching depth, improved the rate of finished products that device is made, reduced the complexity of technology.2), realize the making of notched gates InAlN/GaN HEMT device, and then realize the making of enhancement device.3), can realize that enhancement mode and depletion device are manufactured on a wafer, are used for integrated.4), improved device puncture voltage, reduce the dead resistance between the grid of source, improved device performance.
2, the etch stop layer material is selected In
XGaN or In
XAlGaN, the growth temperature of these materials and InAlN growth temperature coupling do not have pyroprocess.Prevent that pyroprocess from impacting the InAlN of growth in advance, to outdiffusion, reduce the quality of material as In, even cause scrapping etc.In addition, can adopt alkaline corrosion liquefaction to learn the wet method selective etching, avoid the damage in the dry etching.
3, increased the cap layer, the cap layer thickness is the corrosion depth of design, adds that the cap layer can make semiconductor surface away from raceway groove, reduces the influence of surface to raceway groove.Except that the semiconductor under the grid recess, the semiconductor between the drain region, source region is thicker, and its polarization is stronger, can reduce the dead resistance between the grid of source, between the drain-gate like this.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 is embodiment 1 schematic diagram;
Fig. 2 is embodiment 2 schematic diagrames;
Fig. 3 is embodiment 3 schematic diagrames;
Fig. 4 is embodiment 4 schematic diagrames.
1 is substrate, and 2 is nucleating layer, and 3 is resilient coating, and 4 are back of the body barrier layer, and 5 is channel layer, and 6 is separator, and 7 is barrier layer, and 8 is etch stop layer, and 9 is the cap layer, and 10 is protective dielectric layer, and 11 is gate electrode, and 12 is the source electrode, and 13 is drain electrode, and 14 is insulating material.
Embodiment
Embodiment 1:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: Sapphire substrate 1; AlN nucleating layer 2 on substrate 1; GaN resilient coating 3 on nucleating layer 2; Al on resilient coating 3
XGaN carries on the back barrier layer 4, X=0.2; GaN channel layer 5 on back of the body barrier layer 4; AlN separator 6 on channel layer 5; In on separator 6
XAlN barrier layer 7, X=0.15; In on barrier layer 7
XAlGaN etch stop layer 8, X=0.05; In on etch stop layer 8
XAlN cap layer 9, X=0.15; Si on cap layer 9
3N
4 Insulating material 10; The groove metal gate electrode 11 that contacts with etch stop layer, source electrode 12, drain electrode 13.
Embodiment 2:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: SiC substrate 1; AlN nucleating layer 2 on substrate 1; GaN channel layer 5 on nucleating layer 2; In on channel layer 5
XAlN barrier layer 7, X=0.16; In on barrier layer 7
XGaN etch stop layer 8, X=0.17; In on etch stop layer 8
XAlN cap layer 9, X=0.16; The groove metal gate electrode 11 that contacts with etch stop layer; The source electrode 12 that contacts with the cap layer, drain electrode 13.
Embodiment 3:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: GaN substrate 1; AlN nucleating layer 2 on substrate 1; GaN channel layer 5 on nucleating layer 2; In on channel layer 5
XAlN barrier layer 7, X=0.15; In on barrier layer 7
XGaN etch stop layer 8, X=0.13; In on etch stop layer 8
XAlN cap layer 9, X=0.15; SiO on cap layer 9
2 Protective medium 10; The groove metal gate electrode 11 that contacts with etch stop layer, source electrode 12, drain electrode 13.
Embodiment 4:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: Si substrate 1; AlN nucleating layer 2 on substrate 1; GaN channel layer 5 on nucleating layer 2; In on channel layer 5
XAlN barrier layer 7, X=0.15; In on barrier layer 7
XGaN etch stop layer 8, X=0.13; In on etch stop layer 8
XAlN cap layer 9, X=0.15; SiO on cap layer 9
2 Protective medium 10; The groove insulation gate electrode 11 that contacts with etch stop layer, source electrode 12, drain electrode 13, insulating material 14.