CN102290439B - InAIN/ GaN HEM device with etch stop layer - Google Patents
InAIN/ GaN HEM device with etch stop layer Download PDFInfo
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- CN102290439B CN102290439B CN 201110250151 CN201110250151A CN102290439B CN 102290439 B CN102290439 B CN 102290439B CN 201110250151 CN201110250151 CN 201110250151 CN 201110250151 A CN201110250151 A CN 201110250151A CN 102290439 B CN102290439 B CN 102290439B
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- barrier layer
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- 239000000463 material Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 4
- 239000010980 sapphire Substances 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims description 27
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 229910002704 AlGaN Inorganic materials 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 7
- 238000009413 insulation Methods 0.000 abstract description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000005036 potential barrier Methods 0.000 abstract 6
- 238000005530 etching Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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Abstract
The invention discloses an InAIN/ GaN HEMT device with an etch stop layer. The device comprises a Si, SiC, Sapphire or GaN substrate, a buffer layer, a back potential barrier layer and the insulation layer, wherein the substrate is sequentially provided with an AIN nucleating layer, a GaN channel layer, an InXAIN potential barrier layer, an InXGaN or InXAIGaN etch stop layer, an InXAIN cap layer, a source electrode, a drain electrode, a groove metal gate electrode or an insulation gate electrode; the buffer layer and the back potential barrier layer are arranged between the nucleating layer and the channel layer; the buffer layer is below the back potential barrier layer, and the material of the buffer layer is GaN, and the material of the back potential barrier layer is AlXGaN, X is grater than 0 but less than 1; the insulation layer is arranged between the channel layer and the potential barrier layer and the material of the insulation layer is AIN. According to the invention, the yield of device manufacturing can be improved, simultaneously, the accurate control of etch depth can be realized without the damages of dry etching, the process is simple and feasible and has lower cost, and the device performances are improved.
Description
Technical field
The present invention relates to a kind of InAlN/GaN HEMT device that etch stop layer is arranged.
Background technology
InAlN/GaN HEMT device has broad application prospects.The HEMT device not only has great application prospect in high temperature resistant digital circuit, and has very large application potential and good circuit compatibility in microwave high power device and circuit, therefore studies the HEMT device and has very important significance.
The surface distance raceway groove of InAlN/GaN HEMT device barrier layer InAlN is nearer, and more greatly, it is also larger that living resistance is omitted in the source on the raceway groove impact, forms simultaneously raceway groove at the InAlN/GaN place.Also have report to adopt the dry etching grooving to make enhanced AlGaN/GaN HEMT device, but do not adopt the etching termination tech, etching depth can't accurately be controlled, and the rate of finished products of device is low.The device manufacture method of introducing in the document among the IEEE " High Performance E-mode InAIN/GaN HEMTs:Interface States from Subthreshold Slopes ", because barrier layer is very thin, when this kind method is made device, the difficult control of grid grooving technique etching depth, cause easily a large amount of waste products, simultaneously dry method grooving etching also can cause Ions Bombardment and the damage that produces, causes device performance degeneration.Conventional InAlN/GaN HEMT device does not have etch stop layer and cap layer, and vertically etching depth can't accurately be controlled, and the rate of finished products that device is made is lower, and device performance is relatively poor; And the surface distance raceway groove is nearer, and is larger on the raceway groove impact.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of InAlN/GaN HEMT device that etch stop layer is arranged.
For solving the problems of the technologies described above, the technical solution used in the present invention is:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged is characterized in that, comprising:
Si, SiC, Sapphire or GaN substrate; AlN nucleating layer on substrate; GaN channel layer on nucleating layer; In on channel layer
XThe AlN barrier layer, 0＜X＜1; In on barrier layer
XGaN or In
XThe AlGaN etch stop layer, 0＜X＜1; In on etch stop layer
XAlN cap layer, 0＜X＜1; The source electrode and the drain electrode that contact with etch stop layer or cap layer; The groove metal gate electrode or the insulated gate electrodes that contact with etch stop layer.Source region, drain region can be fluted can be without groove.
Insulating material in the insulated gate electrodes comprises SiO
2And Si
3N
4
Also be included in resilient coating and back of the body barrier layer between nucleating layer and the channel layer, resilient coating is below back of the body barrier layer, and the material of resilient coating is GaN, and the material of back of the body barrier layer is Al
XGaN, 0＜X＜1.
Also be included in the separator between channel layer and the barrier layer, the material of separator is AlN.
Also be included in the protective dielectric layer that the protection other materials is not corroded on the cap layer, the protective medium material comprises SiO
2And Si
3N
4
The beneficial effect that adopts technique scheme to produce is:
1, the present invention has increased etch stop layer, and its advantage is 1), make vertically to be etched on the etch stop layer and automatically stop, realizing the accurate control of etching depth, improved the rate of finished products that device is made, reduced the complexity of technique.2), realize the making of notched gates InAlN/GaN HEMT device, and then realize the making of enhancement device.3), can realize that enhancement mode and depletion device are manufactured on a wafer, for integrated.4), improved device puncture voltage, reduce the dead resistance between the grid of source, improved device performance.
2, the etch stop layer material is selected In
XGaN or In
XAlGaN, the growth temperature of these materials and InAlN growth temperature coupling do not have pyroprocess.Prevent that pyroprocess from impacting the InAlN of in advance growth, to outdiffusion, reduce the quality of material such as In, even cause scrapping etc.In addition, can adopt alkaline corrosion liquefaction to learn wet selective etching, avoid the damage in the dry etching.
3, increased the cap layer, the cap layer thickness is the corrosion depth of design, adds that the cap layer can make semiconductor surface away from raceway groove, reduces the surface to the impact of raceway groove.Except the semiconductor under the grid recess, the semiconductor between the drain region, source region is thicker, and its polarization is stronger, can reduce like this dead resistance between the grid of source, between the drain-gate.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 is embodiment 1 schematic diagram;
Fig. 2 is embodiment 2 schematic diagrames;
Fig. 3 is embodiment 3 schematic diagrames;
Fig. 4 is embodiment 4 schematic diagrames.
1 is substrate, and 2 is nucleating layer, and 3 is resilient coating, and 4 are back of the body barrier layer, and 5 is channel layer, and 6 is separator, and 7 is barrier layer, and 8 is etch stop layer, and 9 is the cap layer, and 10 is protective dielectric layer, and 11 is gate electrode, and 12 is the source electrode, and 13 is drain electrode, and 14 is insulating material.
Embodiment
Embodiment 1:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: Sapphire substrate 1; AlN nucleating layer 2 on substrate 1; GaN resilient coating 3 on nucleating layer 2; Al on resilient coating 3
XGaN carries on the back barrier layer 4, X=0.2; GaN channel layer 5 on back of the body barrier layer 4; AlN separator 6 on channel layer 5; In on separator 6
XAlN barrier layer 7, X=0.15; In on barrier layer 7
XAlGaN etch stop layer 8, X=0.05; In on etch stop layer 8
XAlN cap layer 9, X=0.15; Si on cap layer 9
3N
4 Insulating material 10; The groove metal gate electrode 11 that contacts with etch stop layer, source electrode 12, drain electrode 13.
Embodiment 2:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: SiC substrate 1; AlN nucleating layer 2 on substrate 1; GaN channel layer 5 on nucleating layer 2; In on channel layer 5
XAlN barrier layer 7, X=0.16; In on barrier layer 7
XGaN etch stop layer 8, X=0.17; In on etch stop layer 8
XAlN cap layer 9, X=0.16; The groove metal gate electrode 11 that contacts with etch stop layer; The source electrode 12 that contacts with the cap layer, drain electrode 13.
Embodiment 3:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: GaN substrate 1; AlN nucleating layer 2 on substrate 1; GaN channel layer 5 on nucleating layer 2; In on channel layer 5
XAlN barrier layer 7, X=0.15; In on barrier layer 7
XGaN etch stop layer 8, X=0.13; In on etch stop layer 8
XAlN cap layer 9, X=0.15; SiO on cap layer 9
2 Protective medium 10; The groove metal gate electrode 11 that contacts with etch stop layer, source electrode 12, drain electrode 13.
Embodiment 4:
A kind of InAlN/GaN HEMT device that etch stop layer is arranged comprises: Si substrate 1; AlN nucleating layer 2 on substrate 1; GaN channel layer 5 on nucleating layer 2; In on channel layer 5
XAlN barrier layer 7, X=0.15; In on barrier layer 7
XGaN etch stop layer 8, X=0.13; In on etch stop layer 8
XAlN cap layer 9, X=0.15; SiO on cap layer 9
2 Protective medium 10; The groove insulation gate electrode 11 that contacts with etch stop layer, source electrode 12, drain electrode 13, insulating material 14.
Claims (4)
1. the InAlN/GaN HEMT device that etch stop layer is arranged is characterized in that, comprising:
Substrate (1), nucleating layer (2) on described substrate (1), channel layer (5) on described nucleating layer (2), barrier layer (7) on described channel layer (5), etch stop layer (8) on described barrier layer (7), cap layer (9) on described etch stop layer, the source electrode (12) and the drain electrode (13) that contact with etch stop layer (8) or cap layer (9), the groove metal gate electrode (11) that contacts with etch stop layer (8) or insulated gate electrodes (11);
Described backing material is Si or SiC or Sapphire or GaN, and the material of described nucleating layer is AlN, and the material of described channel layer is GaN, and the material of described barrier layer is In
XAlN, the material of described etch stop layer are In
XGaN or In
XAlGaN, the material of described cap layer are In
XAlN, 0＜X＜1.
2. a kind of InAlN/GaN HEMT device that etch stop layer is arranged as claimed in claim 1, it is characterized in that, also be included in resilient coating (3) and back of the body barrier layer (4) between nucleating layer (2) and the channel layer (5), resilient coating (3) is below back of the body barrier layer (4), the material of resilient coating (3) is GaN, and the material of back of the body barrier layer (4) is Al
XGaN, 0＜X＜1.
3. a kind of InAlN/GaN HEMT device that etch stop layer is arranged as claimed in claim 1 or 2 is characterized in that also be included in the separator (6) between channel layer (5) and the barrier layer (7), the material of separator (6) is AlN.
4. a kind of InAlN/GaN HEMT device that etch stop layer is arranged as claimed in claim 3 is characterized in that, also is included in the protective dielectric layer (10) on the cap layer (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110250151 CN102290439B (en) | 2011-08-29 | 2011-08-29 | InAIN/ GaN HEM device with etch stop layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110250151 CN102290439B (en) | 2011-08-29 | 2011-08-29 | InAIN/ GaN HEM device with etch stop layer |
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| Publication Number | Publication Date |
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| CN102290439A CN102290439A (en) | 2011-12-21 |
| CN102290439B true CN102290439B (en) | 2013-02-20 |
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| CN 201110250151 Expired - Fee Related CN102290439B (en) | 2011-08-29 | 2011-08-29 | InAIN/ GaN HEM device with etch stop layer |
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| DE112011105988B4 (en) | 2011-12-23 | 2020-08-06 | Intel Corporation | III-N material structure for gate recess transistors |
| CN104167444A (en) * | 2014-08-27 | 2014-11-26 | 电子科技大学 | Gallium-nitride-based heterojunction field effect transistor with local cap layer |
| CN108346687B (en) * | 2018-01-03 | 2021-02-09 | 东南大学 | Gallium nitride-based high electron mobility transistor |
| CN111755330A (en) * | 2019-03-26 | 2020-10-09 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112219283A (en) * | 2020-07-01 | 2021-01-12 | 英诺赛科（珠海）科技有限公司 | Semiconductor device and method for manufacturing the same |
| CN115812246A (en) * | 2020-08-13 | 2023-03-17 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method thereof |
| CN115360087A (en) * | 2022-09-22 | 2022-11-18 | 徐州金沙江半导体有限公司 | Method for enhancing dielectric film adhesion PECVD film of gallium nitride device |
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| JP2003163226A (en) * | 2001-11-27 | 2003-06-06 | Fujitsu Quantum Devices Ltd | Field effect compound semiconductor device and manufacturing method therefor |
| JP2004273655A (en) * | 2003-03-07 | 2004-09-30 | Nippon Telegr & Teleph Corp <Ntt> | Heterostructure field effect transistor |
| US20070018199A1 (en) * | 2005-07-20 | 2007-01-25 | Cree, Inc. | Nitride-based transistors and fabrication methods with an etch stop layer |
| CN100576467C (en) * | 2007-08-28 | 2009-12-30 | 中国电子科技集团公司第十三研究所 | Utilize indium to mix and improve the method for gallium nitride based transistor material and device performance |
| CN100557815C (en) * | 2008-03-24 | 2009-11-04 | 西安电子科技大学 | InAlN/GaN heterojunction enhancement type high electron mobility transistor structure and manufacture method |
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Inventor after: Xing Dong Inventor after: Feng Zhihong Inventor after: Liu Bo Inventor after: Fang Yulong Inventor after: Dun Shaobo Inventor after: Zhang Xiongwen Inventor after: Cai Shujun Inventor before: Xing Dong |
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Free format text: CORRECT: INVENTOR; FROM: XING DONG TO: XING DONG FENG ZHIHONG LIU BO FANG YULONG GUO SHAOBO ZHANG XIONGWEN CAI SHUJUN |
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Granted publication date: 20130220 |