CN102270591A - One-step die-bonding process of two semiconductor chips - Google Patents

One-step die-bonding process of two semiconductor chips Download PDF

Info

Publication number
CN102270591A
CN102270591A CN 201110213819 CN201110213819A CN102270591A CN 102270591 A CN102270591 A CN 102270591A CN 201110213819 CN201110213819 CN 201110213819 CN 201110213819 A CN201110213819 A CN 201110213819A CN 102270591 A CN102270591 A CN 102270591A
Authority
CN
China
Prior art keywords
chip
solder
tin
depth
degree
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 201110213819
Other languages
Chinese (zh)
Other versions
CN102270591B (en
Inventor
桑林波
韩福彬
陶少勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Great Team Backend Foundry Dongguan Co Ltd
Original Assignee
Great Team Backend Foundry Dongguan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Great Team Backend Foundry Dongguan Co Ltd filed Critical Great Team Backend Foundry Dongguan Co Ltd
Priority to CN 201110213819 priority Critical patent/CN102270591B/en
Publication of CN102270591A publication Critical patent/CN102270591A/en
Application granted granted Critical
Publication of CN102270591B publication Critical patent/CN102270591B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The invention discloses a one-step die-bonding process of two semiconductor chips. The process comprises the following steps of: (a) extruding the shape of the solder by using a solder by use of a die-bonding head which has a die-bonding surface with a size larger than that of an assembly of the two semiconductor chips in parallel arrangement, and then placing the first chip on the solder and pressing down to form the welded joint between the chip and a substrate; and (b) placing the second chip on the solder and pressing down to form the welded joint of the chip and the substrate. The solder which has a required shape and size for the two chips is formed by use of the single large die-bonding head, and the larger the press-bonding head, the more perfect the shape of the solder; and the action of welding the first chip and the action of welding the second chip are performed in sequence, so that the solder has a relatively perfect shape and a small slope, which facilitates follow-up operations. Besides, the device-changing time is saved.

Description

Dual semiconductor chip sheet single stamping technique
Technical field
The present invention relates to the semiconductor packaging field, particularly relate to dual semiconductor chip sheet single stamping technique.
Background technology
In semiconductor chip welding encapsulation technology field, at first scolding tin is pressed into homogeneous thickness and shape with pressing die head, chip is attached on the scolding tin welds again then.Pressing die head is used to regulate evenness, thickness and the width of the scolding tin between chip and the substrate.
The stamping technique that the present dual semiconductor chip sheet that welding arranged side by side is arranged welds employing is to adopt two different pressing die head to carry out.Extrude the tin shape that first chip needs with first pressing die head, place first chip then on tin and press down and form first chip and weld with substrate; Go to extrude the needed tin shape of second chip with second pressing die head, place second chip then on tin and press down and form second chip and weld with substrate.Owing to be two chips of welding,, carry out the action of welding chip then at twice so extrude two the needed scolding tin shape of chip sizes respectively with twice.
Because pressing die head is more little, moulded section is poor more, and the shape of the twice each pressing mold tin formation of pressing mold is very little, so the tin shape of two chip intersections is very imperfect, may cause tin to overflow beyond substrate.For example, when extruding the required scolding tin shape of second chip, second pressing die head can be pressed onto the border of first pressing die head, cause twice formed scolding tin of pressing mold to link together herein easily and form backflow, thereby cause two chips middle than higher, the lower chip in both sides tilts, thereby causes in next flow process bonding wire equipment vision system correctly not to be familiar with, thus the problem that can not carry out the bonding wire operation.
Summary of the invention
The objective of the invention is to avoid weak point of the prior art and a kind of dual semiconductor chip sheet single stamping technique is provided, its saving changes the machine time, and the shape of tin that pressing mold forms is more perfect.
Purpose of the present invention realizes by following technical measures.
Dual semiconductor chip sheet single stamping technique, step comprises:
(a) with the die pressing surface size surpass the twin-core sheet side by side the pressing die head of size extrude the tin shape, place first chip then on tin and press down and form chip and weld with substrate;
(b) place second chip on tin and press down and form chip and weld with substrate.
Be provided with around the die pressing surface of described pressing die head and constitute rectangular four perimeter rows air drains.
The degree of depth of described die pressing surface is 0.04mm, and the degree of depth of described perimeter rows air drain is 0.16mm.
The diagonal of described perimeter rows air drain is provided with the cross bleed groove.
Described cross bleed groove is identical with the degree of depth and the width of described perimeter rows air drain.
The degree of depth of described cross bleed groove is less than the degree of depth of described perimeter rows air drain.
The present invention extrudes two the needed scolding tin shape of chip sizes with single big pressing die head, pressing die head is bigger, the shape that extrudes tin is perfect more, weld the action of first chip and second chip then successively, can form the relatively perfectly shape of tin, and gradient is less, is beneficial to subsequent job; Save the machine time that changes simultaneously.
Embodiment
The invention will be further described with the following Examples.
Dual semiconductor chip sheet single stamping technique, step comprises:
(a) with the die pressing surface size surpass the twin-core sheet side by side the pressing die head of size extrude the tin shape, place first chip then on tin and press down and form chip and weld with substrate;
(b) place second chip on tin and press down and form chip and weld with substrate.
Owing to be two chips of welding, so extrude two the needed scolding tin shape of chip sizes, divide then and carry out the action of welding chip successively, but do not carry out the pressing mold action with single big pressing die head.Can form the relatively perfectly shape of tin, and gradient is less, is beneficial to subsequent job.
And saving changes the machine time, and the shape of tin that pressing mold forms is more perfect, solves chip and tilts to help follow-up bonding wire operation.
Be provided with around the die pressing surface of described pressing die head and constitute rectangular four perimeter rows air drains.
The degree of depth of described die pressing surface is 0.04mm, and the degree of depth of described perimeter rows air drain is 0.16mm.
The diagonal of described perimeter rows air drain is provided with the cross bleed groove.
Described cross bleed groove is identical with the degree of depth and the width of described perimeter rows air drain.
The degree of depth of described cross bleed groove is less than the degree of depth of described perimeter rows air drain.
Should be noted that at last; above embodiment only is used to illustrate technical scheme of the present invention but not limiting the scope of the invention; although the present invention has been done detailed description with reference to preferred embodiment; those of ordinary skill in the art is to be understood that; can make amendment or be equal to replacement technical scheme of the present invention, and not break away from the essence and the scope of technical solution of the present invention.

Claims (6)

1. dual semiconductor chip sheet single stamping technique, it is characterized in that: step comprises:
(a) with the die pressing surface size surpass the twin-core sheet side by side the pressing die head of size extrude the tin shape, place first chip then on tin and press down and form chip and weld with substrate;
(b) place second chip on tin and press down and form chip and weld with substrate.
2. dual semiconductor chip sheet single stamping technique according to claim 1 is characterized in that: be provided with rectangular four the perimeter rows air drains of formation around the die pressing surface of described pressing die head.
3. dual semiconductor chip sheet single stamping technique according to claim 2, it is characterized in that: the degree of depth of described die pressing surface is 0.04mm, the degree of depth of described perimeter rows air drain is 0.16mm.
4. dual semiconductor chip sheet single stamping technique according to claim 2, it is characterized in that: the diagonal of described perimeter rows air drain is provided with the cross bleed groove.
5. dual semiconductor chip sheet single stamping technique according to claim 4 is characterized in that: described cross bleed groove is identical with the degree of depth and the width of described perimeter rows air drain.
6. dual semiconductor chip sheet single stamping technique according to claim 4, it is characterized in that: the degree of depth of described cross bleed groove is less than the degree of depth of described perimeter rows air drain.
CN 201110213819 2011-07-29 2011-07-29 One-step die-bonding process of two semiconductor chips Active CN102270591B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201110213819 CN102270591B (en) 2011-07-29 2011-07-29 One-step die-bonding process of two semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201110213819 CN102270591B (en) 2011-07-29 2011-07-29 One-step die-bonding process of two semiconductor chips

Publications (2)

Publication Number Publication Date
CN102270591A true CN102270591A (en) 2011-12-07
CN102270591B CN102270591B (en) 2013-04-24

Family

ID=45052834

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201110213819 Active CN102270591B (en) 2011-07-29 2011-07-29 One-step die-bonding process of two semiconductor chips

Country Status (1)

Country Link
CN (1) CN102270591B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463886A (en) * 1989-09-04 1995-11-07 Rothenberger Werkzeuge-Maschinen Gmbh Method and apparatus for manufacturing of soldering rod containing copper
CN1534747A (en) * 2003-03-27 2004-10-06 �¹������ҵ��ʽ���� Device and method for mfg. leal wire frame formed by pressure and formed lead wire frame

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5463886A (en) * 1989-09-04 1995-11-07 Rothenberger Werkzeuge-Maschinen Gmbh Method and apparatus for manufacturing of soldering rod containing copper
CN1534747A (en) * 2003-03-27 2004-10-06 �¹������ҵ��ʽ���� Device and method for mfg. leal wire frame formed by pressure and formed lead wire frame

Also Published As

Publication number Publication date
CN102270591B (en) 2013-04-24

Similar Documents

Publication Publication Date Title
CN102270591B (en) One-step die-bonding process of two semiconductor chips
CN102856216B (en) Method for packaging square and flat soldering lug without pin
CN104269359A (en) Novel quad fat no-lead package process method
CN114783895A (en) Application method of aluminum strip bonding wire in packaging body and manufactured semiconductor device
CN204885149U (en) Lead wire frame construction of rectifier bridge
CN204361085U (en) Die-attach area height heat conduction flip-chip encapsulating structure
CN104835772B (en) Pad pasting ball bonding pressing plate after a kind of QFN
CN104538378A (en) Wafer level package structure and technological method thereof
CN207149554U (en) Lead frame and semiconductor devices
CN202855732U (en) MOSFET pipe leading wire framework welded by utilizing triode wire welding machine
CN202153516U (en) Dual enhanced integrated circuit lead frame plate
CN107481990A (en) Lead frame, semiconductor devices and its packaging technology
CN204596772U (en) Pad pasting ball bonding pressing plate after a kind of QFN
CN111656505A (en) Bonding tool for a bonding machine, bonding machine for bonding semiconductor elements and associated method
CN204375738U (en) Wafer-level package structure
CN204375730U (en) A kind of wafer-level package structure
CN104600047A (en) Power module and packaging method thereof
CN104465586B (en) A kind of wafer-level package structure and its process
CN105489531B (en) A kind of COB die bonds wire bonding system and method
CN215869454U (en) LED support
CN104952737B (en) A kind of package frame structure and production method with aluminium strip or L pin or projection
CN105470189B (en) A kind of twin islet frame bonding heat block and fixture
CN202803802U (en) Improved press mold head for semiconductor component packaging
CN207705150U (en) A kind of aluminium strip chopper with impression solder joint
CN212917981U (en) Die head structure suitable for multi-chip

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant