CN102263092B - 半导体模块及其制造方法 - Google Patents

半导体模块及其制造方法 Download PDF

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CN102263092B
CN102263092B CN201110022812.2A CN201110022812A CN102263092B CN 102263092 B CN102263092 B CN 102263092B CN 201110022812 A CN201110022812 A CN 201110022812A CN 102263092 B CN102263092 B CN 102263092B
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dielectric substrate
metal
solder layer
semiconductor chip
semiconductor module
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CN102263092A (zh
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羽鸟宪司
长谷川滋
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Mitsubishi Electric Corp
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Abstract

本发明的目的在于提供一种能够抑制焊料空隙的产生并且维持良好的组装性的半导体模块及其制造方法。本发明的半导体模块具有：绝缘衬底（4）；多个半导体芯片（1），在绝缘衬底（4）表面彼此隔离配置；焊料层（9），在绝缘衬底（4）背面侧，仅形成在与配置有各半导体芯片（1）的位置对应的位置；底板（6），隔着焊料层（9）与绝缘衬底（4）连接。

Description

半导体模块及其制造方法
技术领域
本发明涉及半导体模块及其制造方法，特别涉及用于对配置了半导体元件的绝缘衬底背面的焊料层中的焊料空隙的产生进行抑制的半导体模块及其制造方法。
背景技术
在以往的半导体模块中，对于搭载了例如功率用的半导体芯片的绝缘衬底来说，从散热以及位置固定的必要性出发，一般隔着焊料层焊接在底板上。
专利文件1 特开2003－60158号公报
此时，当为了半导体模块的省空间化而使搭载半导体芯片的绝缘衬底较薄时，存在如下问题：在使绝缘衬底的尺寸大型化了的情况下，热膨胀所引起的翘曲的影响变大，在形成于绝缘衬底下的焊料层中容易产生焊料空隙等，组装性恶化。
发明内容
本发明是为了解决上述课题而提出的，其目的是提供能够抑制焊料空隙的产生并且维持良好的组装性的半导体模块及其制造方法。
本发明的半导体模块具有：绝缘衬底；多个半导体芯片，在所述绝缘衬底表面彼此隔离配置；焊料层，在所述绝缘衬底背面侧，仅形成在与配置有各所述半导体芯片的位置对应的位置；底板，隔着所述焊料层与所述绝缘衬底连接。
此外，本发明的半导体模块的制造方法具有：工序（a），准备绝缘衬底；工序（b），在所述绝缘衬底表面，彼此隔离地配置多个半导体芯片；工序（c），在所述绝缘衬底背面侧，仅在与配置有各所述半导体芯片的位置对应的位置形成焊料层；工序（d），隔着所述焊料层连接所述绝缘衬底与底板。
根据本发明的半导体模块，具有绝缘衬底、在所述绝缘衬底表面彼此隔离配置的多个半导体芯片、在所述绝缘衬底背面侧仅形成在与配置有各所述半导体芯片的位置对应的位置的焊料层、隔着所述焊料层与所述绝缘衬底连接的底板，由此，能够抑制焊料空隙的产生并且维持良好的组装性。
此外，根据本发明的半导体模块的制造方法，具有：工序（a），准备绝缘衬底；工序（b），在所述绝缘衬底表面，彼此隔离地配置多个半导体芯片；工序（c），在所述绝缘衬底背面侧，仅在与配置有各所述半导体芯片的位置对应的位置形成焊料层；以及工序（d），隔着所述焊料层连接所述绝缘衬底与底板，由此，能够抑制焊料空隙的产生并且维持良好的组装性。
附图说明
图1是表示实施方式1的半导体模块的结构的图。
图2是表示实施方式2的半导体模块的结构的图。
图3是表示作为前提技术的半导体模块的结构的图。
附图标记说明：
1 半导体芯片
2、7、9 焊料层
3、5 金属
4 绝缘衬底
6 底板
8 焊料空隙
10、11 金属镀层。
具体实施方式
如图3所示，在作为本发明的前提技术的半导体模块中，半导体芯片1隔着焊料层2配置在金属3上，多个金属3在绝缘衬底4上彼此隔离形成。
在绝缘衬底4的背面，在整个面形成有金属5，绝缘衬底4隔着焊料层7配置在底板6上。
此处，如图3所示，当由于热膨胀等而在绝缘衬底4产生翘曲时，在焊料层7中产生焊料空隙8，使半导体模块的组装性恶化。
在以下的实施方式中所示出的本发明涉及用于解决该问题的半导体模块的结构。
<A. 实施方式1>
<A-1. 结构>
图1所示的是本实施方式1的半导体模块的结构。如图1所示，半导体芯片1隔着焊料层2配置在金属3上，多个金属3彼此隔离形成在绝缘衬底4上。
在绝缘衬底4的背面，在整个面形成有金属5，绝缘衬底4隔着作为第一金属镀层（metal plating）的金属镀层10和焊料层9配置在底板6上。
金属镀层10和焊料层9选择性地仅形成在与配置有半导体芯片1的区域对应的其正下方的区域，此外，彼此隔离。
通过做成这样的结构，由此，如图1所示，即便由于热膨胀等而在绝缘衬底4产生翘曲，由于焊料层9隔离，所以，焊料空隙的产生被抑制，能够良好地保持半导体模块的组装性。
并且，半导体芯片1能够使用SiC等宽带隙半导体。
<A-2. 制造方法>
然后，对上述的半导体模块的制造方法进行说明。首先，准备绝缘衬底4，在其表面选择性地形成金属3。此外，在绝缘衬底4的背面形成金属5。
然后，在金属5上的与半导体芯片1的正下方对应的区域形成焊料润湿性高的金属镀层10。在金属镀层10上分别形成焊料层9。然后，使其与底板6接触进行连接。
此外，在各个金属3上形成焊料层2，分别配置对应的半导体芯片1。多个半导体芯片1彼此隔离配置。
<A-3. 效果>
根据本发明的实施方式1，在半导体模块中具有绝缘衬底4、在绝缘衬底4表面彼此隔离配置的多个半导体芯片1、在绝缘衬底4背面侧仅在与配置有各半导体芯片1的位置对应的位置形成的焊料层9、隔着焊料层9与绝缘衬底4连接的底板6，由此，以确保散热路径并且绝缘衬底4背面的带焊料的区域不变大的方式进行抑制，此外，能够抑制焊料空隙8的产生并且维持良好的组装性。此外，由于焊料区域减少，所以，其结果是，能够实现半导体芯片1配置、半导体模块的缩小（shrink）。
此外，根据本发明的本实施方式1，在半导体模块中，还具有仅在绝缘衬底4背面的与配置有各半导体芯片1的位置对应的位置所形成的作为第一金属镀层的金属镀层10，焊料层9形成在金属镀层10上，由此，能够抑制焊料层8的产生并且维持良好的组装性。
此外，根据本发明的实施方式1，在半导体模块的制造方法中，具有工序（a），准备绝缘衬底4；工序（b），在绝缘衬底4表面，彼此隔离地配置多个半导体芯片1；工序（c），在绝缘衬底4背面侧，仅在与配置有各半导体芯片1的位置对应的位置形成焊料层9；工序（d），隔着焊料层9连接绝缘衬底4与底板6，由此，能够抑制焊料空隙8的产生并且维持良好的组装性。
此外，根据本发明的实施方式1，在半导体模块的制造方法中，还具有工序（e），在工序（c）之前，仅在绝缘衬底4背面的与配置有各半导体芯片1的位置对应的位置，形成作为第一金属镀层的金属镀层10，工序（c）是在金属镀层10上形成焊料层9的工序，由此，能够抑制焊料空隙8的产生并且维持良好的组装性。
<B. 实施方式2>
<B-1. 结构>
图2所示的是本实施方式2的半导体模块的结构。如图2所示，半导体芯片1隔着焊料层2配置在金属3上，多个金属3彼此隔离形成在绝缘衬底4上。
在绝缘衬底4的背面，在整个面形成有金属5，绝缘衬底4隔着作为第二金属镀层的金属镀层11和焊料层9配置在底板6上。
金属镀层11和焊料层9选择性地仅形成在与配置有芯片1的区域对应的其正下方的区域，并且彼此隔离。
通过做成这样的结构，由此，如图1所示，即便由于热膨胀等在绝缘衬底4产生翘曲,也能抑制在焊料层9中产生焊料空隙并且良好地保持半导体模块的组装性。
并且，也可以与实施方式1所示的情况组合。即，也可以在图2的结构中具有图1中的金属镀层10。
<B-2. 制造方法>
然后，对上述的半导体模块的制造方法进行说明。首先，准备绝缘衬底4，在其表面选择性地形成金属3。此外，在绝缘衬底4的背面形成金属5。
然后，在底板6上的与后述的半导体芯片1的正下方对应的区域，形成焊料润湿性高的金属镀层11。在金属镀层11上分别形成焊料层9。然后，使其与绝缘衬底4接触进行连接。
此外，在各个金属3上形成焊料层2，分别配置对应的半导体芯片1。多个半导体芯片1彼此隔离配置。
<B-3. 效果>
根据本发明的实施方式2，在半导体模块中，还具有仅在底板6上的与配置有各半导体芯片1的位置对应的位置所形成的作为第二金属镀层的金属镀层11，焊料层9形成在金属镀层11上，由此，能够抑制焊料空隙8的产生并且维持良好的组装性。
此外，根据本发明的实施方式2，在半导体模块的制造方法中，还具有工序（f），在工序（c）之前，仅在底板6上的与配置有各半导体芯片1的位置对应的位置，形成作为第二金属镀层的金属镀层11，工序（c）是在金属镀层11上形成焊料层9的工序，由此，能够抑制焊料空隙8的产生并且维持良好的组装性。

Claims (8)

1.一种半导体模块，具有：
绝缘衬底；
多个半导体芯片，在所述绝缘衬底表面彼此隔离配置；
金属，形成在所述绝缘衬底背面整个面；
焊料层，在所述绝缘衬底背面侧的所述金属上，仅形成在与配置有各所述半导体芯片的位置对应的、其正下方的位置；以及
底板，隔着所述焊料层与所述绝缘衬底连接，
在所述绝缘衬底与所述底板连接的状态下，所述绝缘衬底弯曲。
2.如权利要求1所述的半导体模块，其特征在于：
还具有仅在所述绝缘衬底背面侧的所述金属上的与配置有所述各半导体芯片的位置对应的、其正下方的位置形成的第一金属镀层，
所述焊料层形成在所述第一金属镀层上。
3.如权利要求1或2所述的半导体模块，其特征在于：
还具有仅在所述底板上的与配置有所述各半导体芯片的位置对应的、其正下方的位置形成的第二金属镀层，
所述焊料层形成在所述第二金属镀层上。
4.如权利要求1或2所述的半导体模块，其特征在于：
所述各半导体芯片是SiC半导体芯片。
5.一种半导体模块的制造方法，具有：
工序(a)，准备绝缘衬底；
工序(b)，在所述绝缘衬底表面，彼此隔离地配置多个半导体芯片；
工序(c)，在所述绝缘衬底背面整个面形成金属，然后，在所述绝缘衬底背面侧的所述金属上，仅在与配置有各所述半导体芯片的位置对应的、其正下方的位置形成焊料层；
工序(d)，隔着所述焊料层连接所述绝缘衬底与底板，
在所述绝缘衬底与所述底板连接的状态下，所述绝缘衬底弯曲。
6.如权利要求5所述的半导体模块的制造方法，其特征在于：
还具有工序(e)，在所述工序(c)之前，仅在所述绝缘衬底背面侧的所述金属上的与配置有所述各半导体芯片的位置对应的、其正下方的位置形成第一金属镀层，
所述工序(c)是在所述第一金属镀层上形成所述焊料层的工序。
7.如权利要求5或6所述的半导体模块的制造方法，其特征在于：
还具有工序(f)，在所述工序(c)之前，仅在所述底板上的与配置有所述各半导体芯片的位置对应的、其正下方的位置形成第二金属镀层，
所述工序(c)是在所述第二金属镀层上形成所述焊料层的工序。
8.如权利要求5或6所述的半导体模块的制造方法，其特征在于：
所述工序(b)是在所述绝缘衬底表面彼此隔离地配置多个SiC半导体芯片的工序。
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