CN102263031A - Method for manufacturing trench vertical metal oxide semiconductor (VMOS) transistor - Google Patents
Method for manufacturing trench vertical metal oxide semiconductor (VMOS) transistor Download PDFInfo
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Abstract
The invention provides a method for manufacturing a trench vertical metal oxide semiconductor (VMOS) transistor. The method comprises the following steps of: providing a semiconductor substrate with an epitaxial layer which is internally provided with a trench, wherein grids are formed in the trench, and sources are formed in the epitaxial layer on both sides of each grid; forming an interlamination medium layer which covers the grids above the epitaxial layer, wherein contact holes are formed in the interlamination medium layer and the epitaxial layer, and the contact holes are adjacent to the sources; and forming a metal interconnection layer on the interlamination medium layer and filling the contact holes with the metal interconnection layer, wherein before the steps of forming the metal interconnection layer, steps of forming first metal layers on the side walls of the interlamination medium layer and the contact holes and at the bottoms of the interlamination medium layer and the contact holes by a chemical vapor deposition method, and forming second metal layers on the first metal layers by a physical vapor deposition method are involved; and the second metal layers and the first metal layers form a stop metal layer. By the method, metal aluminum is effectively prevented from entering the epitaxial layer and the shortcoming of aluminum puncture is overcome.
Description
Technical field
The present invention relates to groove-shaped VMOS transistor, the transistorized metallized method of particularly groove-shaped VMOS.
Background technology
Along with the electric consumers growth of requirement, the demand of power MOSFET is increasing.Groove-shaped VMOS transistor (Trench Vertical MOS) is because the integrated level of its device is higher, conducting resistance is lower, have lower grid-charge leakage density, bigger current capacity, thereby possess lower switching loss and switching speed faster, be widely used in the low pressure and low power field.
The transistorized manufacture method of a kind of existing groove-shaped VMOS is disclosed in application number is 200910052544.1 Chinese patent application.Please refer to Fig. 1～Fig. 3.As Fig. 1, Semiconductor substrate 100 is provided, be formed with epitaxial loayer 101 on the described Semiconductor substrate 100, in described epitaxial loayer 101, form groove (not marking), form gate oxide 102 at described trenched side-wall and bottom; Form the grid 103 that fills up groove above the gate oxide 102 in described groove.
Then, please refer to Fig. 2, in the epitaxial loayer 101 of described grid 103 both sides, form the transistorized source electrode 109 of groove-shaped VMOS; Form first interlayer dielectric layer 104 and second interlayer dielectric layer 105 of cover gate 103 on described epitaxial loayer 101 successively, described first interlayer dielectric layer 104 and second interlayer dielectric layer 105 are as insulating barrier; Then, form contact hole 111 in described first interlayer dielectric layer 104, second interlayer dielectric layer 105 and epitaxial loayer 101, described contact hole 111 extends in the epitaxial loayer 101, and adjacent with the transistorized source electrode of described groove-shaped VMOS 109.
Then, please refer to Fig. 3, carry out metallization step, form interconnection structure, concrete technology comprises: contact metal layer 106 is formed on sidewall and bottom at described contact hole 111, is used to reduce the contact resistance of described metal interconnecting layer 108 and the transistorized source electrode 109 of groove-shaped VMOS; Form barrier metal layer 107 above described contact metal layer 106, the aluminium that is used for barrier metal interconnection layer 108 enters in the epitaxial loayer 101; Above described barrier metal layer 107, form metal interconnecting layer 108, be used for the transistorized source electrode 109 of groove-shaped VMOS is connected with external electric.Wherein, the material of described contact metal layer 106 is selected from titanium (Ti), and the material of described barrier metal layer 107 is selected from titanium nitride (TiN), and the material of described metal interconnecting layer 108 is selected from aluminium (Al) or aluminium alloy (for example aluminium copper, alusil alloy).Aluminium in the above-mentioned metal interconnecting layer 108 can enter in the described epitaxial loayer 101 by barrier metal layer 107, contact metal layer 106, form the defective of junction spiking (Al Spiking), described defective has not only reduced the switching speed of device, more can cause the transistorized leakage current of groove-shaped VMOS.
Therefore, need the transistorized manufacture method of a kind of groove-shaped VMOS, can eliminate the defective of junction spiking.
Summary of the invention
The technical problem that the present invention solves has provided the transistorized manufacture method of a kind of groove-shaped VMOS, has solved the problem of junction spiking.
In order to address the above problem, the invention provides the transistorized manufacture method of a kind of groove-shaped VMOS, described method comprises:
The Semiconductor substrate that is formed with epitaxial loayer is provided, has groove in the described epitaxial loayer, be formed with grid in the described groove, the epitaxial loayer that is positioned at described grid both sides is formed with source electrode;
Form the interlayer dielectric layer of cover gate above described epitaxial loayer, be formed with contact hole in described interlayer dielectric layer and the epitaxial loayer, described contact hole and source electrode are adjacent;
On interlayer dielectric layer, form metal interconnecting layer, and described metal interconnecting layer is filled full contact hole;
Wherein, before described formation metal interconnecting layer, comprise step:
Utilize the method for chemical vapour deposition (CVD) to form the first metal layer in the sidewall and the bottom of described interlayer dielectric layer, contact hole;
Utilize the method for physical vapour deposition (PVD) to form second metal level on described the first metal layer, described second metal level and the first metal layer constitute described barrier metal layer.
Optionally, described the first metal layer material is a titanium nitride.
Optionally, the method that forms the first metal layer is to utilize ammoniacal liquor and two formicester ammonia titaniums or ammoniacal liquor and diethanolamine titanium to carry out chemical vapour deposition (CVD).
Optionally, the material of described second metal level is a titanium nitride.
Optionally, forming second metal level is to utilize argon gas, nitrogen and titanium target to carry out physical vapour deposition (PVD).
Optionally, before forming described barrier metal layer, also comprise step: contact metal layer is formed on sidewall and bottom at interlayer dielectric layer, contact hole.
Optionally, the material of described contact metal layer is a titanium.
Optionally, described second metal layer thickness is greater than described the first metal layer thickness, and wherein said the first metal layer thickness range is 100～150 dusts, and the described second metal layer thickness scope is 1300～1700 dusts.
Optionally, the described metal interconnecting layer utilization deposition machine that forms second metal level forms.
Optionally, the material of described metal interconnecting layer is an aluminum or aluminum alloy.
Compared with prior art, the present invention has the following advantages: form contact hole in first interlayer dielectric layer and second interlayer dielectric layer, the method of utilizing chemical vapour deposition (CVD) is at described contact hole sidewall and bottom deposit the first metal layer, the first metal layer that adopts this kind sedimentation to form is good at the step of contact hole, promptly the junction spreadability to the bottom of contact hole and sidewall is good, sidewall and the junction, bottom of effectively avoiding aluminium in the follow-up metal interconnecting layer to penetrate contact hole enter epitaxial loayer, form the junction spiking problem; Then, utilize the method for physical vapour deposition (PVD) above described the first metal layer, to form second metal level, owing to adopt the thickness of second metal layer thickness of physical vaporous deposition formation greater than the first metal layer that adopts chemical vapour deposition technique to form, effectively increased the metal layer thickness of contact hole bottom, effectively the aluminium in the barrier metal interconnection layer enters in the epitaxial loayer, has eliminated the defective of junction spiking.
Description of drawings
Fig. 1～Fig. 3 is the transistorized manufacture method cross-sectional view of the groove-shaped VMOS of prior art.
Fig. 4 is the transistorized manufacture method schematic flow sheet of groove-shaped VMOS of the present invention.
Fig. 5～Fig. 8 is the transistorized manufacture method cross-sectional view of groove-shaped VMOS of the present invention.
Embodiment
The inventor finds that the transistorized aperture of contact hole of existing groove-shaped VMOS is bigger, usually more than or equal to 0.6 micron, can reach 2 microns under some situation.Prior art forms the method that barrier metal layer only utilizes chemical vapour deposition (CVD) or physical vapour deposition (PVD) at channel bottom and sidewall.Wherein, the uniformity of physical gas-phase deposite method when the deposition barrier metal layer is bad, thereby the barrier metal layer that forms is bad at the step of contact hole, promptly bad in the barrier metal layer spreadability of the sidewall of contact hole and junction, bottom, enter epitaxial loayer owing to make sidewall and the junction, bottom that metal interconnecting layer and metal alloy technology makes the aluminium of metal interconnecting layer penetrate contact hole, thereby form junction spiking at follow-up high temperature (300～400 degrees centigrade); Though and if utilize chemical gaseous phase depositing process deposition during barrier metal layer the sidewall of contact hole and bottom good uniformity, but the chemical vapor deposition method time is long, deposition velocity is slow, the barrier metal layer that forms the same thickness that forms with existing physical vapour deposition (PVD) needs the time longer, for example physical gas-phase deposite method forms the titanium nitride metal of 100 dusts, need 10～50 seconds, and forming the titanium nitride metal needs of 100 dusts, chemical gaseous phase depositing process wants 100～200 seconds, and the titanium nitride metal that chemical gaseous phase depositing process need form is thick more, the process time that needs is long more, bigger for the makers' manufacturing cost of wafer, therefore, the existing thinner thickness that utilizes the barrier metal layer of chemical gaseous phase depositing process formation can not stop aluminium effectively, forms junction spiking easily in the contact hole bottom.
In order to solve the junction spiking problem, the inventor proposes the transistorized manufacture method of a kind of groove-shaped VMOS, please refer to Fig. 4, and Fig. 4 is the transistorized manufacture method schematic flow sheet of groove-shaped VMOS of the present invention.Described method comprises:
Step S1 provides the Semiconductor substrate that is formed with epitaxial loayer, has groove in the described epitaxial loayer, is formed with grid in the described groove, and the epitaxial loayer that is positioned at described grid both sides is formed with source electrode;
Step S2, the interlayer dielectric layer of formation cover gate is formed with contact hole in described interlayer dielectric layer and the epitaxial loayer above described epitaxial loayer, and described contact hole and source electrode are adjacent;
Step S3 forms contact metal layer in the sidewall and the bottom of described interlayer dielectric layer, contact hole;
Step S4 utilizes the method for chemical vapour deposition (CVD) to form the first metal layer in the sidewall and the bottom of described contact metal layer, contact hole;
Step S5 utilizes the method for physical vapour deposition (PVD) to form second metal level on described the first metal layer, and described second metal level and the first metal layer constitute described barrier metal layer;
Step S6 forms metal interconnecting layer on described barrier metal layer.
Below in conjunction with specific embodiment technical scheme of the present invention is described in detail.Please refer to Fig. 5 to Fig. 8, Fig. 5～Fig. 8 is the transistorized manufacture method cross-sectional view of groove-shaped VMOS of the present invention.
At first, please refer to Fig. 5.Semiconductor substrate 200 is provided, is formed with epitaxial loayer 201 on the described Semiconductor substrate 200.Be formed with groove (not marking) in the described epitaxial loayer 201, be formed with the transistorized grid 203 of groove-shaped VMOS in the described groove, the epitaxial loayer 201 that is positioned at described grid 203 both sides is formed with the transistorized source electrode 209 of groove-shaped VMOS.The manufacture method of described grid 203 and source electrode 209 is those skilled in the art's a known technology.In the present embodiment, the manufacture method of described grid 203 comprises: form groove in described epitaxial loayer 201; In the sidewall and the bottom deposit oxide layer of described groove, form the transistorized gate oxide 202 of groove-shaped VMOS; In described groove, form polysilicon gate 203, as the transistorized grid of groove-shaped VMOS.The manufacture method of described source electrode 209 comprises: form the mask layer (not shown) above described epitaxial loayer 201, described mask layer has and the source-drain electrode corresponding opening; With described mask layer is that mask carries out the ion injection, forms source electrode 209.
Then, please refer to Fig. 6, form the interlayer dielectric layer that covers described grid 203 on described epitaxial loayer 202, described interlayer dielectric layer is as insulating barrier.In the present embodiment, described interlayer dielectric layer comprises first dielectric layer 204 and second dielectric layer 205.As an embodiment, the manufacture method of described interlayer dielectric layer comprises: deposition first dielectric layer 204 above described epitaxial loayer 202, and the material of described first dielectric layer 204 is selected from low temperature oxide; Above described first dielectric layer 204, form second dielectric layer 205, constitute interlayer dielectric layer with first dielectric layer 204.The material of described second dielectric layer 205 is selected from silica, organic silicate glass or Pyrex.
Still with reference to figure 6, described second dielectric layer 205, first dielectric layer 204, epitaxial loayer 201 are carried out etching, form contact hole 211 in described first dielectric layer 204, second dielectric layer 205 and epitaxial loayer 201, described contact hole 211 is adjacent with source electrode 209.Described contact hole 211 has aperture value d, and the scope of common described aperture value d is 0.6 micron～3 microns.
Then, please refer to Fig. 7, contact metal layer 206 is formed on sidewall and bottom at described second dielectric layer 205, contact hole 211, and described contact metal layer 206 covers described second dielectric layer 205, is used to reduce the metal interconnecting layer of follow-up making step formation and the contact resistance of source electrode 209.In the present embodiment, the material of described contact metal layer 206 is selected from titanium (Ti), and the thickness range of described contact metal layer 206 is 200～800 dusts.As an embodiment, the formation method of described contact metal layer 206 comprises physical vapour deposition (PVD) or chemical vapour deposition (CVD).
Then, still with reference to figure 7, utilize the method for chemical vapour deposition (CVD) to form the first metal layer 207a at the bottom and the sidewall of described contact metal layer 206, contact hole 211, as an embodiment, the material of described the first metal layer 207a is selected from titanium nitride (TiN), and its thickness range is 100～150 dusts.As preferred embodiment, the thickness range of described the first metal layer 207a is 120～130 dusts.The first metal layer 207a of the method deposition of described chemical vapour deposition (CVD) has good spreadability, be that described chemical gaseous phase depositing process is even at the sidewall of described contact hole 211 and the formation the first metal layer 207a thickness above the bottom, the metal interconnecting layer that has solved follow-up formation is in the sidewall of contact hole 211 and the junction spiking problem of bottom.Usually, the method for described chemical vapour deposition (CVD) comprises heating step, chemical gas phase reaction step.Described heating step at first rises to the temperature of setting with the temperature of chemical vapour deposition (CVD) board cavity by room temperature, and the temperature of setting described in the present embodiment is 400～450 degrees centigrade; Then, utilize ammoniacal liquor and two formicester ammonia titaniums (TDMAT) or ammoniacal liquor and diethanolamine titanium (TDEAT) to carry out chemical gas phase reaction; Because common described ammoniacal liquor and two formicester ammonia titaniums (TDMAT) or ammoniacal liquor and diethanolamine titanium (TDEAT) react with gas form in chemical vapour deposition (CVD) board cavity, two formicester ammonia titaniums (TDMAT) or diethanolamine titanium (TDEAT) are decomposed, produce titanium nitride atom and gaseous by-product, described accessory substance is extracted board out through the pump of chemical vapour deposition (CVD) board cavity, and a large amount of titanium nitride atoms gathers and silicon chip surface, forms titanium nitride membrane.Because the accessory substance that produces in chemical gas phase reaction process may be accumulated in cavity inner wall, uniformity to titanium nitride membrane is influential, therefore, in the chemical gas phase reaction step, every step of removing impurity at regular intervals, guaranteeing the titanium nitride membrane good uniformity of deposition, thereby the first metal layer 207a that has guaranteed deposition has good homogeneous, and is good at the step of the bottom of contact hole and sidewall.
With reference to figure 7, utilize the method for physical vapour deposition (PVD) above described the first metal layer 207a, to form the second metal level 207b, constitute barrier metal layer 207 with described the first metal layer 207a.The material of the described second metal level 207b is identical with the material of the first metal layer 207a, and its thickness is greater than the thickness of the first metal layer 207a, and the described second metal level 207b has solved the junction spiking problem of contact hole 211 bottoms.As an embodiment, the described second metal layer thickness scope is 1300～1700 dusts.Preferably, the thickness range of the described second metal level 207b is 1400～1600 dusts.Described physical gas-phase deposite method need not to heat up, and directly utilizes argon gas, nitrogen and titanium target, forms the second metal level 207b.Be specially: utilize after the ionization argon ion bombardment titanium target, sputter titanium atom; Utilize electric field that titanium atom is quickened, the titanium atom of acceleration and nitrogen reaction become the titanium nitride atom, and migrate to silicon chip surface; A large amount of titanium nitride atomic cohesions and formation film (being the second metal level 207b), the material of described film is a titanium nitride.Utilize the process time of physical vapour deposition (PVD) short, the thickness of the second metal level 207b of formation is bigger, can stop that the aluminium of follow-up metal interconnection layer enters in the epitaxial loayer.
At last, please refer to Fig. 8, above the described second metal level 207b, form metal interconnecting layer 208.The material of described metal interconnecting layer 208 is selected from aluminium (Al) or aluminium alloy.Described aluminium alloy comprises alusil alloy, aluminium copper.In the present embodiment, described metal interconnecting layer 208 forms by the method for physical vapour deposition (PVD).As the preferred embodiments of the present invention, after second metal level 207b deposition is finished, directly utilize the same physical vapour deposition (PVD) board that forms the second metal level 207b to form metal interconnecting layer 208, need not product is taken out of board, reduce the step that forms metal interconnecting layer 208 like this, simultaneously, reduced product and extraneous contacting, minimizing helps adhering to of the metal interconnecting layer 208 and the second metal level 207b to the pollution of the second metal level 207b.After metal interconnecting layer 208 forms, need carry out alloy technique usually, so that the aluminium of metal interconnecting layer 208 has good the contact with the second metal level 207b.
Need to prove that with reference to figure 7, said method is after contact metal layer 206 forms, need carry out rapid thermal annealing (RTP) technology, make described contact metal layer 206 combine, form titanizing silicon, reduce the aluminium of metal interconnecting layer 208 and the contact resistance of source electrode 209 with the silicon of epitaxial loayer 201.Described RTP annealing process is same as the prior art, and in the present embodiment, the RTP annealing process utilizes N
2, its range of flow is 100～500scsm, annealing time is 10～40s, annealing temperature 450～600 degree.
The step of barrier metal layer of the present invention can also utilize the mode of twice chemical vapour deposition (CVD) to form, and needs the long process time but form satisfactory barrier metal layer, has increased manufacturing cost.Therefore, comparatively preferred mode forms the first metal layer at first utilizing chemical gaseous phase depositing process, utilizes physical gas-phase deposite method to form second metal level then.
Said method utilizes chemical vapour deposition (CVD) to form step and spreadability the first metal layer preferably in the sidewall of contact hole and bottom, and is good in the spreadability of the junction of contact hole bottom and sidewall, solved bottom the contact hole and the junction spiking problem of sidewall junction; Utilize physical vapour deposition (PVD) above the first metal layer, to form second metal level then, second metal layer thickness is bigger, solved the junction spiking problem of contact hole bottom, and described method is utilized same etching machine bench in the step that forms second dielectric layer and plated metal interconnection layer, reduce by a processing step, improve existing board utilance, and reduced the pollution of second dielectric layer top, improve the adhesion effect of the metal interconnecting layer and second dielectric layer.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (10)
1. groove-shaped VMOS transistor fabrication method, described method comprises: the Semiconductor substrate that is formed with epitaxial loayer is provided, has groove in the described epitaxial loayer, be formed with grid in the described groove, the epitaxial loayer that is positioned at described grid both sides is formed with source electrode;
Form the interlayer dielectric layer of cover gate above described epitaxial loayer, be formed with contact hole in described interlayer dielectric layer and the epitaxial loayer, described contact hole and source electrode are adjacent;
On interlayer dielectric layer, form metal interconnecting layer, and described metal interconnecting layer is filled full contact hole;
It is characterized in that, before described formation metal interconnecting layer, comprise step:
Utilize the method for chemical vapour deposition (CVD) to form the first metal layer in the sidewall and the bottom of described interlayer dielectric layer, contact hole;
Utilize the method for physical vapour deposition (PVD) to form second metal level on described the first metal layer, described second metal level and the first metal layer constitute described barrier metal layer.
2. groove-shaped VMOS transistor fabrication method as claimed in claim 1 is characterized in that described the first metal layer material is a titanium nitride.
3. groove-shaped VMOS transistor fabrication method as claimed in claim 1 or 2 is characterized in that, the method that forms the first metal layer is to utilize ammoniacal liquor and two formicester ammonia titaniums or ammoniacal liquor and diethanolamine titanium to carry out chemical vapour deposition (CVD).
4. groove-shaped VMOS transistor fabrication method as claimed in claim 1 is characterized in that the material of described second metal level is a titanium nitride.
5. as claim 1 or 4 described groove-shaped VMOS transistor fabrication methods, it is characterized in that forming second metal level is to utilize argon gas, nitrogen and titanium target to carry out physical vapour deposition (PVD).
6. groove-shaped VMOS transistor fabrication method as claimed in claim 1 is characterized in that, before forming described barrier metal layer, also comprises step: contact metal layer is formed on sidewall and bottom at interlayer dielectric layer, contact hole.
7. groove-shaped VMOS transistor fabrication method as claimed in claim 6 is characterized in that the material of described contact metal layer is a titanium.
8. groove-shaped VMOS transistor fabrication method as claimed in claim 1, it is characterized in that, described second metal layer thickness is greater than described the first metal layer thickness, and wherein said the first metal layer thickness range is 100～150 dusts, and the described second metal layer thickness scope is 1300～1700 dusts.
9. groove-shaped VMOS transistor fabrication method as claimed in claim 1 is characterized in that, the deposition machine that described metal interconnecting layer utilization forms second metal level forms.
10. groove-shaped VMOS transistor fabrication method as claimed in claim 1 is characterized in that the material of described metal interconnecting layer is an aluminum or aluminum alloy.
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| CN2010101928438A CN102263031A (en) | 2010-05-26 | 2010-05-26 | Method for manufacturing trench vertical metal oxide semiconductor (VMOS) transistor |
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| CN2010101928438A CN102263031A (en) | 2010-05-26 | 2010-05-26 | Method for manufacturing trench vertical metal oxide semiconductor (VMOS) transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569182A (en) * | 2012-03-01 | 2012-07-11 | 上海宏力半导体制造有限公司 | Contact hole and manufacturing method thereof as well as semiconductor device |
| CN113782491A (en) * | 2021-08-31 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Contact hole manufacturing method and structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW396566B (en) * | 1997-09-30 | 2000-07-01 | Lucent Technologies Inc | Improved silicon IC contacts using composite TiN barrier layers |
| US6177338B1 (en) * | 1999-02-08 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Two step barrier process |
| CN1388573A (en) * | 2001-05-25 | 2003-01-01 | 矽统科技股份有限公司 | Making process of metal intraconnection wire in semiconductor |
| CN101064295A (en) * | 2006-04-30 | 2007-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
| CN101567338A (en) * | 2009-06-04 | 2009-10-28 | 上海宏力半导体制造有限公司 | Manufacturing method for power MOS transistor |
-
2010
- 2010-05-26 CN CN2010101928438A patent/CN102263031A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW396566B (en) * | 1997-09-30 | 2000-07-01 | Lucent Technologies Inc | Improved silicon IC contacts using composite TiN barrier layers |
| US6177338B1 (en) * | 1999-02-08 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Two step barrier process |
| CN1388573A (en) * | 2001-05-25 | 2003-01-01 | 矽统科技股份有限公司 | Making process of metal intraconnection wire in semiconductor |
| CN101064295A (en) * | 2006-04-30 | 2007-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its making method |
| CN101567338A (en) * | 2009-06-04 | 2009-10-28 | 上海宏力半导体制造有限公司 | Manufacturing method for power MOS transistor |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569182A (en) * | 2012-03-01 | 2012-07-11 | 上海宏力半导体制造有限公司 | Contact hole and manufacturing method thereof as well as semiconductor device |
| CN102569182B (en) * | 2012-03-01 | 2016-07-06 | 上海华虹宏力半导体制造有限公司 | Contact hole and preparation method thereof, semiconductor device |
| CN113782491A (en) * | 2021-08-31 | 2021-12-10 | 上海华虹宏力半导体制造有限公司 | Contact hole manufacturing method and structure |
| CN113782491B (en) * | 2021-08-31 | 2024-01-23 | 上海华虹宏力半导体制造有限公司 | Manufacturing method and structure of contact hole |
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