CN101064295A - Semiconductor device and its making method - Google Patents
Semiconductor device and its making method Download PDFInfo
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- CN101064295A CN101064295A CN 200610026326 CN200610026326A CN101064295A CN 101064295 A CN101064295 A CN 101064295A CN 200610026326 CN200610026326 CN 200610026326 CN 200610026326 A CN200610026326 A CN 200610026326A CN 101064295 A CN101064295 A CN 101064295A
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Abstract
The invention provides semiconductor component and preparing method. The semiconductor component possesses a top metal layer and a lower metal layer which is electric connected with the top metal layer via the middle medium layer. The method firstly covers etch stopping layer on the underlay which possesses metal pattern, its thickness is 100-300 angstrom, covering the blocking layer whose thickness is two times of etch stopping layer on the etch stopping layer, covering middle medium layer on the blocking layer and etching the groove and through hole which are needed by depositing top metal, thereinto existence of the blocking layer avoids peeling off of the etch stopping layer and the middle medium layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of semiconductor device and manufacture method thereof.
Background technology
When semiconductor technology evolves requires more and more high integration, also more and more harsher to the requirement of live width and technology.When little live width technology node strides forward, the crucial solution that the IC industry selects for use copper and low-K material to postpone as the interconnection resistance electric capacity (RC) that reduces 0.13um and following technology node thereof, remove the process of aluminium with respect to etching in the aluminum metal technology, copper has characteristics such as easy diffusion, difficult etching, industry has been introduced dual-damascene technics (Dual Damascene), its characteristics are exactly earlier to form middle dielectric layer on the substrate of device and etch groove and through hole having, cement copper enters in the good figure of etching then, and uses flattening method and remove unnecessary copper.
Generally in the semiconductor device rear part top-level metallic was made, its processing step was generally in formation and has on the substrate of metallic pattern, deposit etching stop layer, middle dielectric layer, copper diffusion trapping layer, copper illuvium, cmp then.Therefore, the dielectric material such as the etching stop layer of corresponding exploitation and dual-damascene technics compatibility, intermediate medium layer material just become and press for.The process integration of copper and low-K material is challenging.
With respect to bigger SIN of dielectric constant (K～7.8) and SION (K～7), the general little SIC (K～5) of dielectric constant that adopts is as etching stop layer in the prior art, adopt chemical gas-phase deposition method deposit fluorine silex glass (FSG) as middle dielectric layer and in technology the fluorine with high concentration reduce its dielectric constant.But the fluorine of high concentration usually is unsettled, thus adhesiveness from its interface to the dielectric layer or the metal level diffusion on both sides that can destroy.Number of patent application is that 99110641 Chinese patent discloses and a kind ofly prevents that by forming at the FSG upper surface method that fluorine material passes silicon oxynitride wherein from solving FSG and diffusing to upper strata corrosion metal and destroy FSG and the problem of the interface of metal adhesion, but the high concentration fluorine causes the adhesiveness variation of FSG and etching stop layer and produces the problem of peeling off in top-level metallic deposition back becoming the problem that the technologist pays close attention to the destruction of lower floor's etching stop layer.
Fig. 1 is the schematic diagram that directly covers middle dielectric layer in the prior art on the etching stop layer.As shown in Figure 1, be coated with etching stop layer 120 and middle dielectric layer 130 on the substrate 100 that metal pattern 110 is arranged, groove 150 and through hole 140 are formed on the middle dielectric layer 130 and in groove 150 and through hole 140 and are filled with metal, for example copper.The schematic diagram that Fig. 2 peels off for the middle dielectric layer on etching stop layer in the prior art and its upper strata.As shown in Figure 2, in copper wiring, the adhesion of non-conductive medium material and its metal level and other auxiliary dielectric layer has problem unavoidably, take place because phenomenon is peeled off in middle dielectric layer 130 and the bad generation of etching stop layer 120 adhesivenesses, peel off phenomenon can occur in this device production process or device production finish after in to passivation layer and outer lead (packaging wire bonding) adhesion strength reliability testing.Produce in process of production and peel off, can cause back layer metal level perk, influence its electrical connection and finally cause device electrically to be failed; If do not peel off in process of production, also can cause the lifetime of device owing to its adhesion property difference.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of semiconductor device and manufacture method thereof, to solve top-level metallic middle dielectric layer and its lower floor's etching stop layer poor adhesion and to produce the problem of peeling off.
For achieving the above object, the invention provides a kind of semiconductor device, comprising:
Substrate; Dielectric layer that on substrate, forms and the metal pattern layer that is formed in the described dielectric layer;
The etching stop layer that on described dielectric layer and metal pattern layer, forms;
The barrier layer that on described etching stop layer, forms;
The middle dielectric layer that on described barrier layer, forms; Have groove and through hole on the described middle dielectric layer, in described groove and through hole, be filled with metal barrier, metal seed layer and interconnecting metal layer successively.
The thickness of described etching stop layer is 100 dusts～300 dusts.
The thickness on described barrier layer is 200 dusts～600 dusts.
Described etching stop layer is at least a kind of or its combination in silica, carborundum (SiC), silicon nitride (SiN), carbon oxynitride (SiOC), the nitrogen-doped silicon carbide.
Described barrier layer is at least a kind of or its combination in silica, carborundum (SiC), silicon nitride (SiN), carbon oxynitride (SiOC), the nitrogen-doped silicon carbide.
Described middle dielectric layer is at least a kind of or its combination in fluorine silex glass (FSG), phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), silica, silicon nitride (SiN), the carborundum (SiC).
The degree of depth of the groove on the described middle dielectric layer is less than the degree of depth of through hole.
Described metal barrier is a kind of or its combination in titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), cobalt (Co), platinum (Pt), titanium tungsten (TiW), titanium nitride (TiN), the tantalum nitride (TaN).
Described metal seed layer is copper, aluminium, tungsten, gold or silver-colored.
Described interconnecting metal layer comprises copper or aluminium.
Described through hole is positioned at corresponding position, metal pattern top.
Interconnecting metal layer in the described through hole is electrically connected with described metal pattern on the described substrate by described metal seed layer and metal barrier.
Correspondingly, the invention provides a kind of manufacture method of semiconductor device, comprising:
Semi-conductive substrate is provided, on substrate, forms dielectric layer and metal pattern layer;
On described dielectric layer and metal pattern layer, form etching stop layer;
On described etching stop layer, form a barrier layer;
On described barrier layer, form middle dielectric layer;
The described middle dielectric layer of etching, barrier layer and etching stop layer form through hole exposing described metal pattern, and form groove at described middle dielectric layer;
In described groove and through hole, fill metal seed layer, metal barrier and interconnecting metal layer successively.
The formation method on described etching stop layer and barrier layer comprises physical vapor deposition (PVD) or chemical vapor deposition (CVD).
Described chemical vapour deposition (CVD) comprises that aumospheric pressure cvd (APCVD), low-pressure chemical vapor deposition (LPCVD), gas ions strengthen chemical vapour deposition (CVD) (PE CVD), high density plasma CVD (HDPCVD).
The thickness of described etching stop layer is 100 dusts～300 dusts.
The thickness on described barrier layer is 200 dusts～600 dusts.
The formation method of described middle dielectric layer comprises physical vapour deposition (PVD), chemical vapour deposition (CVD).
Described metal barrier utilizes physical vapour deposition (PVD) or electro-plating method to form.
Compared with prior art, the present invention has the following advantages: the present invention is by inserting the barrier layer between etching stop layer and middle dielectric layer, stoped the diffusion of the fluorine in the middle dielectric layer to etching stop layer and middle dielectric layer, thereby reduced because fluorine diffusion has freely brought corrosion and the destruction to two-layer interface, helped to increase two-layer adhesion up and down at interface;
In addition, because the bombardment of deposition process intermediate ion is to the destruction and the reorganization of chemical bond, can in the deielectric-coating of deposition, produce very high stress, high membrane stress can cause cracking and layering, barrier layer SiN is because ion bombardment destroys the Si-N key, thereby has high compression, thereby helps the tensile stress of balance intermediate medium layer material fluorine silex glass (FSG), thereby reduced because stress for the influence of the adhesion between layer and the layer, has increased its adhesion.
Description of drawings
Fig. 1 is the schematic diagram that directly covers middle dielectric layer in the prior art on the etching stop layer;
The schematic diagram that Fig. 2 peels off for the middle dielectric layer on etching stop layer in the prior art and its upper strata;
Fig. 3 is the section of structure of semiconductor device of the present invention;
Fig. 4 is the process chart of method, semi-conductor device manufacturing method of the present invention;
Fig. 5 to Figure 10 is the profile of explanation method, semi-conductor device manufacturing method of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 3 is the section of structure of semiconductor device of the present invention.As shown in Figure 3, semiconductor device of the present invention comprises a substrate 100 and is formed at the metal pattern layer 110 in the dielectric layer 105 on the described substrate 100 that metal pattern layer 110 forms by spin coating photoresist (Photoresist) exposure imaging and etching on dielectric layer 105.Be formed with etching stop layer 120 on described dielectric layer 105 and metal pattern layer 110, thickness is 100 dusts～300 dusts, and its material can be a silica, carborundum (SiC), silicon nitride (SiN), carbon oxynitride (SiOC), one or its combination in the nitrogen-doped silicon carbide.The effect of etching stop layer is can not destroy its lower floor's figure when this layer material of etching in order to prevent.Etching stop layer 120 stops layer as the terminal point of the material etching on its upper strata, can protect the metal pattern 110 of its lower floor can not be etched and forms defective.Semiconductor device of the present invention is coated with thickness on etching stop layer 120 be 200 dusts～600 dust barrier layers 125, the material of selecting for use can be silica, carborundum (SiC), silicon nitride (SiN), carbon oxynitride (SiOC), one or its combination in the nitrogen-doped silicon carbide.On barrier layer 125, deposit the middle dielectric layer 130 of advanced low-k materials, reducing the resistance capacitance (RC) that its parasitic capacitance and interconnected metallic resistance cause with interconnecting metal such as copper coupling postpones, optionally material comprises fluorine silex glass (FSG), phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG).
On the middle dielectric layer 130 painting photoresist of passing through is arranged, exposure imaging the figure transfer of mask plate to middle dielectric layer 130 and the through hole 140 and the groove 150 that form, the degree of depth of groove 150 is less than the degree of depth of through hole 140, and whether both connect the needs of the electrical connection of depending on the device decision.In through hole 140 and groove 150, be coated with metal barrier 160 successively, metal seed layer 170, interconnecting metal layer 180, metal barrier comprises titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), cobalt (Co), platinum (Pt), titanium tungsten (TiW), titanium nitride (TiN), a kind of or its combination in the tantalum nitride (TaN), metal seed layer comprises copper, aluminium, tungsten, gold or silver, interconnecting metal layer comprises copper or aluminium.Through hole 140 bottoms link to each other with metal pattern 110 on the substrate 100.
The barrier layer 125 of deposition can increase the adhesiveness of middle dielectric layer 130 and etching stop layer 120, for example, barrier layer 125 materials are SiN, middle dielectric layer 130 materials are generally selected fluorine silex glass (FSG) for use for top-level metallic, fluorine among the FSG has very strong diffusion effect, thereby because in order to reduce resistance capacitance (RC) delay that the dielectric layer material dielectric constant reduces its parasitic capacitance and interconnecting metal resistance, FSG is a fluorine of often selecting high concentration for use in deposition, the fluorine of high concentration is unsettled, its lower floor diffusion of can making progress, fluorine can reduce its adhesiveness to the corrosion of interface, can cause layer with layer peel off, SiN is the barrier layer of good fluorine, the content of N is high more, and the few more generation of the diffusion of fluorine is introduced barrier material and can effectively be stopped its diffusion, reduce its corrosion, increased adhesion property the surface.
In addition, the advanced low-k materials FSG of deposition has tensile stress, high stress in the deielectric-coating can cause layering, deposited barrier layer material SiN using plasma strengthens chemical vapour deposition (CVD), the destruction of deposition process high speed ion pair SiN intermediate ion key can make the SiN film of deposition that very high compression (Compressive stress) is arranged, thereby helps the tensile stress among the balance FSG that the influence of its lower membrane is reduced the lamination that stress brings.
Fig. 4 is the process chart of method, semi-conductor device manufacturing method of the present invention.As shown in Figure 4, the manufacture method of semiconductor device of the present invention.At first, on substrate 100, cover etching stop layer 120 (S210) with metal pattern 110; Then, on etching stop layer 120 by vapour deposition barrier layer 125 (S220); Then, on barrier layer 125, cover middle dielectric layer 130 (S230); By photoetching, be etched on the middle dielectric layer 130 and form through hole 140 and groove 150, and open the barrier layer 125 and the etching stop layer 120 of through hole 140 bottoms, make through hole 140 bottoms expose metal pattern 110 (S240) on the substrate 100; At last, in through hole 140 and groove 150, cover metal barrier 160 (S250); On metal barrier 160, cover metal seed layer 170 (S260); On metal seed layer 170, fill interconnecting metal layer 180 (S270).
Fig. 5 to Figure 10 is the profile of explanation method, semi-conductor device manufacturing method of the present invention.Describe the processing step of this method of realization in detail below in conjunction with Fig. 5 to Figure 10.As shown in Figure 5, the present invention at first forms a dielectric layer 105 and by photoetching, etching and plated metal at substrate 100, copper for example, the metal pattern 110 of formation.
Then, as shown in Figure 6, deposition one etching stop layer 120 on substrate 100 and metal pattern 110, the method for deposition can be a plasma enhanced chemical vapor deposition.Preferably, the thickness of deposition is 100 dust to 300 dusts, and the material of deposition can be a nitrogen-doped silicon carbide, the oxide of silicon, carborundum (SiC), silicon nitride (SiN), one or its combination in the carbon oxynitride (SiOC).This etching stop layer 120 can not diffuse in the upper strata to stop metal such as copper in the lower metal pattern as protection lower metal pattern 110 injury-free barrier material and can be used as the diffusion impervious layer of lower metal when the etching of upper strata.Copper has very strong diffusion effect as the interconnecting metal of back segment as known to persons skilled in the art, thereby etching stop layer also has as the effect that stops the lower metal diffusion.Method, semi-conductor device manufacturing method of the present invention is not that direct accumulation top dielectric layer is finished the deposition to non-conductive dielectric layer on etching stop layer 120, but after deposition-etch stops layer 120, on etching stop layer 120, deposit one deck barrier layer 125 by physical vapor deposition (PVD) or chemical vapor deposition, the thickness on this barrier layer 125 is 200 dusts～600 dusts, the material on this barrier layer can be high density and heavily stressed silicon nitride (SiN) or other organic materials, inorganic material, metal, the oxide that perhaps comprises silicon at least, carborundum (SiC), one or its combination in the carbon oxynitride (SiOC).After the deposition of finishing barrier layer 125, deposit middle dielectric layer 130 thereon, because middle dielectric layer need be selected the little material of dielectric constant for use, the preferred method deposit fluorine silex glass (FSG) that uses chemical vapour deposition (CVD) in the present embodiment, wherein, the concentration height of common fluorine, its dielectric constant can be little, makes its dielectric constant be about 3.7 in the present embodiment.Other optional material comprises fluorine silex glass (FSG), phosphorosilicate glass (PSG), Pyrex (BSG) or boron-phosphorosilicate glass (BPSG).The barrier layer 125 of deposition can stop the diffusion of fluorine in the middle dielectric layer 130 and reduce the tensile stress influence of FSG, has increased the adhesion property of etching stop layer 120 and middle dielectric layer 130, reduced two-layer between layering, defective such as peel off.
Finish after having on the substrate of metal pattern deposition-etch and stopping layer 120, barrier layer 125 and middle dielectric layer 130, as shown in Figure 7, painting photoresist 135 forms pattern 136 by exposure imaging on middle dielectric layer, the definition connecting hole, the position of metal pattern 110 is corresponding on the middle dielectric layer 130 that exposes lower floor, the position of pattern 136 and substrate 100.Then; as shown in Figure 8; this middle dielectric layer 130 of etching; photoresist is covered the position as the middle dielectric layer 130 of barrier layer protected its lower floor of etching by photoresist in etching process; so middle dielectric layer 130 connecting hole positions are owing to expose and can be etched; by dry method or wet etching, on middle dielectric layer 130, form through hole 140.Be etched in when exposing middle dielectric layer 130 lower floor barrier layers 125 and stop, as can be seen, barrier layer 125 is also as the etching stop layer of middle dielectric layer 130.Remove photoresist 135 by ashing (Ashing) and cleaning (strip), just formed the through hole 140 on middle dielectric layer 130.As shown in Figure 9, with on middle dielectric layer 130, forming groove 150 with above-mentioned identical method, the degree of depth of groove 150 is less than the degree of depth of through hole 140, also be the barrier layer 125 that middle dielectric layer 130 lower floors can not exposed in the bottom of groove 150, whether groove 150 is with the link to each other electrical connection needs of the metal that depends on groove 150 and through hole 140 depositions of through hole 140.Continue etching and cleaning then and remove through hole 140 following barrier layer 130 and etching stop layers 125, the metal pattern 110 on the substrate can be exposed by through hole 140.
As shown in figure 10, in groove 150 that forms and through hole 140, insert metal, as copper, because the diffusion effect of copper ion, if it is not handled accordingly, the copper that is filled in through hole 140 and the groove 150 will diffuse to its adjacent dielectric layer such as middle dielectric layer 130, will change the insulation effect of dielectric layer and introduce other ghost effect, influences the performance of device.Thereby be necessary it is carried out suitable processing; usually can first deposit diffusion impervious layer (Diffusion Barrier), by suitable method such as physical vapour deposition (PVD) or chemical vapour deposition (CVD) deposit layer of metal barrier layer 160, its material can be titanium nitride (TiN) 150 kinds of described through hole 140 and grooves; titanium (Ti); tungsten (W), tantalum (Ta), molybdenum (Mo); cobalt (Co); platinum (Pt), titanium tungsten (TiW), a kind of or its combination in the tantalum nitride (TiN).Add metal barrier 160 and can well stop the diffusion of metallic copper, and can strengthen the adhesiveness of metallic copper and its dielectric layer dielectric layer.(Metal seed) 170 of accumulation metal seed layer on metal barrier 160 and interconnecting metal layer 180, its deposit can be physical vapour deposition (PVD), chemical vapour deposition (CVD) or plating.The thickness of metals deposited layer fills up whole through hole 140 and groove 150 at least.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (19)
1, a kind of semiconductor device is characterized in that comprising:
Substrate; Dielectric layer that on substrate, forms and the metal pattern layer that is formed in the described dielectric layer;
The etching stop layer that on described dielectric layer and metal pattern layer, forms;
The barrier layer that on described etching stop layer, forms;
The middle dielectric layer that on described barrier layer, forms; Have groove and through hole on the described middle dielectric layer, in described groove and through hole, be filled with metal barrier, metal seed layer and interconnecting metal layer successively.
2, semiconductor device as claimed in claim 1 is characterized in that: the thickness of described etching stop layer is 100 dusts～300 dusts.
3, semiconductor device as claimed in claim 1 is characterized in that: the thickness on described barrier layer is 200 dusts～600 dusts.
4, semiconductor device as claimed in claim 2 is characterized in that: described etching stop layer is at least a kind of or its combination in silica, carborundum (SiC), silicon nitride (SiN), carbon oxynitride (SiOC), the nitrogen-doped silicon carbide.
5, semiconductor device as claimed in claim 3 is characterized in that: described barrier layer is at least a kind of or its combination in silica, carborundum (SiC), silicon nitride (SiN), carbon oxynitride (SiOC), the nitrogen-doped silicon carbide.
6, semiconductor device as claimed in claim 1 is characterized in that: described middle dielectric layer is at least a kind of or its combination in fluorine silex glass (FSG), phosphorosilicate glass (PSG), Pyrex (BSG), boron-phosphorosilicate glass (BPSG), silica, silicon nitride (SiN), the carborundum (SiC).
7, semiconductor device as claimed in claim 1 is characterized in that: the degree of depth of the groove on the described middle dielectric layer is less than the degree of depth of through hole.
8, semiconductor device as claimed in claim 1 is characterized in that: described metal barrier is a kind of or its combination in titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), cobalt (Co), platinum (Pt), titanium tungsten (TiW), titanium nitride (TiN), the tantalum nitride (TaN).
9, semiconductor device as claimed in claim 1 is characterized in that: described metal seed layer is copper, aluminium, tungsten, gold or silver-colored.
10, semiconductor device as claimed in claim 1 is characterized in that: described interconnecting metal layer comprises copper or aluminium.
11, semiconductor device as claimed in claim 1 is characterized in that: described through hole is positioned at corresponding position, metal pattern top.
12, semiconductor device as claimed in claim 1 is characterized in that: the interconnecting metal layer in the described through hole is electrically connected with described metal pattern on the described substrate by described metal seed layer and metal barrier.
13, a kind of manufacture method of semiconductor device is characterized in that comprising:
Semi-conductive substrate is provided, on substrate, forms dielectric layer and metal pattern layer;
On described dielectric layer and metal pattern layer, form etching stop layer;
On described etching stop layer, form a barrier layer;
On described barrier layer, form middle dielectric layer;
The described middle dielectric layer of etching, barrier layer and etching stop layer form through hole exposing described metal pattern, and form groove at described middle dielectric layer;
In described groove and through hole, fill metal seed layer, metal barrier and interconnecting metal layer successively.
14, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that: the formation method on described etching stop layer and barrier layer comprises physical vapor deposition (PVD) or chemical vapor deposition (CVD).
15, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that: described chemical vapour deposition (CVD) comprises that aumospheric pressure cvd (APCVD), low-pressure chemical vapor deposition (LPCVD), gas ions strengthen chemical vapour deposition (CVD) (PE CVD), high density plasma CVD (HDPCVD).
16, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that: the thickness of described etching stop layer is 100 dusts～300 dusts.
17, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that: the thickness on described barrier layer is 200 dusts～600 dusts.
18, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that: the formation method of described middle dielectric layer comprises physical vapour deposition (PVD), chemical vapour deposition (CVD).
19, the manufacture method of semiconductor device as claimed in claim 13 is characterized in that: described metal barrier utilizes physical vapour deposition (PVD) or electro-plating method to form.
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