CN1388573A - Making process of metal intraconnection wire in semiconductor - Google Patents
Making process of metal intraconnection wire in semiconductor Download PDFInfo
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- CN1388573A CN1388573A CN 01116180 CN01116180A CN1388573A CN 1388573 A CN1388573 A CN 1388573A CN 01116180 CN01116180 CN 01116180 CN 01116180 A CN01116180 A CN 01116180A CN 1388573 A CN1388573 A CN 1388573A
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Abstract
The making process of metal intraconnection wire in semiconductor includes the following steps: providing one semiconductor substrate having conducting area with metal wires and holes; forming one metal Ti layer on the semiconductor substrate; forming one first TiN layer on the metal Ti layer via CVD course; and forming one second TiN layer on the first TiN layer via PVD course. The said process can ensure no oxidation of the first TiN layer and raise the reliability of the element.
Description
The invention relates to a kind of manufacture method of metal intraconnection wire in semiconductor, particularly relevant for a kind of after forming first titanium nitride layer with chemical vapour deposition technique (CVD), form second titanium nitride layer in addition with physical vaporous deposition (PVD) again, can oxidation not take place because of its unstable chemcial property to guarantee previous formed first titanium nitride layer.
Consult the method for Fig. 1-Fig. 5 for the formation internal connection-wire structure of conventional art.
Be illustrated in figure 1 as the source/drain (source/drain) of mixing N/P type ion at the semiconductor-based end 100, or be used for being used as the metal pattern of intraconnections (interconnects), formed conductive region 120; Next, comprehensive deposition one insulating barrier 140, this insulating barrier 140 is not limited to earth silicon material, also can utilize the organic or inorganic dielectric material of other low-ks to constitute; Then, with traditional micro-photographing process and the above-mentioned insulating barrier 140 of etching step selective etch, expose the contact hole 150 of above-mentioned conductive region 120 with formation; Then, utilize physics vapor phase deposition method (PVD) to form titanium coating 160.
Consult Fig. 2, next, after titanium coating 160 forms, on last titanium titanium coating 160, form titanium nitride layer 180 with CVD.
Consult Fig. 3, now in the comprehensive formation tungsten layer 200 of titanium nitride 180 laminar surfaces, and fills up contact hole.
At last, consult Fig. 4, carry out cmp processing procedure (CMP), and under suitable operating condition, carry out grinding steps, to remove the tungsten metal level 200 of insulating barrier 140 tops, and staying tungsten structure 200a in the contact hole 150, itself and titanium nitride layer 180a, titanium coating 160a constitute tungsten plug (PG) jointly.
Consult shown in Figure 5ly, it is the operating process generalized section of the formation internal connection-wire structure of conventional art, mixes the source/drain of N/P type ion at the semiconductor-based end 300, or is used for being used as the metal pattern of intraconnections, to form conductive region 320; Next, comprehensive deposition one insulating barrier 340, this insulating barrier 340 is not limited to earth silicon material, also can utilize the organic or inorganic dielectric material of other low-ks to constitute; Then, with traditional micro-photographing process and the above-mentioned insulating barrier 340 of etching step selective etch, expose the contact hole 350 of above-mentioned conductive region 320 with formation; Then, utilize physics vapor phase deposition method to form a titanium coating 360.
In above-mentioned conventional process, the reason that forms titanium nitride layer 180 with CVD is as follows: in formation tungsten layer 200, can import tungsten fluoride (WF usually
6) gas, if this moment, titanium nitride layer 180 did not cover titanium coating 160 fully, usually can be because import tungsten fluoride (WF
6) gas and chemical reactions take place with titanium coating 160, and then produce fluoride.The generation of fluoride will cause the volumetric expansion of titanium coating 160, and resistance improves.And relatively poor with the gradient coating performance of the formed titanium nitride layer of CVD, in the processing procedure below 0.18 μ m, usually in contact hole 150 bottoms and sidewall can't have enough thickness, so can't provide effective protection to titanium coating.And have preferable gradient coating performance with the formed titanium nitride layer of CVD, therefore, the processing procedure below 0.18 μ m normally forms titanium nitride layer with the CVD processing procedure.Titanium coating is provided the better protect effect.
Yet though above-mentioned have preferable gradient coating performance with the formed titanium nitride layer of CVD processing procedure, its chemical property is with the formed titanium nitride layer of PVD processing procedure, and is comparatively unstable.When therefore being exposed in the atmosphere with the formed titanium nitride layer of CVD processing procedure, with be easy to atmosphere in aqueous vapor reaction and oxidation and produces TiNO, and this situation will increase and more serious along with the time that exposes, and the impedance of titanium nitride layer will increase thereupon, up to reaching a saturation value.
Above-mentioned situation will be when semiconductor element be operated easier displaying, promptly element because electric current will produce a large amount of heat because of its high impedance, and cause the damage of semiconductor element by above-mentioned titanium nitride layer, reduces the reliability of product when operation.
Main purpose of the present invention is to provide a kind of manufacture method of metal intraconnection wire in semiconductor, by on titanium coating, forming after the titanium nitride layer with the CVD processing procedure, with the PVD processing procedure, on the previous formed titanium nitride layer of CVD processing procedure, cover the titanium nitride layer more in addition.Owing to have than stable chemical property with formed second titanium nitride layer of PVD processing procedure, with respect to the formed titanium nitride layer of CVD processing procedure, be difficult for taking place oxidation, and can avoid before being subjected to oxidation, reach the purpose of the reliability that improves element with the formed titanium nitride layer of CVD processing procedure.
The object of the present invention is achieved like this: a kind of manufacture method of metal intraconnection wire in semiconductor is characterized in that: it comprises the following steps:
(1) provide a semiconductor-based end that comprises conductive region, this conductive region has metal wire and hole;
(2) compliance ground forms a titanium coating on the surface at this semiconductor-based end;
(3) form first titanium nitride layer with chemical vapour deposition technique compliance ground on this titanium coating surface;
(4) form second titanium nitride layer with physical vaporous deposition compliance ground on this first titanium nitride layer surface.
Comprise all sidedly and form a silicon dioxide layer in this semiconductor-based basal surface.This conductive region comprises source/drain.
A kind of manufacture method of metal intraconnection wire in semiconductor is characterized in that: it comprises the following steps:
(1) provide a semiconductor-based end that comprises conductive region, this conductive region has metal wire and hole;
(2) form a titanium coating in the surperficial compliance ground of this conductor substrate;
(3) form first titanium nitride layer with chemical vapour deposition technique in compliance ground, above-mentioned titanium coating surface;
(4) form second titanium nitride layer with physical vaporous deposition in compliance ground, above-mentioned first titanium nitride layer surface;
(5), and fill up described hole in this comprehensive formation one tungsten layer in second titanium nitride layer surface.
More comprise all sidedly and form silicon dioxide layer in this semiconductor-based basal surface.This conductive region comprises source/drain.This tungsten layer is to use tungsten hexafluoride and silicomethane as reacting gas.It is reacting gas that this tungsten layer is to use tungsten hexafluoride and chlorine silicomethane.It is reacting gas that this tungsten layer is to use tungsten hexafluoride and hydrogen.
Major advantage of the present invention is the effect with the reliability that improves element.
Describe in detail below in conjunction with preferred embodiment and conjunction with figs..
Fig. 1 is the operating process generalized section of conventional art.
Fig. 2 is the subsequent step generalized section of figure.
Fig. 3 is the subsequent step generalized section of Fig. 2.
Fig. 4 is the subsequent step generalized section of Fig. 3.
Fig. 5 is the operating process generalized section that tradition forms internal connection-wire structure.
Fig. 6 is a subsequent step generalized section of the present invention.
Fig. 7 is the subsequent step generalized section of Fig. 6.
Fig. 8 is the subsequent step generalized section of Fig. 7.
Consult Fig. 6, after titanium coating 300 forms, on above-mentioned titanium coating 360, form titanium nitride layer 380 with CVD; Then, on above-mentioned titanium nitride layer 380, form second titanium nitride layer 400 in addition with PVD.Fully cover titanium nitride layer 380 with formed second titanium nitride layer 400 of PVD this moment, because its chemical property is stable than titanium nitride layer 380, therefore is not easy and the extraneous oxidation reaction that produces, and can avoid titanium nitride layer 380 that oxidation takes place simultaneously.
Consult Fig. 7, then,, and fill up contact hole 350 in second titanium nitride layer, 400 surperficial comprehensive formation tungsten layers 420.In the process that forms tungsten layer 420, with tungsten hexafluoride (WF
6) and silicomethane (SiH
4), or with tungsten hexafluoride (WF
6) and chlorine silicomethane (SiH
2Cl
2), or with tungsten hexafluoride (WF
6) and hydrogen (H
2) as reacting gas.
Consult Fig. 8, at last, carry out cmp processing procedure (CMP), and under suitable operating condition, carry out grinding steps, to remove the tungsten metal level 420 of insulating barrier 340 tops, and staying tungsten structure 420a in the contact hole 350, itself and titanium nitride layer 380a (being made of the titanium nitride layer 380 and second titanium nitride layer 400) and titanium coating 360u constitute tungsten plug (PG) jointly.
In sum; by the described method of the embodiment of the invention; at first form titanium nitride layer with good step coverage property with the CVD processing procedure; protect titanium coating; then, again with chemical property comparatively stable prevent the oxidation of previous formed titanium nitride layer with formed second titanium nitride layer of PVD processing procedure.Therefore, can in the processing procedure that forms barrier layer and intraconnections, avoid being subjected to oxidation at short notice, to overcome the ageing effect of CVD-TiN in the conventional art with the formed titanium nitride layer of CVD processing procedure.
In addition, in the scheduling of processing procedure, also can increase the standby time of allowing of semiconductor element after forming titanium nitride layer, and then promote processing procedure in the elasticity of adjusting in the running with the CVD processing procedure.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, change of being done and retouching all belong within protection scope of the present invention.
Claims (9)
1, a kind of manufacture method of metal intraconnection wire in semiconductor, it is characterized in that: it comprises the following steps:
(1) provide a semiconductor-based end that comprises conductive region, this conductive region has metal wire and hole;
(2) compliance ground forms a titanium coating on the surface at this semiconductor-based end;
(3) form first titanium nitride layer with chemical vapour deposition technique compliance ground on this titanium coating surface;
(4) form second titanium nitride layer with physical vaporous deposition compliance ground on this first titanium nitride layer surface.
2, the manufacture method of metal intraconnection wire in semiconductor as claimed in claim 1 is characterized in that: comprise all sidedly and form a silicon dioxide layer in this semiconductor-based basal surface.
3, the manufacture method of metal intraconnection wire in semiconductor as claimed in claim 2 is characterized in that: this conductive region comprises source/drain.
4, a kind of manufacture method of metal intraconnection wire in semiconductor, it is characterized in that: it comprises the following steps:
(1) provide a semiconductor-based end that comprises conductive region, this conductive region has metal wire and hole;
(2) form a titanium coating in the surperficial compliance ground of this conductor substrate;
(3) form first titanium nitride layer with chemical vapour deposition technique in compliance ground, above-mentioned titanium coating surface;
(4) form second titanium nitride layer with physical vaporous deposition in compliance ground, above-mentioned first titanium nitride layer surface;
(5), and fill up described hole in this comprehensive formation one tungsten layer in second titanium nitride layer surface.
5, the manufacture method of metal intraconnection wire in semiconductor as claimed in claim 4 is characterized in that: more comprise all sidedly in this semiconductor-based basal surface formation silicon dioxide layer.
6, the manufacture method of metal intraconnection wire in semiconductor as claimed in claim 4 is characterized in that: this conductive region comprises source/drain.
7, the manufacture method of metal intraconnection wire in semiconductor as claimed in claim 4 is characterized in that: this tungsten layer is to use tungsten hexafluoride and silicomethane as reacting gas.
8, the manufacture method of metal intraconnection wire in semiconductor as claimed in claim 4 is characterized in that: it is reacting gas that this tungsten layer is to use tungsten hexafluoride and chlorine silicomethane.
9, the manufacture method of metal intraconnection wire in semiconductor as claimed in claim 4 is characterized in that: it is reacting gas that this tungsten layer is to use tungsten hexafluoride and hydrogen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01116180 CN1388573A (en) | 2001-05-25 | 2001-05-25 | Making process of metal intraconnection wire in semiconductor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01116180 CN1388573A (en) | 2001-05-25 | 2001-05-25 | Making process of metal intraconnection wire in semiconductor |
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| CN 01116180 Pending CN1388573A (en) | 2001-05-25 | 2001-05-25 | Making process of metal intraconnection wire in semiconductor |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263031A (en) * | 2010-05-26 | 2011-11-30 | 上海宏力半导体制造有限公司 | Method for manufacturing trench vertical metal oxide semiconductor (VMOS) transistor |
| CN102412186A (en) * | 2011-03-08 | 2012-04-11 | 上海华虹Nec电子有限公司 | Manufacture method of through hole of large size |
| CN111029358A (en) * | 2019-12-26 | 2020-04-17 | 华虹半导体(无锡)有限公司 | CMOS image sensor and method of manufacturing the same |
| CN115433919A (en) * | 2022-09-29 | 2022-12-06 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
-
2001
- 2001-05-25 CN CN 01116180 patent/CN1388573A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263031A (en) * | 2010-05-26 | 2011-11-30 | 上海宏力半导体制造有限公司 | Method for manufacturing trench vertical metal oxide semiconductor (VMOS) transistor |
| CN102412186A (en) * | 2011-03-08 | 2012-04-11 | 上海华虹Nec电子有限公司 | Manufacture method of through hole of large size |
| CN111029358A (en) * | 2019-12-26 | 2020-04-17 | 华虹半导体(无锡)有限公司 | CMOS image sensor and method of manufacturing the same |
| CN115433919A (en) * | 2022-09-29 | 2022-12-06 | 长鑫存储技术有限公司 | Preparation method of semiconductor structure and semiconductor structure |
| CN115433919B (en) * | 2022-09-29 | 2024-01-12 | 长鑫存储技术有限公司 | Method for preparing semiconductor structure and semiconductor structure |
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