CN115433919B - Method for preparing semiconductor structure and semiconductor structure - Google Patents

Method for preparing semiconductor structure and semiconductor structure Download PDF

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Publication number
CN115433919B
CN115433919B CN202211199827.0A CN202211199827A CN115433919B CN 115433919 B CN115433919 B CN 115433919B CN 202211199827 A CN202211199827 A CN 202211199827A CN 115433919 B CN115433919 B CN 115433919B
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deposition process
deposition
metal layer
titanium metal
titanium
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CN115433919A (en
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刘曦光
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The disclosure provides a semiconductor structure, a method for manufacturing the semiconductor structure and the semiconductor structure, wherein the method for manufacturing the semiconductor structure comprises the following steps: providing a substrate, wherein the substrate comprises a semiconductor base and a dielectric layer arranged on the semiconductor base, and a contact hole exposing the semiconductor base is formed in the dielectric layer; depositing a titanium metal layer on the side wall of the contact hole in a chemical vapor deposition mode, wherein the titanium metal layer deposited by the first deposition process and the second deposition process completely covers the side wall of the contact hole; the process for depositing the titanium metal layer comprises a first deposition process and a second deposition process. By combining the first deposition process and the second deposition process, a titanium metal layer which completely covers the side wall of the contact hole can be formed, so that the use amount of titanium nitride is effectively reduced, or the use of titanium nitride is avoided, and the resistance of the contact structure is obviously reduced.

Description

Method for preparing semiconductor structure and semiconductor structure
Technical Field
The disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for manufacturing the same.
Background
With the rapid development of semiconductor memory technology, in order to cope with more complex demands, there is a need to continuously increase the element density of dynamic random access memories (Dynamic Random Access Memory, abbreviated as DRAMs). Shrinking the linewidth of semiconductor fabrication processes is an effective way to increase device density.
In order to conduct between each region in the semiconductor device and the external circuit, respectively, it is often necessary to prepare a contact structure, such as a contact structure between the peripheral circuit and the semiconductor substrate, or the like. The contact structure should have the effect of adhering to the conductive structure to be subsequently prepared and blocking the penetration of the components of the conductive structure into the semiconductor substrate. Common contact structures typically include a titanium metal layer and a titanium nitride layer. Wherein the separate titanium metal layer is not easily covered on the side wall in the preparation process, so that the side wall has partially exposed areas, gaps exist between the exposed areas and the conductive structure which is prepared later, or components of the conductive structure diffuse into the areas to cause damage. It is therefore also desirable to prepare a titanium nitride layer that, by the combined action of the titanium nitride layer and the titanium metal layer, provides an effective adhesion and barrier for the contact structure. However, the resistance of the titanium nitride layer is significantly higher than that of the titanium metal layer, and the arrangement of the titanium metal layer and the titanium nitride layer can cause the resistance of the contact structure to be significantly increased, thereby significantly affecting the performance of the semiconductor device.
Disclosure of Invention
Based on this, in order to secure adhesion and barrier capability of the contact structure while reducing the resistance of the contact structure, it is necessary to provide a method for manufacturing a semiconductor structure.
According to some embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor structure, comprising the steps of:
providing a substrate, wherein the substrate comprises a semiconductor base and a dielectric layer arranged on the semiconductor base, and a contact hole exposing the semiconductor base is formed in the dielectric layer;
depositing a titanium metal layer on the side wall of the contact hole in a chemical vapor deposition mode, wherein the process of depositing the titanium metal layer comprises a first deposition process and a second deposition process, and the titanium metal layer deposited by the first deposition process and the second deposition process completely covers the side wall of the contact hole; the gas raw materials in the first deposition process and the second deposition process comprise titanium source gas and hydrogen, the flow rate of the hydrogen in the deposition raw materials in the first deposition process is more than 60%, and the flow rate of the hydrogen in the deposition raw materials in the second deposition process is less than or equal to 50%.
In some embodiments of the present disclosure, in the second deposition process, the hydrogen gas is present in the deposition feedstock at a flow rate of 10% or less.
In some embodiments of the present disclosure, the gas feedstock in the second deposition process further comprises a protective gas, wherein in the second deposition process, the gas flow rate of the titanium source gas is 10sccm to 20sccm, and the gas flow rate of the hydrogen gas is 20sccm to 200sccm.
In some embodiments of the present disclosure, the gas raw material in the first deposition process further includes a protective gas, and in the first deposition process, the gas flow rate of the titanium source gas is 5sccm to 10sccm, and the gas flow rate of the hydrogen gas is 2000sccm to 6000sccm.
In some embodiments of the present disclosure, the deposition power is 500W to 1000W in the first deposition process, and the deposition power is 800W to 1500W in the second deposition process.
In some embodiments of the present disclosure, the first deposition process and the second deposition process are performed in the same deposition chamber.
In some embodiments of the present disclosure, the material of the semiconductor substrate includes silicon, and further including a step of forming a conductive alloy between the titanium metal layer located at the bottom of the contact hole and the semiconductor substrate after the first deposition process.
In some embodiments of the present disclosure, the titanium source gas comprises a titanium halide.
In some embodiments of the present disclosure, after the first deposition process, the method further comprises the step of purging and removing residual deposition raw materials from the surface of the titanium metal layer deposited by the first deposition process.
In some embodiments of the present disclosure, after the second deposition process, the method further comprises the step of purging the surface of the titanium metal layer deposited by the second deposition process and removing residual deposition raw material
In some of the embodiments of the present disclosure, after depositing the titanium metal layer, further comprising: and preparing a conductive plug which contacts the titanium metal layer on the titanium metal layer, wherein the conductive plug and the titanium metal layer fill up the contact hole.
In some embodiments of the present disclosure, the conductive plug material includes one or more of tungsten, copper, aluminum, and cobalt.
In some embodiments of the present disclosure, the process of depositing the titanium metal layer includes a plurality of the first deposition processes.
In some embodiments of the present disclosure, the depositing the titanium metal layer includes a plurality of the second deposition processes.
In some embodiments of the disclosure, in the process of depositing the titanium metal layer, a total deposition time of the first deposition process is 5s to 30s; the total deposition time of the second deposition process is 5 s-120 s.
According to still further embodiments of the present disclosure, there is provided a semiconductor structure, comprising:
the semiconductor device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a semiconductor base and a dielectric layer arranged on the semiconductor base, and a contact hole exposing the semiconductor base is formed in the dielectric layer; the method comprises the steps of,
and the titanium metal layer completely covers the side wall of the contact hole.
In some embodiments of the present disclosure, the material of the semiconductor substrate comprises silicon and the material of the dielectric layer comprises silicon oxide.
In some embodiments of the present disclosure, the titanium metal layer on the sidewall of the contact hole has a thickness of 2nm to 15nm.
In some embodiments of the disclosure, a conductive plug is further included, the conductive plug is disposed in the contact hole, and the conductive plug contacts the titanium metal layer.
In some embodiments of the present disclosure, the conductive plug material includes one or more of tungsten, copper, aluminum, and cobalt.
The preparation method of the semiconductor structure comprises the step of depositing the titanium metal layer on the side wall of the contact hole in a chemical vapor deposition mode, and the titanium metal layer completely covers the side wall of the contact hole through a process comprising a first deposition process and a second deposition process. The flow rate of the hydrogen in the first deposition process is relatively high, and in the first deposition process, titanium atoms can be rapidly deposited on the upper section of the side wall of the contact hole, which is close to the opening. In the second deposition process, titanium atoms are deposited more in the middle section and the lower section of the side wall of the contact hole, which are far away from the opening. By combining the first deposition process and the second deposition process, the hole filling capability of titanium atoms in the contact holes can be improved under the condition of ensuring the overall preparation efficiency of the titanium metal layer, so that the titanium metal layer completely covering the side walls of the contact holes is formed. The titanium metal layer completely covering the side wall of the contact hole can play the roles of effective adhesion and blocking, so that the use amount of titanium nitride can be effectively reduced or the use of titanium nitride can be avoided, and the resistance of the contact structure can be obviously reduced.
The foregoing description is only an overview of the technical solutions of the present disclosure, and in order to make the technical means of the present disclosure more clearly understood, it can be implemented according to the content of the specification, and the following detailed description is given with reference to the preferred embodiments of the present disclosure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and that other embodiments of the drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram illustrating steps of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a substrate used to fabricate a semiconductor structure;
FIG. 3 is a schematic view of the structure of FIG. 2 after deposition of a first titanium metal portion;
FIG. 4 is a schematic illustration of the structure of FIG. 3 after deposition of a second titanium metal portion;
FIG. 5 is a schematic diagram of the structure of FIG. 4 after the conductive plugs are formed;
wherein, each reference sign and meaning are as follows:
110. a semiconductor substrate; 120. a dielectric layer; 121. a contact hole; 210. a titanium metal layer; 211. a first titanium metal portion; 212. a second titanium metal part; 220. an electrical contact layer; 230. and a conductive plug.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. The manner of electrical connection is used to indicate that electrical current may be conducted between a plurality of elements that are electrically connected, either by one element directly contacting another element or by one element being connected to another element by another electrically conductive element. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
The present disclosure provides a method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate, wherein the substrate comprises a semiconductor base and a dielectric layer arranged on the semiconductor base, and a contact hole exposing the semiconductor base is formed in the dielectric layer;
depositing a titanium metal layer on the side wall of the contact hole in a chemical vapor deposition mode, wherein the titanium metal layer deposited by the first deposition process and the second deposition process completely covers the side wall of the contact hole; the process for depositing the titanium metal layer comprises a first deposition process and a second deposition process; the gas raw materials in the first deposition process and the second deposition process comprise titanium source gas and hydrogen, the flow rate of the hydrogen in the deposition raw materials in the first deposition process is more than 60%, and the flow rate of the hydrogen in the deposition raw materials in the second deposition process is less than or equal to 50%.
It is understood that the first deposition process and the second deposition process each include a titanium source gas and hydrogen gas for reducing the titanium source gas to produce metallic titanium. Therefore, the first deposition process and the second deposition process can both deposit metallic titanium on the side wall of the contact hole, and the metallic titanium deposited by the first deposition process and the second deposition process jointly participate in forming a titanium metal layer which completely covers the side wall of the contact hole.
Titanium metal and titanium nitride are commonly used in the conventional art as adhesion layers and diffusion barriers between the semiconductor substrate and the conductive structure. The technical conception of the preparation method of the above embodiment of the present disclosure is as follows: a titanium metal layer completely covering the dielectric layer is used as an adhesion layer and a diffusion barrier layer to reduce the amount of titanium nitride as much as possible or to avoid the introduction of a titanium nitride layer. The resistance of the titanium metal layer is significantly lower than that of the titanium nitride layer, and thus the method of fabricating the semiconductor structure can be used to reduce the resistance of the contact structure.
It will be appreciated that the above technical concept is not adopted in the conventional art, mainly because it is difficult to prepare a titanium metal layer completely covering the sidewall of the contact hole in the contact hole during the actual preparation process. The researchers of the present disclosure have found through a number of inventive experiments that the hydrogen flow rate in the first deposition process, in which titanium atoms can be rapidly deposited on the upper section of the sidewall of the contact hole near the opening, is relatively high. In the second deposition process, titanium atoms are deposited more in the middle section and the lower section of the side wall of the contact hole, which are far away from the opening. By combining the first deposition process and the second deposition process, the hole filling capability of titanium atoms in the contact holes can be improved under the condition of ensuring the overall preparation efficiency of the titanium metal layer, so that the titanium metal layer completely covering the side walls of the contact holes is formed.
In order to facilitate understanding of the method for fabricating a semiconductor structure described above, reference is made to fig. 1, which illustrates an embodiment of a method for fabricating a semiconductor structure, including steps S1 to S3.
Step S1, providing a substrate comprising a semiconductor base and a dielectric layer, wherein a contact hole exposing the semiconductor base is formed in the dielectric layer.
Referring to fig. 2, a schematic structural diagram of a substrate including a semiconductor base 110 and a dielectric layer 120 is shown. The dielectric layer 120 is disposed on the semiconductor substrate 110, and a contact hole exposing the semiconductor substrate 110 is disposed in the dielectric layer 120.
It is understood that the semiconductor substrate 110 refers to a semiconductor feature having a particular functional structure, which may include semiconductors and other non-semiconductor materials that participate in forming the feature. The dielectric layer 120 is disposed on the semiconductor substrate 110, and optionally, the dielectric layer 120 is made of an insulating material. The dielectric layer 120 is provided with a contact hole 121 exposing the semiconductor substrate 110, other components to be disposed on the substrate can be electrically connected to the semiconductor substrate 110 exposed in the contact hole 121, and the dielectric layer 120 is used for insulating the semiconductor substrate 110 from the components in other regions.
In some examples of this embodiment, the material of semiconductor substrate 110 comprises silicon and the material of dielectric layer 120 comprises silicon oxide. The silicon oxide has insulation property, and the silicon oxide is used as the material of the dielectric layer 120, so that the short circuit between the silicon material below the dielectric layer 120 and the subsequent components arranged above the dielectric layer 120 can be effectively prevented.
In some examples of this embodiment, the dielectric layer 120 may be disposed on the semiconductor substrate 110 by chemical vapor deposition. Alternatively, in preparing the dielectric layer 120, the semiconductor substrate 110 may be placed in a deposition chamber, and a silicon source gas and an oxygen source gas are introduced to react to obtain the dielectric layer 120 including a silicon oxide material on the semiconductor substrate 110. In other examples of this embodiment, the silicon material on the surface layer of the semiconductor substrate 110 may also be directly subjected to a heat treatment in an oxidizing atmosphere to obtain the dielectric layer 120 including silicon oxide.
In some examples of this embodiment, the manner in which the contact hole 121 exposing the semiconductor substrate 110 is opened in the dielectric layer 120 may be etching. Optionally, the dielectric layer 120 is etched in a manner selected from dry etching. For example, in the dry etching process, an etching gas with a relatively high etching selectivity to the dielectric layer 120 is selected to etch the dielectric layer 120. The etching gas etches the dielectric layer 120 at a faster rate and etches the semiconductor substrate 110 at a slower rate, so that the process of etching the contact hole 121 does not substantially damage the semiconductor substrate 110.
The exposed portion of the semiconductor substrate 110 of the contact hole 121 is used for electrical connection to a component disposed subsequently, and electrical connection between the semiconductor substrate 110 and other components is required through a contact structure, so that the contact structure is required to be disposed in the contact hole 121. The conventional contact structure generally includes a conductive plug, however, in the process of preparing the conductive plug, the material used for preparing the conductive plug or the material used for preparing the conductive plug may contaminate the dielectric layer 120 and the semiconductor substrate 110, and thus, it is also necessary to prepare a material having adsorption and diffusion barrier effects in the contact hole 121.
In step S2, a titanium metal layer 210 is deposited on the sidewalls of the contact holes 121 to completely cover the sidewalls of the contact holes 121.
The process of depositing the titanium metal layer 210 includes a first deposition process and a second deposition process. The gas feed in both the first deposition process and the second deposition process comprises a titanium source gas and hydrogen gas.
Among them, it is understood that in the first deposition process and the second deposition process, the titanium source gas is selected from materials capable of being reduced by hydrogen gas, and metallic titanium atoms can be generated by reacting the titanium source gas with the hydrogen gas.
In some examples of this embodiment, the titanium source gas comprises a titanium halide. Alternatively, the titanium halide may be selected from one or more of titanium chloride, titanium bromide and titanium iodide. For example, the titanium halide is titanium tetrachloride (TiCl 4 )。
The titanium source gas in the first deposition process and the second deposition process may be different or the same. For example, the titanium source gases in the first deposition process and the second deposition process may each be independently selected from one or more of titanium chloride, titanium bromide, and titanium iodide. In some examples of this embodiment, the titanium source gas in the first deposition process and the second deposition process are the same to simplify the raw materials required for the process of the titanium metal layer 210. Optionally, the titanium source gas in both the first deposition process and the second deposition process is titanium tetrachloride.
In some examples of this embodiment, a protective gas may also be included in the first deposition process and the second deposition process. The protective gas can form plasma on one hand, is used for participating in the reaction process of converting titanium source gas into titanium atoms, and on the other hand, is also used for adjusting the hydrogen ratio in the first deposition process and the second deposition process so as to control the deposition area of the titanium atoms. Optionally, the first deposition process and the second deposition process use the same type of gaseous feedstock.
In some examples of this embodiment, the first deposition process and the second deposition process may be performed in the same deposition chamber. Conventional contact structures include a titanium metal layer 210 and a titanium nitride layer, which require two deposition chambers and a deposition source formulation to complete the fabrication. The first deposition process and the second deposition process are arranged in the same deposition chamber, compared with the traditional contact structure, the preparation process is simpler, and the required deposition chamber and the deposition raw material formula can be obviously simplified.
In the process of the titanium metal layer 210, the first deposition process may be performed first, and then the second deposition process may be performed, or the second deposition process may be performed first, and then the first deposition process may be performed. In addition, the process of depositing the titanium metal layer 210 may include a plurality of first deposition processes, and the second deposition process and the plurality of first deposition processes may be alternately performed. The process of depositing the titanium metal layer 210 may also include a plurality of second deposition processes, alternating between the first deposition process and the plurality of second deposition processes.
In some examples of this embodiment, the process of the titanium metal layer 210 includes a first deposition process and a second deposition process, and the first deposition process is performed before the second deposition process is performed. Correspondingly, step S2 includes steps S2.1 and S2.2 as shown below.
In step S2.1, a first titanium metal portion 211 is deposited on the sidewall of the contact hole 121 by a first deposition process.
The gas raw materials of the first deposition process comprise titanium source gas and hydrogen, and the flow rate of the hydrogen in the gas raw materials is more than 60%. Optionally, other auxiliary gases, such as a protective gas, for adjusting the flow ratio of the hydrogen gas may be included in the gas feed.
Referring to fig. 3, the first titanium metal portion 211 formed by controlling the flow rate of hydrogen in the gas raw material to be more than 60% is mainly concentrated on the upper portion of the dielectric layer 120 and the top section of the sidewall of the contact hole 121 away from the bottom of the hole, and is difficult to deposit on the middle portion and the bottom end portion of the sidewall of the contact hole 121.
In some examples of this embodiment, in the first deposition process, the gas flow rate of the titanium source gas is 5sccm to 10sccm and the gas flow rate of the hydrogen gas is 2000sccm to 6000sccm. The gas flow rates of the protective gas may be set correspondingly according to the gas flow rates of the hydrogen gas and the titanium source gas so that the flow rate of the hydrogen gas in the gas raw material is more than 60%.
Alternatively, the gas flow rate of the titanium source gas is 5sccm, 6ccm, 7sccm, 8sccm, 9sccm, 10sccm, or a range between any two of the gas flows.
Alternatively, the hydrogen gas has a gas flow rate of 2000sccm, 2500ccm, 3000sccm, 3500sccm, 4000sccm, 5000sccm, 6000sccm, or a range between any two of these gas flows.
In some examples of this embodiment, the protective gas has a gas flow rate of 1000sccm to 3000sccm. The gas flow rate of the protective gas can be correspondingly adjusted according to the flow rate ratio of the hydrogen.
In some examples of this embodiment, the gas feed for the first deposition process further comprises a protective gas selected from gases that do not react with the semiconductor substrate 110 and the titanium metal, such as an inert gas. Optionally, the protective gas comprises argon.
In some examples of this embodiment, the titanium source gas in the first deposition process is selected from titanium tetrachloride.
In some examples of this embodiment, the deposition power is 500W to 1000W in the first deposition process. For example, in the first deposition process, the deposition power is 500W, 600W, 700W, 800W, 900W, 1000W, or ranges between the deposition powers therein.
In some examples of this embodiment, the deposition time is controlled to be 5s to 30s in the first deposition process. By controlling the deposition time, the first titanium metal portions 211 with a relatively proper thickness are deposited on part of the sidewalls of the top section of the contact hole 121, so as to perform an effective adhesion and blocking function, and the contact holes 121 for preparing the subsequent conductive plugs 230 are still exposed between the deposited first titanium metal portions 211.
In some examples of this embodiment, after the first deposition process, a step of forming a conductive alloy between the titanium layer at the bottom of the contact hole and the semiconductor substrate at the bottom of the contact hole is further included.
Referring to fig. 3, in step S2.1, deposited titanium atoms are also deposited on the dielectric layer 120 and at the bottom of the contact hole 121 at the same time. In some examples of this embodiment, the material of the semiconductor substrate 110 includes silicon, and the deposited titanium atoms on the semiconductor substrate 110 are also capable of reacting with silicon to form titanium silicide (TiSi x ) Titanium silicide has better conductivity and can be used as an electrical contact structure between the semiconductor substrate 110 and the conductive plugs 230 to be subsequently prepared.
In order to obtain higher preparation efficiency of the titanium metal layer 210 in the conventional technology, a process similar to step S2.1 is generally used to prepare titanium metal, so that the prepared titanium metal is difficult to completely cover the side wall of the contact hole 121, which makes the single titanium metal layer 210 incapable of playing an effective role in adhesion and blocking. A titanium nitride layer is further formed on the titanium metal layer 210 to completely cover the sidewalls of the contact hole 121. In order to solve the problems existing in the conventional art, the embodiment of the present disclosure further provides step S2.2 to overcome the problem that the deposited titanium metal cannot completely cover the sidewalls of the contact hole 121.
It is understood that in other embodiments, the first deposition process may be performed multiple times, and the first titanium metal portion 211 is formed with a higher coverage rate and a higher coverage thickness at the top portion of the sidewall of the contact hole 121 after the multiple first deposition processes are performed.
In step S2.2, a second titanium metal portion 212 is deposited on the sidewall of the contact hole 121 by a second deposition process.
The gas raw materials of the second deposition process comprise titanium source gas and hydrogen, and the flow rate of the hydrogen in the gas raw materials is less than or equal to 50%. Optionally, other auxiliary gases, such as a protective gas, for adjusting the flow ratio of the hydrogen gas may be included in the gas feed.
Referring to fig. 4, the titanium metal deposited by the second deposition process is a second titanium metal portion 212. Controlling the flow rate of hydrogen in the gas raw material to be equal to or less than 50% enables the second titanium metal portion 212 to extend along the first titanium metal portion 211 and to be attached to the middle and bottom section portions of the side wall of the contact hole 121 near the hole bottom. The second titanium metal portion 212 and the first titanium metal portion 211 together constitute a titanium metal layer 210 that completely covers the sidewalls of the contact hole 121.
In some examples of this embodiment, the gas flow rate of the titanium source gas is 5sccm to 50sccm and the gas flow rate of the hydrogen gas is 10sccm to 500sccm in the second deposition process. The gas flow rates of the auxiliary gas can be correspondingly set according to the gas flow rates of the hydrogen gas and the titanium source gas, so that the flow rate of the hydrogen gas in the gas raw material is less than or equal to 50%.
Alternatively, the gas flow rate of the titanium source gas is 5sccm, 12ccm, 25sccm, 36sccm, 40sccm, 50sccm, or a range between any two of the gas flows.
Alternatively, the gas flow rate of hydrogen is 10sccm, 40sccm, 120sccm, 250ccm, 400sccm, 500sccm, or a range between any two of the gas flows.
In some examples of this embodiment, the gas feed for the second deposition process further comprises a protective gas having a gas flow rate of 1000sccm to 3000sccm. The gas flow rate of the protective gas can be correspondingly adjusted according to the flow rate ratio of the hydrogen.
In some examples of this embodiment, the protective gas is selected from gases that do not react with the semiconductor substrate 110 and the titanium metal, such as inert gases. Optionally, the protective gas comprises argon.
In some examples of this embodiment, the titanium source gas in the second deposition process is selected from titanium tetrachloride.
In some examples of this embodiment, the deposition power is 800W to 1500W in the second deposition process. For example, in a first deposition process, the deposition power is 800W, 900W, 1000W, 1200W, 1400W, 1500W, or ranges between deposition powers therein. Optionally, the deposition power of the second deposition process is higher than the deposition power of the first deposition process. For example, the power of the first deposition process is 800W and the power of the second deposition process is 1200W.
In some examples of this embodiment, the deposition time is controlled to be 5s to 120s in the second deposition process. By controlling the deposition time, the second titanium metal portion 212 with a relatively proper thickness is deposited on the side walls of the middle section and the bottom section of the contact hole 121, so that the titanium metal layer 210 has an effective adhesion and blocking function as a whole.
In some examples of this embodiment, the deposition time of the second deposition process is greater than the deposition time of the first deposition process.
In some examples of this embodiment, the thickness of the titanium metal layer 210 on the sidewalls of the contact holes 121 is 5nm to 15nm. By controlling the thickness of the titanium metal layer 210 on the sidewall to be 2 nm-15 nm, the titanium metal layer 210 can have a more excellent blocking effect, and the pollution of the dielectric layer 120 and the semiconductor base layer by the conductive plug 230 which is prepared later can be fully avoided.
Wherein the first titanium metal portion 211 may cover a top section portion of the sidewall of the contact hole 121, and the second titanium metal portion 212 may further cover a middle section portion and a bottom section portion of the sidewall of the contact hole 121. The top section portion of the side wall of the contact hole 121 refers to a portion spaced apart from the bottom wall of the contact hole 121. The top section of the sidewall of the contact hole 121 may be in the upper half of the sidewall of the contact hole 121. The middle and bottom sections of the sidewall of the contact hole 121 refer to the sidewalls other than the top section, and the sidewall of the bottom section is connected to the bottom wall of the contact hole 121. By the combination of the first titanium metal portion 211 and the second titanium metal portion 212, the formed titanium metal layer 210 can be sufficiently covered onto the side wall of the contact hole 121.
It is understood that in other embodiments, the second deposition process may be performed multiple times, and the second titanium metal portion 212 is formed to have a higher coverage rate and coverage thickness in the middle and bottom portions of the sidewall of the contact hole 121 after the second deposition process is performed multiple times.
In step S3, the conductive plugs 230 contacting the titanium metal layer 210 are prepared in the contact holes 121.
Referring to fig. 5, a conductive plug 230 is disposed in the contact hole 121, a titanium metal layer 210 is disposed between a sidewall of the contact hole 121 and the conductive plug 230, and the conductive plug 230 contacts the titanium metal layer 210.
In some examples of this embodiment, conductive plugs 230 also have portions disposed on dielectric layer 120 to facilitate electrical connection to components to be connected.
In some examples of this embodiment, the material of the conductive plug 230 includes one or more of tungsten, copper, aluminum, and cobalt.
In some examples of this embodiment, the manner in which conductive plugs 230 are prepared is selected from chemical vapor deposition. Alternatively, the conductive plugs 230 are prepared by plasma enhanced chemical vapor deposition.
In some examples of this embodiment, the material of conductive plugs 230 includes tungsten, and correspondingly, the gas source for depositing conductive plugs 230 includes tungsten hexafluoride and hydrogen. Optionally, the gaseous materials for depositing conductive plugs 230 may also include tungsten hexafluoride and methane.
It will be appreciated that the conductive plugs 230 prepared in this step are used to electrically connect the semiconductor substrate 110 to other components, such as peripheral circuitry to which the semiconductor structure is to be connected.
The preparation of the titanium metal layer 210 and the conductive plugs 230 in the contact holes 121 on the substrate in the semiconductor structure can be completed through steps S1 to S3. Wherein, since the first deposition process and the second deposition process are adopted in the process of preparing the titanium metal layer 210, efficient hole filling of titanium metal in the contact hole 121 is realized, so that the prepared titanium metal layer 210 completely covers the side wall of the contact hole 121.
In the conventional art, the contact structure disposed on the semiconductor substrate 110 generally includes both the titanium metal layer 210 and the titanium nitride layer, and good adhesion and barrier effects are obtained by the co-action of the titanium metal layer 210 and the titanium nitride layer. In the semiconductor structure of this embodiment, the titanium metal layer 210 is disposed between the semiconductor substrate 110 and the conductive plug 230 without disposing the titanium nitride layer, and the titanium metal layer 210 completely covers the sidewall of the contact hole 121, so that the resistance of the contact structure can be reduced while effective adhesion and blocking are performed.
Yet another embodiment of the present disclosure also provides a semiconductor structure, the semiconductor structure in this embodiment being as shown in fig. 5. The semiconductor structure includes: a substrate, the substrate comprises a semiconductor base 110 and a dielectric layer 120 arranged on the semiconductor base 110, and a contact hole 121 exposing the semiconductor base 110 is formed in the dielectric layer 120; and a titanium metal layer 210, the titanium metal layer 210 completely covering the sidewalls of the contact hole 121.
In some examples of this embodiment, the material of semiconductor substrate 110 comprises silicon and the material of dielectric layer 120 comprises silicon oxide.
In some examples of this embodiment, the thickness of the titanium metal layer 210 on the sidewalls of the contact holes 121 is 5nm to 15nm.
In some examples of this embodiment, the semiconductor structure further includes a conductive plug 230, the conductive plug 230 is disposed in the contact hole 121, and the conductive plug 230 contacts the titanium metal layer 210. Optionally, the material of the conductive plugs 230 includes one or more of tungsten, copper, aluminum, and cobalt.
The preparation method of the titanium metal layer 210 in the semiconductor structure may refer to step S2 in the above embodiment, and the preparation method of the conductive plug 230 may refer to step S3.
The method for preparing the semiconductor structure may refer to the method for preparing the semiconductor structure shown in the above embodiment.
Further, the semiconductor substrate in the semiconductor structure provided by the present disclosure may be electrically connected to other conductive components through the conductive plugs.
In another aspect, the present disclosure also provides a memory device including a functional circuit and the semiconductor structure of the above embodiment. The functional circuit is electrically connected to the semiconductor substrate in the semiconductor structure. In some examples of this embodiment, the semiconductor structure further includes a conductive plug through which the functional circuit is electrically connected to the semiconductor substrate.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
It should be understood that the steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps of a step may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor does the order in which the sub-steps or stages are performed necessarily occur in sequence, but may be performed alternately or alternately with at least a portion of the sub-steps or stages of other steps or other steps.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

Claims (18)

1. A method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate, wherein the substrate comprises a semiconductor base and a dielectric layer arranged on the semiconductor base, and a contact hole exposing the semiconductor base is formed in the dielectric layer;
depositing a titanium metal layer on the side wall of the contact hole in a chemical vapor deposition mode, wherein the process of depositing the titanium metal layer comprises a first deposition process and a second deposition process, and the titanium metal layer deposited by the first deposition process and the second deposition process completely covers the side wall of the contact hole; the gas raw materials in the first deposition process and the second deposition process comprise titanium source gas and hydrogen, the flow rate of the hydrogen in the deposition raw materials in the first deposition process is more than 60%, and the flow rate of the hydrogen in the deposition raw materials in the second deposition process is less than or equal to 50%.
2. The method of claim 1, wherein the hydrogen flow rate in the deposition source material in the second deposition process is 10% or less.
3. The method according to claim 1, wherein the gas source in the second deposition process further comprises a protective gas, and wherein the gas flow rate of the titanium source gas is 10sccm to 20sccm and the gas flow rate of the hydrogen gas is 20sccm to 200sccm in the second deposition process.
4. The method according to claim 1, wherein the gas source in the first deposition process further comprises a protective gas, and wherein the gas flow rate of the titanium source gas is 5sccm to 10sccm and the gas flow rate of the hydrogen gas is 2000sccm to 6000sccm in the first deposition process.
5. The method of claim 1, wherein in the first deposition process, the deposition power is 500W to 1000W, and in the second deposition process, the deposition power is 800W to 1500W.
6. The method of claim 1, wherein the first deposition process and the second deposition process are performed in a same deposition chamber.
7. The method of any one of claims 1 to 6, wherein the material of the semiconductor substrate comprises silicon, and further comprising the step of forming a conductive alloy between the titanium metal layer at the bottom of the contact hole and the semiconductor substrate after the first deposition process.
8. The method of manufacturing a semiconductor structure according to any one of claims 1 to 6, wherein the titanium source gas comprises titanium halide.
9. The method of fabricating a semiconductor structure according to any one of claims 1 to 6, further comprising the steps of purging the surface of the titanium metal layer deposited by the first deposition process and removing residual deposition raw material after the first deposition process; and/or
After the second deposition process, the method further comprises the steps of purging and removing residual deposition raw materials from the surface of the titanium metal layer deposited by the second deposition process.
10. The method of manufacturing a semiconductor structure according to any one of claims 1 to 6, further comprising, after depositing the titanium metal layer: and preparing a conductive plug which contacts the titanium metal layer on the titanium metal layer, wherein the conductive plug and the titanium metal layer fill up the contact hole.
11. The method of claim 10, wherein the conductive plugs comprise one or more of tungsten, copper, aluminum, and cobalt.
12. The method of any one of claims 1-6 and 11, wherein the depositing the titanium metal layer comprises a plurality of first deposition processes; and/or the number of the groups of groups,
the process of depositing the titanium metal layer comprises a plurality of second deposition processes.
13. The method of claim 12, wherein in the depositing the titanium metal layer, a total deposition time of the first deposition process is 5s to 30s; the total deposition time of the second deposition process is 5 s-120 s.
14. A semiconductor structure prepared by the method of any one of claims 1 to 13.
15. The semiconductor structure of claim 14, wherein the material of the semiconductor substrate comprises silicon and the material of the dielectric layer comprises silicon oxide.
16. The semiconductor structure of claim 14, wherein the titanium metal layer on the sidewalls of the contact hole has a thickness of 2nm to 15nm.
17. The semiconductor structure of any one of claims 14-16, further comprising a conductive plug disposed in the contact hole, the conductive plug contacting the titanium metal layer.
18. The semiconductor structure of claim 17, wherein the conductive plug material comprises one or more of tungsten, copper, aluminum, and cobalt.
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CN101312152A (en) * 2007-05-23 2008-11-26 中芯国际集成电路制造(上海)有限公司 Bit line contact forming method
CN102024747A (en) * 2009-09-11 2011-04-20 中芯国际集成电路制造(上海)有限公司 Method for manufacturing aluminium plug of power device
CN104157562A (en) * 2014-08-26 2014-11-19 上海华虹宏力半导体制造有限公司 Method for forming semiconductor structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1388573A (en) * 2001-05-25 2003-01-01 矽统科技股份有限公司 Making process of metal intraconnection wire in semiconductor
TW200426984A (en) * 2003-05-22 2004-12-01 Taiwan Semiconductor Mfg Method for fabricating conductive plug and semiconductor device
CN101312152A (en) * 2007-05-23 2008-11-26 中芯国际集成电路制造(上海)有限公司 Bit line contact forming method
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