CN102254839B - The outer simple and easy integrated approach of a kind of ic core and framework - Google Patents

The outer simple and easy integrated approach of a kind of ic core and framework Download PDF

Info

Publication number
CN102254839B
CN102254839B CN201010180158.3A CN201010180158A CN102254839B CN 102254839 B CN102254839 B CN 102254839B CN 201010180158 A CN201010180158 A CN 201010180158A CN 102254839 B CN102254839 B CN 102254839B
Authority
CN
China
Prior art keywords
pin
end point
connection end
chip
base plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201010180158.3A
Other languages
Chinese (zh)
Other versions
CN102254839A (en
Inventor
刘圣平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN201010180158.3A priority Critical patent/CN102254839B/en
Publication of CN102254839A publication Critical patent/CN102254839A/en
Application granted granted Critical
Publication of CN102254839B publication Critical patent/CN102254839B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Credit Cards Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention relates to the outer simple and easy integrated approach of a kind of ic core and framework, outside its core, simple and easy integrated approach mainly: by access bridge and base plate in the non-standard framework of layout uniqueness, or utilize base plate in standard card cage, as bridge transfer transition, to on chip, some needs to merge connection but isolated end points (bond pad), crossing over wire (line) is connected on a certain suitable pin or access bridge or base plate, realize merging to connect, or the enforcement of unsettled leap wire (line) merges connection in the middle of chip.The beneficial effect that the present invention produces is: easily IC chip circuits many for pin position is simply integrated into the few new integrated circuit in pin position again, resource in former chip circuit is made to be recombinated or optimize or expand, save the great number cost that the simple new integrated circuit of development small lot takes, shorten the construction cycle of new integrated circuit, be badly in need of with quick customer in response.

Description

The outer simple and easy integrated approach of a kind of ic core and framework
Technical field
The present invention relates to a kind of integrated circuit (IC) manufacture method, particularly the outer simple and easy integrated approach of the core implemented before packaging of a kind of IC chip, can save the simple new integrated circuit (IC) of development small lot pay great number cost.
Background technology
Existing method for manufacturing integrated circuit is generally almost all first be integrated in by circuit in one piece of silicon chip, then it is inner to frame pin silicon wafer circuitry exit wire to be connected (side is fixed), finally forms with encapsulating material encapsulation.This manufacture method, although integrated level is high, encapsulation is easily, very high to cost needed for the development of the simple new integrated circuit of small lot, and only having silicon chip factory can integrated novel circuit, encapsulation factory normally can not again change or recombinate or expand former IC chip circuit function.
Summary of the invention
Can not to the again integrated technical problem of former chip circuit when the present invention mainly solves ic chip package, there is provided a kind of and also can implement the outer simple and easy integrated method of core when encapsulating, to recombinate resource in former chip circuit, or change or expanded circuit function, reduce former integrated circuit volume (or reduce former integrated circuit taken up space), shorten the new lsi development cycle, save the simple new integrated circuit institute of development small lot and pay great number cost, design urgent need to meet application fast.
The present invention is as follows for solving the problems of the technologies described above taked technical scheme (method):
(1) the non-standard framework of the layout uniqueness that design is different from standard, wherein base plate and pin, or between pin and pin, have access bridge to intert wherein, to wire (line) rise the same with base plate of access bridge passes through transfer transitional function, do not draw outside encapsulation, as embodiment 1, 2, non-standard framework used in 3, wherein there are four pins 5, 6, 7, 8 side by side in the straight long limit of base plate 10, there are symmetrical two access bridges 11 on other three limits of base plate 10, 12 is adjoint, at access bridge 11, two pins 2 is had again outside 12, 3 whole process are held up with both hands, at two pins 2, two pins 1 is had again outside 3, 4 is omnidistance with escorting, base plate 10 can be applicable to simultaneously paste IC chip 9 and discrete electronic device, pin, some loose position on access bridge, also be just in time applicable to pasting discrete electronic device or simple chip, pin, access bridge, backplane placement, easy adaptation wire is freely direct or cross over connection, wire is avoided to cross in the middle of chip,
(2) utilize embodiment 1,2,3 non-standard frameworks used, some end points (bond pad) for circumferentially-spaced on discrete device and chip 9 needs to merge draws, be with wire directly or cross a certain suitable pin or access bridge and merge and connect; Two or more end points (bond pad) for circumferentially-spaced on chip need merge but do not draw, with wire directly or cross over and be connected on a certain suitable access bridge or base plate; For the line on chip and discrete device, can directly connect or indirect utilization pin, access bridge, base plate transition connect;
(3) utilize embodiment 4,5,6 standard card cages used, connect the end points (bond pad) merged on IC chip 9, realize core outer simple and easy integrated, its concrete grammar is, for adjacent side on chip or opposite side some end points (bond pad) needing merging to connect isolated, be connected to certain same pin from the leap of IC chip 9 middle convenience with wire, realize great-leap-forward and merge connection; For on chip with on one side isolated some need the end points (bond pad) that merges, with wire directly or cross over and be connected on certain same pin, realize merging and connect; For the end points (bond pad) that some needs of circumferentially-spaced on chip merge, be first separately connected on base plate 10 with wire nearby, then be connected to a certain pin with wire from base plate 10, utilize base plate to make terminal, realize passing through merging connection; For some key discrete device or companion chip in application circuit, be first pasted onto the position that base plate or pin or access bridge are suitable, then connect with wire.
The beneficial effect that the present invention produces is: easily by the external end points of IC chip circuit (bond pad) many for pin position, again merge integrated before packaging, become the new integrated circuit that pin position is few, circuit resource in former chip is made to be recombinated or expand, easily make former chip become one and have the new integrated circuit that New function or function are slightly complicated, reduce former integrated circuit volume (or reduce former integrated circuit taken up space), shorten the new lsi development cycle, save the simple new integrated circuit of development small lot pay great number cost, be badly in need of to meet application design fast.
Accompanying drawing explanation
Fig. 1 is the concrete wiring connection layout of the embodiment of the present invention 1.
Fig. 2 is the concrete wiring connection layout of the embodiment of the present invention 2.
Fig. 3 is the concrete wiring connection layout of the embodiment of the present invention 3.
Fig. 4 is the concrete wiring connection layout of the embodiment of the present invention 4.
Fig. 5 is the concrete wiring connection layout of the embodiment of the present invention 5.
Fig. 6 is the concrete wiring connection layout of the embodiment of the present invention 6.
In figure: 1 ~ 8 is pin in framework, 9 is integrated circuit (IC) chip, the a of its surrounding, b, c, d, e, f, g, h, j, k, l, m, n is external connection end point (bond pad), 10 for placing the base plate of IC chip 9 in framework, 11 is left access bridge in framework, 12 is right access bridge in framework, 13 is package material, D1, D2 is voltage stabilizing didoe, D3, D4 is diode, R, R1, R2 is resistance, on discrete device and chip 9, each end points (bond pad) a ~ n is to pin 1 ~ 8, access bridge 11, 12, on base plate 10, connecting lead wire is the good wire of conduction.Fig. 1,2,3 frameworks used are non-standard framework; Fig. 4,5,6 frameworks used are standard card cage.
Embodiment
Below by embodiment, and by reference to the accompanying drawings, technical scheme of the present invention (method) is further described in detail:
Embodiment 1 to 6, as shown in figs. 1 to 6, in figure: 1 ~ 8 is pin in framework, 9 is integrated circuit (IC) chip, the a of its surrounding, b, c, d, e, f, g, h, j, k, l, m, n is external connection end point (bond pad), 10 for placing the base plate of IC chip 9 in framework, 11 is left access bridge in framework, 12 is right access bridge in framework, 13 is package material, D1, D2 is voltage stabilizing didoe, D3, D4 is diode, R, R1, R2 is resistance, on discrete device and chip 9, each end points (bond pad) a ~ n is to pin 1 ~ 8, access bridge 11, 12, on base plate 10, connecting lead wire is the good wire of conduction.Fig. 1,2,3 frameworks used are non-standard framework; Fig. 4,5,6 frameworks used are standard card cage.
Embodiment 1:
The technical scheme (non-standard framework is to the integrated approach of IC chip) that the present embodiment is taked, as shown in Figure 1, E class 14 pin chip insulating cement is pasted on the position that in described new frame, base plate 10 is suitable, voltage stabilizing didoe D1 positive pole conducting resinl is pasted on base plate 10 upper left corner, D1 negative pole wire is connected to pin 1, voltage stabilizing didoe D2 negative pole conducting resinl is pasted on base plate 10 upper right corner, voltage stabilizing didoe D2 positive pole wire is connected to pin 4, the two ends of resistance R1 (or equivalence element), direct welding (or paste) is in pin 2 and the suitable position of access bridge 11, the two ends of resistance R2 (or equivalence element) are directly welded (or stickup) in pin 3 and the suitable position of access bridge 12, pin 1 ~ 8 in framework, access bridge 11, 12, between base plate 10 to chip upper extreme point (bond pad) a ~ n by the scheme (method) of wire connecting wiring be: pin 1 connection end point c, pin 2 connection end point b, g, pin 3 connection end point i, m, pin 4 connection end point 1, pin 5 connects access bridge 12 connection end point h again, k, pin 6 connection end point n, pin 7 connection end point a, pin 8 connects access bridge 11 connection end point e again, f, base plate 10 connection end point d, j, through above-mentioned leap wiry or directly connect, achieve as required to merge to the non-conterminous pad in some interval on IC chip and connect, and line does not intersect not from the middle leap of chip yet, reach the object to the outer simple and easy integration packaging of IC core.
Embodiment 2:
The technical scheme (non-standard framework is to the integrated approach of IC chip) that the present embodiment is taked, as shown in Figure 2, category-A 14 pin chip insulating cement is pasted on the position that in described new frame, base plate 10 is suitable, voltage stabilizing didoe D1 positive pole conducting resinl is pasted on base plate 10 upper left corner, voltage stabilizing didoe D1 negative pole wire is connected to pin 1, voltage stabilizing didoe D2 negative pole conducting resinl is pasted on base plate 10 upper right corner, voltage stabilizing didoe D2 positive pole wire is connected to pin 4, the two ends of resistance R1 (or equivalence element), direct welding (or paste) is in pin 2 and the suitable position of access bridge 11, the two ends of resistance R2 (or equivalence element) are directly welded (or stickup) in pin 3 and the suitable position of access bridge 12, pin 1 ~ 8 in framework, access bridge 11, 12, between base plate 10 to chip 9 upper extreme point (bond pad) a ~ n by the scheme (method) of wire connecting wiring be: pin 1 connection end point d, pin 2 connection end point c, g, pin 3 connection end point h, l, pin 4 connection end point k, pin 5 connection end point m and access bridge 12 connection end point j again, pin 6 connection end point n, pin 7 connection end point a, pin 8 connection end point b and access bridge 11 connection end point e again, base plate 10 connection end point f, i, through above-mentioned leap wiry or directly connect, achieve as required to merge to the end points (bond pad) of some interval (non-conterminous) on IC chip 9 and connect, and line does not intersect not from the middle leap of chip 9 yet, reach the object to the outer simple and easy integration packaging of IC core.
Embodiment 3:
The technical scheme (non-standard framework is to the integrated approach of IC chip) that the present embodiment is taked, as shown in Figure 3, category-A 14 pin chip insulating cement is pasted on the position that in described new frame, base plate 10 is suitable, voltage stabilizing didoe D1 positive pole conducting resinl is pasted on base plate 10 upper left corner, voltage stabilizing didoe D1 negative pole wire is connected to pin 1, voltage stabilizing didoe D2 negative pole conducting resinl is pasted on base plate 10 upper right corner, voltage stabilizing didoe D2 positive pole wire is connected to pin 4, diode D3 negative pole conducting resinl is pasted on access bridge 11, diode D3 positive pole wire is connected to pin 2, diode D4 negative pole conducting resinl is pasted on access bridge 12, diode D4 positive pole wire is connected to pin 3, the two ends of resistance R1 (or equivalence element), direct welding (or stickup) is between pin 7 and 8, (or stickup) is directly welded between pin 5 and 6 in the two ends of resistance R2 (or equivalence element), pin 1 ~ 8 in framework, access bridge 11, 12, between base plate 10 to chip 9 upper extreme point (bond pad) a ~ n by the scheme (method) of wire connecting wiring be: pin 1 connection end point d, pin 2 connection end point e, g, pin 3 connection end point h, j, pin 4 connection end point k, pin 5 connects access bridge 12 connection end point i again, 1, pin 6 connection end point n, pin 7 connection end point a, pin 8 connects access bridge 11 connection end point c again, f, base plate 10 connection end point b, m, through above-mentioned leap wiry or directly connect, achieve as required to merge to the end points (bond pad) of some interval (non-conterminous) on IC chip 9 and connect, and line does not intersect not from the middle leap of chip 9 yet, reach the object to the outer simple and easy integration packaging of IC core.
Embodiment 4:
The technical scheme (standard card cage is to the integrated approach of IC chip) that the present embodiment is taked, as shown in Figure 4, S class 14 pin chip insulating cement is pasted on the position that in existing 8 footnote collimator frames, base plate 10 is suitable, the two ends of resistance R (or equivalence element), direct welding (or stickup) is between pin 8 and base plate 10, pin 1 ~ 8 in framework, between base plate 10 to chip 9 upper extreme point (bond pad) a ~ n by the scheme (method) of wire connecting wiring be: pin 1 is connection end point b and base plate 10 respectively, pin 2 connection end point c, pin 3 connection end point e, pin 4 connection end point g, pin 5 is connection end point h and base plate 10 respectively, pin 6 connection end point i, j, pin 7 connection end point m, pin 8 connection end point n, base plate 10 goes back connection end point d, f, l, through above-mentioned with leap wiry or directly connect, achieve as required to merge to the end points (bond pad) of some interval (non-conterminous) on IC chip 9 and connect, and line does not intersect, base plate 10 is particularly utilized to pass through transfer in chip 91, d, f, b, ingenious the achieving of h five end points (bond pad) merges connection, successfully reach the object to the outer simple and easy integration packaging of IC core.
Embodiment 5:
The technical scheme (standard card cage is to the integrated approach of IC chip) that the present embodiment is taked, as shown in Figure 5, S class 14 pin chip insulating cement is pasted on the position that in existing 8 footnote collimator frames, base plate 10 is suitable, the two ends of resistance R (or equivalence element), direct welding (or stickup) is between pin 6 and 7, pin 1 ~ 8 in framework, between base plate 10 to chip 9 upper extreme point (bond pad) a ~ n by the scheme (method) of wire connecting wiring be: pin 1 connection end point e, pin 2 is connection end point f and base plate 10 respectively, pin 3 connection end point g, pin 4 connection end point i, pin 5 connection end point k, pin 6 connection end point n, pin 7 is connection end point b and pin 8 respectively, pin 8 is connection end point d again, l, base plate 10 goes back connection end point h, j, wherein, end points l crosses over line on opposite side and end points d and is connected to pin 8 in the middle of IC chip 9, pin 7 is in parallel with 8 is to strengthen external circuit connection reliability, end points h, j utilizes base plate 10 and line transfer to be transitioned into pin 2 and realizes merging with end points f and be connected, successfully reach the object to the outer simple and easy integration packaging of IC core.
Embodiment 6:
The technical scheme (standard card cage is to the integrated approach of IC chip) that the present embodiment is taked, as shown in Figure 6, E class 14 pin chip insulating cement is pasted on the position that in existing 8 footnote collimator frames, base plate 10 is suitable, resistance R1 (or equivalence element) welding (or stickup) is between pin 1 and access bridge 10, resistance R2 (or equivalence element) welding (or stickup) is between pin 4 and access bridge 10, pin 1 ~ 8, access bridge 11, 12, between base plate 10 to chip 9 upper extreme point (bond pad) a ~ n by the scheme (method) of wire connecting wiring be: pin 1 connection end point e, f, pin 2 connecting bottom board 10 and end points g, pin 3 connection end point d, h, pin 4 connection end point i, j, pin 5 connection end point 1, pin 6 connection end point m, pin 7 connection end point a, pin 8 connection end point c, base plate 10 connection end point b, k, n, wherein, chip 9 upper terminal d and h is distributed on two adjacent limits, unsettled leap wire connection end point h and pin 3 in the middle of chip 9, realize terminal d with h be connected merge, b on chip 9, n, k, g tetra-terminals utilize base plate 10 connection merging to be wired on pin 2 again, thus reach the object of the outer simple and easy integration packaging of core.

Claims (7)

1. the non-standard framework that the outer simple and easy integrated approach of ic core is used, is characterized in that:
(1) wherein pin 1 ~ 8, access bridge 11 and 12, base plate 10 is in packaging body 13, access bridge 11 interval is had between described base plate 10 and pin 2, access bridge 12 interval is had between described base plate 10 and pin 3, access bridge 11 and 12 interval is had between pin 1 ~ 4 and pin 5 ~ 8, pin 1 ~ 4 and pin 5 ~ 8 point two row stretch out outside packaging body 13, access bridge 11, 12 and base plate 10 do not draw outside packaging body 13, direct or the unsettled leap of wire is connected to pin, access bridge and base plate, pin 5 ~ 8 is side by side in the straight long limit of base plate 10, there are symmetrical two access bridges 11 on the other both sides adjacent with straight long limit of base plate 10, 12 is adjoint, at access bridge 11, two pins 2 is had outside 12, 3 hold up with both hands, at pin 2, pin 1 is had outside 3, 4 is omnidistance with escorting, base plate 10 can paste IC chip 9 and discrete electronic device chip simultaneously,
(2) in the IC chip 9 surrounding end points a ~ n pasted on non-standard chassis base 10, two or more end points at interval need merging to draw, that direct or unsettled a certain pin or the access bridge of crossing merges and connect with wire, two or more end points for interval in IC chip 9 surrounding end points a ~ n need to merge but do not draw, with wire, direct or unsettled leap is connected on a certain access bridge or base plate, for the line on IC chip 9 and discrete electronic device chip, can directly connect or indirect utilization pin, access bridge, base plate transition connect.
2. the method for attachment of the non-standard framework that the outer simple and easy integrated approach of a kind of ic core according to claim 1 is used: wherein, described IC chip 9 is E class 14 pin chip 9, E class 14 pin chip 9 insulating cement is pasted among the base plate 10 of framework, voltage stabilizing didoe D1 positive pole conducting resinl is pasted on base plate 10 upper left corner, the unsettled leap of voltage stabilizing didoe D1 negative pole wire is connected to pin 1, voltage stabilizing didoe D2 negative pole conducting resinl is pasted on base plate 10 upper right corner, the unsettled leap of voltage stabilizing didoe D2 positive pole wire is connected to pin 4, the two ends of resistance R1 or equivalence element are directly welded or are pasted onto between pin 2 and access bridge 11, the two ends of resistance R2 or equivalence element are directly welded or are pasted onto between pin 3 and access bridge 12, the pin 1 ~ 8 of framework, access bridge 11 and 12, be pin 1 connection end point c with the pass of wire connecting wiring between end points a ~ n in base plate 10 to chip 9, pin 2 connection end point b, g, pin 3 connection end point i, m, pin 4 connection end point l, pin 5 connects access bridge 12 again by access bridge 12 connection end point h, k, pin 6 connection end point n, pin 7 connection end point a, pin 8 connects access bridge 11 again by access bridge 11 connection end point e, f, base plate 10 connection end point d, j, through above-mentioned unsettled leap wiry or directly connect, achieve as required to merge to the non-conterminous end points in some interval on E class 14 pin chip 9 and connect, and line does not intersect not from the middle unsettled leap of chip 9 yet.
3. the method for attachment of the non-standard framework that the outer simple and easy integrated approach of a kind of ic core according to claim 1 is used: wherein, described IC chip 9 is category-A 14 pin chip 9, category-A 14 pin chip 9 is pasted among chassis base 10 with insulating cement, voltage stabilizing didoe D1 positive pole conducting resinl is pasted on base plate 10 upper left corner, voltage stabilizing didoe D1 negative pole wire is connected to pin 1, voltage stabilizing didoe D2 negative pole conducting resinl is pasted on base plate 10 upper right corner, voltage stabilizing didoe D2 positive pole wire is connected to pin 4, the two ends of resistance R1 or equivalence element are directly welded or are pasted onto between pin 2 and access bridge 11, the two ends of resistance R2 or equivalence element, direct welding or be pasted onto between pin 3 and access bridge 12, the pin 1 ~ 8 of framework, access bridge 11 and 12, be pin 1 connection end point d with the pass of wire connecting wiring between end points a ~ n in base plate 10 to chip 9, pin 2 connection end point c, g, pin 3 connection end point h, l, pin 4 connection end point k, pin 5 connection end point m and access bridge 12, again by access bridge 12 connection end point j, pin 6 connection end point n, pin 7 connection end point a, pin 8 connection end point b and access bridge 11, again by access bridge 11 connection end point e, base plate 10 connection end point f, i, through above-mentioned unsettled leap wiry or directly connect, achieve as required to merge to the non-conterminous end points in some interval on category-A 14 pin chip 9 and connect, and line does not intersect not from the middle unsettled leap of chip 9 yet.
4. the method for attachment of the non-standard framework that the outer simple and easy integrated approach of a kind of ic core according to claim 1 is used: wherein, described IC chip 9 is category-A 14 pin chip 9, category-A 14 pin chip 9 insulating cement is pasted among the base plate 10 of framework, voltage stabilizing didoe D1 positive pole conducting resinl is pasted on base plate 10 upper left corner, voltage stabilizing didoe D1 negative pole wire is connected to pin 1, voltage stabilizing didoe D2 negative pole conducting resinl is pasted on base plate 10 upper right corner, voltage stabilizing didoe D2 positive pole wire is connected to pin 4, diode D3 negative pole conducting resinl is pasted on access bridge 11, diode D3 positive pole wire is connected to pin 2, diode D4 negative pole conducting resinl is pasted on access bridge 12, diode D4 positive pole wire is connected to pin 3, the two ends of resistance R1 or equivalence element are directly welded or are pasted onto between pin 7 and pin 8, the two ends of resistance R2 or equivalence element are directly welded or are pasted onto between pin 5 and pin 6, the pin 1 ~ 8 of framework, access bridge 11 and 12, be pin 1 connection end point d with the pass of wire connecting wiring between end points a ~ n in base plate 10 to chip 9, pin 2 connection end point e, g, pin 3 connection end point h, j, pin 4 connection end point k, pin 5 connects access bridge 12, again by access bridge 12 connection end point i, l, pin 6 connection end point n, pin 7 connection end point a, pin 8 connects access bridge 11, again by access bridge 11 connection end point c, f, base plate 10 connection end point b, m, through above-mentioned unsettled leap wiry or directly connect, achieve as required to merge to the non-conterminous end points in some interval on category-A 14 pin chip 9 and connect, and line does not intersect not from the middle unsettled leap of chip 9 yet.
5. the outer simple and easy integrated approach of ic core, for the connection between IC chip 9 and standard card cage, it is characterized in that: described IC chip 9 is S class 14 pin chip 9, S class 14 pin chip 9 insulating cement is pasted among the base plate 10 of 8 footnote collimator frames, the two ends of resistance R or equivalence element are directly welded or are pasted onto between pin 8 and base plate 10, the pin 1 ~ 8 of framework, be pin 1 respectively connection end point b and base plate 10 with the pass of wire connecting wiring between end points a ~ n in base plate 10 to chip 9, pin 2 connection end point c, pin 3 connection end point e, pin 4 connection end point g, pin 5 is connection end point h and base plate 10 respectively, pin 6 connection end point i, j, pin 7 connection end point m, pin 8 connection end point n, base plate 10 goes back connection end point d, f, l, through above-mentioned with leap wiry or directly connect, to five end points l in S class 14 pin chip 9, d, f, b, h utilizes base plate 10 to pass through transfer and achieves merging connection, and line does not intersect.
6. the outer simple and easy integrated approach of ic core according to claim 5, it is characterized in that: wherein, described IC chip 9 is S class 14 pin chip 9, S class 14 pin chip 9 insulating cement is pasted among the base plate 10 of 8 footnote collimator frames, the two ends of resistance R or equivalence element, direct welding or be pasted onto between pin 6 and pin 7, the pin 1 ~ 8 of framework, be pin 1 connection end point e with the pass of wire connecting wiring between end points a ~ n in base plate 10 to chip 9, pin 2 is connection end point f and base plate 10 respectively, pin 3 connection end point g, pin 4 connection end point i, pin 5 connection end point k, pin 6 connection end point n, pin 7 is connection end point b and pin 8 respectively, pin 8 is connection end point d again, l, base plate 10 goes back connection end point h, j, wherein, end points l is unsettled in the middle of the chip 9 to be crossed the another side relative with limit, end points 1 place and is connected to pin 8, it is to strengthen external circuit connection reliability that pin 7 is connected with pin 8, end points h, j utilizes base plate 10 and line transfer to be transitioned into pin 2, thus realize being connected with end points f and merge.
7. the outer simple and easy integrated approach of ic core according to claim 5, it is characterized in that: wherein, described IC chip 9 is E class 14 pin chip 9, E class 14 pin chip 9 insulating cement is pasted among the base plate 10 of 8 footnote collimator frames, resistance R1 or equivalence element weld or are pasted onto between pin 1 and base plate 10, resistance R2 or equivalence element weld or are pasted onto between pin 4 and base plate 10, pin 1 ~ 8, be pin 1 connection end point e with the pass of wire connecting wiring between end points a ~ n in base plate 10 to chip 9, f, pin 2 connecting bottom board 10 and end points g, pin 3 is connected to end points d spaced apart on two adjacent edges of chip 9, h, wherein, end points d connects pin 3 by wire unsettled leap in the middle of chip 9, realize end points d and be connected merging with end points h, pin 4 connection end point i, j, pin 5 connection end point l, pin 6 connection end point m, pin 7 connection end point a, pin 8 connection end point c, base plate 10 goes back connection end point b, k, n, thus, four end points b in chip 9, n, k, g utilizes base plate 10 to connect merging to be wired on pin 2 again.
CN201010180158.3A 2010-05-21 2010-05-21 The outer simple and easy integrated approach of a kind of ic core and framework Expired - Fee Related CN102254839B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201010180158.3A CN102254839B (en) 2010-05-21 2010-05-21 The outer simple and easy integrated approach of a kind of ic core and framework

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201010180158.3A CN102254839B (en) 2010-05-21 2010-05-21 The outer simple and easy integrated approach of a kind of ic core and framework

Publications (2)

Publication Number Publication Date
CN102254839A CN102254839A (en) 2011-11-23
CN102254839B true CN102254839B (en) 2015-09-02

Family

ID=44982008

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201010180158.3A Expired - Fee Related CN102254839B (en) 2010-05-21 2010-05-21 The outer simple and easy integrated approach of a kind of ic core and framework

Country Status (1)

Country Link
CN (1) CN102254839B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7214050B2 (en) * 2020-05-19 2023-01-27 三菱電機株式会社 semiconductor module
WO2023272450A1 (en) * 2021-06-28 2023-01-05 欧菲光集团股份有限公司 Chip packaging structure, camera module, and electronic device
CN115632038A (en) * 2022-12-22 2023-01-20 紫光同芯微电子有限公司 Chip packaging structure and method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0018489A2 (en) * 1979-05-07 1980-11-12 International Business Machines Corporation A module for an array of integrated circuit chips, accomodating discretionary fly wire connections
EP0083406A2 (en) * 1981-12-31 1983-07-13 International Business Machines Corporation Module for supporting electrical components
EP0070861B1 (en) * 1981-01-16 1986-08-13 Mosaic Systems, Inc. Wafer and method of testing networks thereon
JPH0380548A (en) * 1989-05-15 1991-04-05 Toshiba Corp Semiconductor device
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
US6498391B1 (en) * 1999-04-12 2002-12-24 Siliconware Precision Industries Co., Ltd. Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same
CN2854807Y (en) * 2004-12-09 2007-01-03 晨星半导体股份有限公司 Integral circuit device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0018489A2 (en) * 1979-05-07 1980-11-12 International Business Machines Corporation A module for an array of integrated circuit chips, accomodating discretionary fly wire connections
EP0070861B1 (en) * 1981-01-16 1986-08-13 Mosaic Systems, Inc. Wafer and method of testing networks thereon
EP0083406A2 (en) * 1981-12-31 1983-07-13 International Business Machines Corporation Module for supporting electrical components
JPH0380548A (en) * 1989-05-15 1991-04-05 Toshiba Corp Semiconductor device
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
US6498391B1 (en) * 1999-04-12 2002-12-24 Siliconware Precision Industries Co., Ltd. Dual-chip integrated circuit package with unaligned chip arrangement and method of manufacturing the same
CN2854807Y (en) * 2004-12-09 2007-01-03 晨星半导体股份有限公司 Integral circuit device

Also Published As

Publication number Publication date
CN102254839A (en) 2011-11-23

Similar Documents

Publication Publication Date Title
CN102254839B (en) The outer simple and easy integrated approach of a kind of ic core and framework
CN103117263A (en) Integrated circuit package
CN204706557U (en) A kind of Intelligent Power Module
CN102222660B (en) Double-lead-frame multi-chip common packaging body and manufacturing method thereof
CN203553129U (en) Integrated circuit package with anti-shock function
CN206312942U (en) A kind of single-chip Hall current sensor
CN203276862U (en) Storage chip and storage equipment
CN202585395U (en) DIP (Dual inline-pin Package) lead frame structure
CN206274510U (en) A kind of five pin IC structures
CN106324484B (en) The wireless debug circuit and method of chip
CN206370421U (en) It is a kind of to be easy to fixed lead frame, semiconductor devices and setting tool
CN203536411U (en) Semiconductor packaging structure
CN103441107B (en) Semiconductor package assembly and a manufacturing method thereof
CN105633058B (en) Device identification structure and its manufacturing method
CN106558570B (en) Flip chip encapsulation
CN201946589U (en) Improved lead frame
CN205920965U (en) Lead frame with high bonding strength
CN103996628A (en) Method for manufacturing double-lead-frame multi-chip common packaging body
CN204958379U (en) Single carrier chip package spare of level MEMS of system
CN206639795U (en) A kind of integrated circuit package structure
CN201302995Y (en) Lead wire frame structure for integrated circuit with double loading plates
CN202694759U (en) Chip structure of liquid crystal drive control circuit
CN203276861U (en) Storage chip and storage equipment
CN203103284U (en) TSOP (Thin Small Outline Package) memory device
CN203118933U (en) Memory chip with singular number of pins

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C53 Correction of patent of invention or patent application
CB02 Change of applicant information

Address after: 315400 Zhejiang city in Yuyao Province, Lan Jiang Jie Dao Tan Jia Ling Cun TA Shan Miao East Building 1, No. 1 B11

Applicant after: Liu Shengping

Address before: Wu p a village in Hubei province Wuxue City Xianglong road 435400 No. 3 building 152 room one one unit

Applicant before: Liu Shengping

COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 435400 HUANGGANG, HUBEI PROVINCE TO: 315400 NINGBO, ZHEJIANG PROVINCE

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150902

Termination date: 20190521