CN206639795U - A kind of integrated circuit package structure - Google Patents
A kind of integrated circuit package structure Download PDFInfo
- Publication number
- CN206639795U CN206639795U CN201720279059.8U CN201720279059U CN206639795U CN 206639795 U CN206639795 U CN 206639795U CN 201720279059 U CN201720279059 U CN 201720279059U CN 206639795 U CN206639795 U CN 206639795U
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- pin
- interfaces
- connection
- chip
- integrated circuit
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Abstract
Integrated circuit fields are the utility model is related to, more particularly to a kind of integrated circuit package structure.The integrated circuit package structure, including chip, multiple pins, packaging part, the both sides for the chip that the multiple pin is arranged in order, the multiple pin corresponds to multiple interfaces of chip respectively, the packaging part is connected to around chip, position correspondence setting signal output interface of the chip according to packaging part.Integrated circuit structure of the present utility model can set output interface signal according to the position correspondence of outer connecting element so that interface signal can be set nearby, avoid the connecting lead wire of complex designing, and connection is simple, reduces production and R＆D costs.
Description
Technical field
Integrated circuit fields are the utility model is related to, more particularly to a kind of integrated circuit package structure.
Background technology
Existing integrated circuit has all fixed in circuit design untill the function of each interface on circuit,
Each interface is corresponded when being connected with outer member, but when the link position of outer member and interface changes, is then needed
Want the lead between docking port and outer member to do rearrangement, easily the layout on circuit board is caused confusion, and lead
Trend to redesign, the research and development of raising and production cost.
Utility model content
The utility model provides a kind of integrated circuit package structure, it is intended to which solving existing surface-mounted integrated circuit can not be according to outside
Element optimally selection signal interface.
The utility model provides a kind of integrated circuit package structure, including chip, multiple pins, packaging part, the multiple
The both sides for the chip that pin is arranged in order, the multiple pin correspond to multiple interfaces of chip respectively, and the packaging part is connected to
Around chip, position correspondence setting signal output interface of the chip according to packaging part.
As further improvement of the utility model, the chip is provided with 8 interfaces, and accordingly the encapsulating structure is provided with 8
Individual pin, the first pin connection VDD interfaces, the second pin connection VPP interfaces, three-prong, the 4th pin connection PA interfaces, the
Five pins connect PB or PD interfaces, the 6th pin, the 7th pin connection PWM interfaces, the 8th pin connection VSS interfaces.
As further improvement of the utility model, the chip is provided with 16 interfaces, and accordingly the encapsulating structure is provided with
16 pins, the first pin, the 6th pin, the 7th pin, the 8th pin connection PA interfaces, the second pin, the 11st pin connect
Connect VDD interfaces, the 5th pin connection VDDL interfaces, three-prong connection VPP interfaces, the 4th pin connection NC interfaces, the 9th pipe
Pin, the tenth pin, the 15th pin, the 16th pin, the 12nd pin, the tenth three-prong connection PWM interfaces, the 14th pin
Connect VSS interfaces.
As further improvement of the utility model, the chip is provided with 16 interfaces, and accordingly the encapsulating structure is provided with
16 pins, the first pin, the 4th pin, the 5th pin, the 6th pin connection PA interfaces, the second pin, the 11st pin connect
Connect VDD interfaces, the 7th pin connection VDDL interfaces, three-prong connection VPP interfaces, the 8th pin, the 15th pin, the 16th
Pin connects PC interfaces, the 9th pin, the tenth pin connection PD interfaces, and the 12nd pin, the tenth three-prong connect PWM interfaces,
14th pin connects VSS interfaces.
The beneficial effects of the utility model are：Integrated circuit structure of the present utility model can according to outer connecting element
Position correspondence sets output interface signal so that interface signal can be set nearby, avoid the connecting lead wire of complex designing, even
Connect simply, reduce production and R＆D costs.
Brief description of the drawings
Fig. 1 is a kind of first structure figure of integrated circuit package structure of the utility model；
Fig. 2 is a kind of the second structure chart of integrated circuit package structure of the utility model；
Fig. 3 is a kind of the 3rd structure chart of integrated circuit package structure of the utility model.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation
Example, the utility model is further elaborated.
A kind of integrated circuit package structure of the present utility model, including chip, multiple pins, packaging part, the multiple pipe
The both sides for the chip that pin is arranged in order, the multiple pin correspond to multiple interfaces of chip respectively, and the packaging part is connected to core
Around piece, position correspondence setting signal output interface of the chip according to packaging part.
Embodiment one：
As shown in figure 1, chip is provided with 8 interfaces, accordingly the encapsulating structure is provided with 8 pins, the first pin connection VDD
Interface, the second pin connection VPP interfaces, three-prong, the 4th pin connection PA interfaces, the 5th pin connection PB or PD interfaces,
6th pin, the 7th pin connection PWM interfaces, the 8th pin connection VSS interfaces.
Embodiment two：
As shown in Fig. 2 chip is provided with 16 interfaces, accordingly the encapsulating structure is provided with 16 pins, the first pin, the 6th
Pin, the 7th pin, the 8th pin connection PA interfaces, the second pin, the 11st pin connection VDD interfaces, the connection of the 5th pin
VDDL interfaces, three-prong connection VPP interfaces, the 4th pin connection NC interfaces, the 9th pin, the tenth pin, the 15th pin,
16th pin, the 12nd pin, the tenth three-prong connection PWM interfaces, the 14th pin connection VSS interfaces.
Embodiment three：
As shown in figure 3, chip is provided with 16 interfaces, accordingly the encapsulating structure is provided with 16 pins, the first pin, the 4th
Pin, the 5th pin, the 6th pin connection PA interfaces, the second pin, the 11st pin connection VDD interfaces, the connection of the 7th pin
VDDL interfaces, three-prong connection VPP interfaces, the 8th pin, the 15th pin, the 16th pin connection PC interfaces, the 9th pipe
Pin, the tenth pin connection PD interfaces, the 12nd pin, the tenth three-prong connection PWM interfaces, the 14th pin connection VSS interfaces.
Above content is to combine specific preferred embodiment further detailed description of the utility model, it is impossible to
Assert that specific implementation of the present utility model is confined to these explanations.For the ordinary skill of the utility model art
For personnel, without departing from the concept of the premise utility, some simple deduction or replace can also be made, should all be regarded
To belong to the scope of protection of the utility model.
Claims (4)
- A kind of 1. integrated circuit package structure, it is characterised in that including chip, multiple pins, packaging part, the multiple pin according to The both sides of the chip of secondary arrangement, the multiple pin correspond to multiple interfaces of chip respectively, and the packaging part is connected to chip Around, position correspondence setting signal output interface of the chip according to packaging part.
- 2. integrated circuit package structure according to claim 1, it is characterised in that the chip is provided with 8 interfaces, corresponding The ground encapsulating structure is provided with 8 pins, the first pin connection VDD interfaces, the second pin connection VPP interfaces, three-prong, the 4th Pin connects PA interfaces, the 5th pin connection PB or PD interfaces, the 6th pin, the 7th pin connection PWM interfaces, the 8th pin company Connect VSS interfaces.
- 3. integrated circuit package structure according to claim 1, it is characterised in that the chip is provided with 16 interfaces, right Should the ground encapsulating structure be provided with 16 pins, the first pin, the 6th pin, the 7th pin, the 8th pin connect PA interfaces, second Pin, the 11st pin connection VDD interfaces, the 5th pin connection VDDL interfaces, three-prong connection VPP interfaces, the 4th pin Connect NC interfaces, the 9th pin, the tenth pin, the 15th pin, the 16th pin, the 12nd pin, the connection of the tenth three-prong PWM interfaces, the 14th pin connection VSS interfaces.
- 4. integrated circuit package structure according to claim 1, it is characterised in that the chip is provided with 16 interfaces, right Should the ground encapsulating structure be provided with 16 pins, the first pin, the 4th pin, the 5th pin, the 6th pin connect PA interfaces, second Pin, the 11st pin connection VDD interfaces, the 7th pin connection VDDL interfaces, three-prong connection VPP interfaces, the 8th pin, 15th pin, the 16th pin connection PC interfaces, the 9th pin, the tenth pin connection PD interfaces, the 12nd pin, the 13rd Pin connects PWM interfaces, the 14th pin connection VSS interfaces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720279059.8U CN206639795U (en) | 2017-03-21 | 2017-03-21 | A kind of integrated circuit package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720279059.8U CN206639795U (en) | 2017-03-21 | 2017-03-21 | A kind of integrated circuit package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206639795U true CN206639795U (en) | 2017-11-14 |
Family
ID=60250657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720279059.8U Expired - Fee Related CN206639795U (en) | 2017-03-21 | 2017-03-21 | A kind of integrated circuit package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206639795U (en) |
-
2017
- 2017-03-21 CN CN201720279059.8U patent/CN206639795U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171114 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |