CN206961822U - The encapsulating structure and printed circuit board (PCB) of chip - Google Patents
The encapsulating structure and printed circuit board (PCB) of chip Download PDFInfo
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- CN206961822U CN206961822U CN201720780830.XU CN201720780830U CN206961822U CN 206961822 U CN206961822 U CN 206961822U CN 201720780830 U CN201720780830 U CN 201720780830U CN 206961822 U CN206961822 U CN 206961822U
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Abstract
The application provides the encapsulating structure and printed circuit board (PCB) of chip, and encapsulating structure is soldered to the pad area of printed circuit board (PCB), and the edge of the encapsulating structure plane adjacent with pad area is provided with PCIe pin areas；PCIe pin areas include at least two row's pins；At least at least part pin of each row of two row's pins is the PCIe pins for coupling PCIe interface lead；Wherein, at least two row's pins include first row pin and second row pin, and first row pin is arranged on the outside relative to second row pin of the plane adjacent with pad area of encapsulating structure；First row pin and second row pin arrange in the first direction；The first area of isolation is provided with first row pin between adjacent PCIe pins, the PCIe pins on second row pin are set so that pass through the first area of isolation by the PCIe pins on second row pin and perpendicular to the straight line of first direction.First area of isolation of the application encapsulating structure is not provided with pin, reduces the wiring difficulty of the PCIe interface lead on printed circuit board (PCB).
Description
Technical field
The application is related to chip encapsulation technology field, more particularly to the encapsulating structure and printed circuit board (PCB) of chip.
Background technology
The pad area of printed circuit board (PCB) is soldered to after chip package, multiple pads of pad area are used for the encapsulation with chip
Pin in structure is welded.Lead is coupled on pad, is connected for chip to be carried out into circuit with other components.There is provided
The PCIe pins of the chip of PCIe interface are used to couple PCIe interface signal.The lead of transmission PCIe interface signal needs to meet
PCIe bus specifications, to make chip access meet PCIe high frequency environment.Due to the space between adjacent PCIe pins compared with
It is small, it is difficult to service wire is set in the superficial layer of printed circuit board (PCB), adds manufacture difficulty and cost of manufacture.
Utility model content
The application provides the encapsulating structure and printed circuit board (PCB) of chip, the service wire of PCIe pins is arranged on printing electricity
The superficial layer of road plate, reduce the difficulty and cost of manufacture of the lead for arranging PCIe interface signal on a printed circuit.
To reach above-mentioned purpose, according to the first aspect of the application, there is provided according to the first core of the application first aspect
The encapsulating structure of piece, encapsulating structure is used to accommodate chip, and is soldered to the pad area of printed circuit board (PCB), and pad area includes multiple
Pad, the edge of the encapsulating structure plane adjacent with pad area are provided with PCIe pin areas；PCIe pin areas include at least two rows
Pin；At least at least part pin of each row of two row's pins is the PCIe pins for coupling PCIe interface lead；Wherein,
At least two row's pins include first row pin and second row pin, and first row pin is arranged on the adjacent with pad area of encapsulating structure
Plane the outside relative to second row pin；First row pin arranges in the first direction, and second row pin is in the first direction
Arrangement；The first area of isolation is provided with first row pin between adjacent PCIe pins, sets the PCIe on second row pin to draw
Pin so that pass through the first area of isolation by the PCIe pins on second row pin and perpendicular to the straight line of first direction.
According to the encapsulating structure of the first chip of the first aspect of the application, there is provided according to the of the application first aspect
The encapsulating structure of two chips, wherein, the first area of isolation is provided with the pin for coupling power lead or ground lead.
According to the encapsulating structure of the first chip of the first aspect of the application, there is provided according to the of the application first aspect
The encapsulating structure of three chips, wherein, it is not provided with pin in the first area of isolation so that the first row pin at the first area of isolation
The distance between upper adjacent PCIe pins are more than the distance between pin adjacent on second row pin.
One of encapsulating structure according to the first of the first aspect of the application to the 3rd chip, there is provided according to the application
The encapsulating structure of the fourth chip of one side, wherein, the pad area of printed circuit board (PCB) include respectively with the first area of isolation both sides
The welding of PCIe pins two pads between first area, in first area, at least one the first PCIe interface leads are set
To couple the PCIe pins of second row pin.
According to the encapsulating structure of the fourth chip of the first aspect of the application, there is provided according to the of the application first aspect
The encapsulating structure of five chips, wherein, PCIe pin areas also include the 3rd row's pin, and at least part pin of the 3rd row's pin is use
In the PCIe pins of coupling PCIe interface lead；3rd row's pin is arranged on the phase of the plane adjacent with pad area of encapsulating structure
For the inner side of second row pin；At least one the second PCIe interface leads are set to couple the 3rd row's pin in first area
PCIe pins.
According to the encapsulating structure of the fifth chip of the first aspect of the application, there is provided according to the of the application first aspect
The encapsulating structure of six chips, wherein, PCIe pin areas also include the 4th row's pin, and at least part pin of the 4th row's pin is use
In the PCIe pins of coupling PCIe interface lead；4th row's pin is arranged on the phase of the plane adjacent with pad area of encapsulating structure
For the outside of first row pin；The second area of isolation is provided with 4th row's pin between adjacent PCIe pins, by second
Area of isolation and straight line perpendicular to first direction passes through the first area of isolation；Pad area be provided with respectively with the second area of isolation two
Second area between two pads of the pin welding of side；At least three PCIe interface leads are set to couple in second area
The PCIe pins of the PCIe pins of first row pin, the PCIe pins of second row pin and the 3rd row's pin.
According to the encapsulating structure of the fifth chip of the first aspect of the application, there is provided according to the of the application first aspect
The encapsulating structure of seven chips, wherein, PCIe pin areas also include the 4th row's pin, and at least part pin of the 4th row's pin is use
In the PCIe pins of coupling PCIe interface lead；4th row's pin is arranged on the phase of the plane adjacent with pad area of encapsulating structure
For the outside of first row pin；The second area of isolation is provided with 4th row's pin between adjacent PCIe pins, by second
Area of isolation and straight line perpendicular to first direction passes through the first area of isolation；Pad area be provided with respectively with the second area of isolation two
Second area between two pads of the pin welding of side；In second area, at least the first PCIe interface lead, second are set
The PCIe interface lead of the PCIe pins of PCIe interface lead and coupling first row pin.
According to the encapsulating structure of the fourth chip of the first aspect of the application, there is provided according to the of the application first aspect
The encapsulating structure of eight chips, wherein, first row pin is provided with multiple first area of isolation, and the pad area of printed circuit board (PCB) is including more
Individual first area, each first area are corresponding with one of them first area of isolation.
According to the encapsulating structure of the first chip of the first aspect of the application, there is provided according to the of the application first aspect
The encapsulating structure of nine chips, wherein, all PCIe interface leads are located at the same layer of printed circuit board (PCB).
One of encapsulating structure according to the first of the first aspect of the application to the 9th chip, there is provided according to the application
The encapsulating structure of tenth chip of one side, wherein, the pin of PCIe pin areas is BGA soldered balls.
According to the encapsulating structure of the 6th or the 7th chip of the first aspect of the application, there is provided according to the application first party
The encapsulating structure of 11st chip in face, wherein, the width of the first area of isolation and the second area of isolation draws more than PCIe interface
Three times of the width of line.
According to the second aspect of the application, there is provided according to the first printed circuit board (PCB) of the application second aspect, including weldering
Panel and the encapsulating structure for the chip being arranged on pad area；Pad area includes multiple pads, it is characterised in that encapsulating structure with
The edge of the adjacent plane of pad area is provided with PCIe pin areas；PCIe pin areas include at least two row's pins；At least two rows draw
At least part pin of each row of pin is the PCIe pins for coupling PCIe interface lead；Wherein, at least two row's pin bags
Include first row pin and second row pin, first row pin be arranged on the plane adjacent with pad area of encapsulating structure relative to
The outside of second row pin；First row pin arranges in the first direction, and second row pin arranges in the first direction；First row pin
The first area of isolation is provided between upper adjacent PCIe pins, the PCIe pins on second row pin are set so that by second
Arrange the PCIe pins on pin and pass through the first area of isolation perpendicular to the straight line of first direction.
According to the first printed circuit board (PCB) of the second aspect of the application, there is provided according to the second of the application second aspect the print
Printed circuit board, wherein, the pad area of printed circuit board (PCB) includes welded respectively with the PCIe pins of the first area of isolation both sides two
First area between individual pad, at least one the first PCIe interface leads are set to couple second row pin in first area
PCIe pins.
According to the second printed circuit board (PCB) of the second aspect of the application, there is provided according to the 3rd of the application second aspect the print
Printed circuit board, wherein, PCIe pin areas also include the 3rd row's pin, and at least part pin of the 3rd row's pin is for coupling
The PCIe pins of PCIe interface lead；3rd row's pin be arranged on the plane adjacent with pad area of encapsulating structure relative to
The inner side of two row's pins；At least one the second PCIe interface leads are also set up in first area to couple the PCIe of the 3rd row's pin
Pin.
What the application realized has the beneficial effect that：
(1) the first area of isolation of encapsulating structure is not provided with pin so that the corresponding region of printed circuit board (PCB) need not be set
Pad, cabling space is provided to couple the PCIe interface lead of second row pin, the PCIe interface reduced on printed circuit board (PCB) is drawn
The wiring difficulty of line.
(2) the first area of isolation of encapsulating structure and the second area of isolation are not provided with pin, can be set on encapsulating structure
More multiple rows of PCIe pins, the corresponding region of printed circuit board (PCB) need not set pad, to couple the PCIe interface on more multiple rows of pin
Lead provides cabling space, meets the needs of more PCIe interface leads.
(3) the first area of isolation of encapsulating structure only sets two row's PCIe pins, PCIe interface in the case of setting pin
Lead reduces the manufacture difficulty of printed circuit board (PCB) without unnecessary cabling space.
Brief description of the drawings
, below will be to embodiment or existing in order to illustrate more clearly of the embodiment of the present application or technical scheme of the prior art
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments described in application, for those skilled in the art, it can also be obtained according to these accompanying drawings other attached
Figure.
Fig. 1 is the encapsulating structure of chip and the assembling schematic diagram of printed circuit board (PCB) according to the embodiment of the present application；
Fig. 2 is the encapsulating structure of chip and the assembling schematic diagram of printed circuit board (PCB) according to the embodiment of the present application two；
Fig. 3 is the encapsulating structure of chip and the assembling schematic diagram of printed circuit board (PCB) according to the embodiment of the present application three；
Fig. 4 is the schematic diagram according to the encapsulating structure of the chip of the embodiment of the present application four；And
Fig. 5 is the partial enlarged drawing in the region 450 of Fig. 4 encapsulating structure.
Embodiment
With reference to the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Ground describes, it is clear that described embodiment is some embodiments of the present application, rather than whole embodiments.Based on the application
In embodiment, the every other embodiment that those skilled in the art are obtained under the premise of creative work is not made, all
Belong to the scope of the application protection.
Embodiment one
Fig. 1 is the encapsulating structure of chip and the assembling schematic diagram of printed circuit board (PCB) according to the embodiment of the present application.Such as Fig. 1 institutes
Show, the encapsulating structure 10 of chip is used to accommodate chip, and can be soldered to the pad area of printed circuit board (PCB) 100 (by the envelope of chip
The region that assembling structure 10 covers).Encapsulating structure 10 includes multiple rows of pin.Pad area includes multiple pads, for by encapsulating structure
10 at least part pin is welded on printed circuit board (PCB) 100.
As shown in figure 1, plane (two be welded to each other that encapsulating structure 10 is adjacent with the pad area of printed circuit board (PCB) 100
Plane) edge be provided with PCIe pin areas.PCIe pin areas include at least two row's pins, and (referring to Fig. 1, pin row 110 is with drawing
120) pin is arranged.Pin row 110 and pin row 120 include multiple pins.At least each row's of two row's pins is part or all of
Pin is the PCIe pins for coupling PCIe interface lead, as be labeled with Fig. 1 " PCIe " pin (112,114,116,
118th, 122,124,126,128,152,154,156 and 158).
Printed circuit board (PCB) 100 also includes golden finger area 130.Golden finger area 130 is provided with multiple golden fingers (132,134),
As the part of connector, for printed circuit board (PCB) to be connected into external equipment.Golden finger (132,134) is used to transmit telecommunications
Number.As an example, part golden finger transmission PCIe interface signal.
Alternatively, it is bga structure according to the encapsulating structure of the embodiment of the present application, the pin of PCIe pin areas is BGA
Soldered ball.Relative to other encapsulating structures, the pad of bga structure is bigger, easily operated, and reliability is high.
With continued reference to Fig. 1, in the present embodiment, PCIe pin areas include pin row 110 and pin row 120, and pin row 110 sets
Put in the outside relative to pin row 120 of the plane adjacent with pad area of encapsulating structure 10 (in Fig. 1 under encapsulating structure 10
Side).PCIe pin areas are arranged on the edge of encapsulating structure 10.Relative in the plane adjacent with pad area of encapsulating structure 10
The heart, the edge of encapsulating structure 10 is referred to as outside.Pin row 110 and pin the row 120 in the horizontal direction (institute of arrow 160 in Fig. 1
Show) arrangement.It is to be appreciated that PCIe pin areas may also set up the left margin of encapsulating structure 10 in Fig. 1 or the right edge.
With reference to figure 1, in embodiment one, it is provided with pin row 110 between adjacent PCIe pins (112,114,116,118)
Area of isolation (142,144,146,148), to reduce the crosstalk between adjacent PCIe pins.It is provided with pin row 120
PCIe pins 122, PCIe pins 124, PCIe pins 126 and PCIe pins 128, respectively with area of isolation 142, area of isolation
144th, area of isolation 146 and area of isolation 148 are adjacent, and PCIe pins with area of isolation adjacent thereto line with by arrow
The orientation of pin row indicated by first 160 is vertical.
Alternatively, PCIe pins 152, PCIe pins 154, PCIe pins 156 and PCIe are additionally provided with pin row 120
Pin 158, respectively with PCIe pins 112, PCIe pins 114, PCIe pins 116 and the phase of PCIe pins 118 of pin row 110
It is adjacent.And the PCIe pins in pin row 120, the line with the PCIe pins in pin row 110 adjacent thereto is the same as by arrow 160
The orientation of indicated pin row is vertical.
In the embodiment shown in fig. 1, area of isolation (142,144,146,148) is provided with for coupling ground lead GND
Pin.Alternatively, area of isolation is provided for the pin of coupling power lead.
The pin of encapsulating structure 10 corresponds with the pad of printed circuit board (PCB) 100.
Lead is set on printed circuit board (PCB) 100, to connect golden finger and pad, and the pin of pad and encapsulating structure 10
Welding, so that golden finger is connected to the pin of encapsulating structure.The lead for connecting PCIe pins is referred to as PCIe interface lead.
The pad (not shown) welded with the GND pin on area of isolation (142,144,146,148) is additionally provided with pad area.
Golden finger is connected to the PCIe pins of PCIe pin areas by PCIe interface lead.For example, as shown in figure 1, golden hand
Refer to the 132 PCIe pins 112 that pin row 110 is connected to by PCIe interface lead, connection golden finger 134 is arranged in 120 with pin
The leads of PCIe pins 152 passed through from printed circuit board (PCB) 100 with position corresponding to area of isolation 142, and avoid contact with and draw
GND pin 142 in pin row 110.Referring to Fig. 1, as an example, set in pin 110 area of isolation 142 of row in outside
GND pin has been put, between GND pin and PCIe pins 112, a lead can have still been accommodated and pass through, so as to which the lead can connect
The PCIe pins 152 being connected in the pin row 120 of inner side.And area of isolation 142 GND pin and PCIe pins 114 it
Between, a lead can also be accommodated and passed through, to connect the PCIe pins 122 in PCIe rows 120.
In the present embodiment, PCIe pin areas are set in the edge of encapsulating structure, connection PCIe pins and golden hand can be shortened
The length of the PCIe interface lead of finger, reduce influence of the PCIe interface lead to PCIe signals.
Embodiment two
Fig. 2 illustrates the PCIe connectors of the encapsulating structure and printed circuit board (PCB) according to the chip of the embodiment of the present application two.
In the present embodiment, chip-packaging structure 20 is disposed with printed circuit board (PCB) 200.Chip-packaging structure 20 includes multiple
Pin.The region of the receiving PCIe pins of encapsulating structure is referred to as PCIe pin areas.In Fig. 2, PCIe pin areas are arranged including pin
210 and pin row 220.Pin row 210 be arranged on encapsulating structure 20 the planes adjacent with pad area relative to pin arrange 220
Outside.PCIe pin areas are arranged on the edge of encapsulating structure 20.
With reference in the embodiment two of figure 2, it is provided with pin row 210 between adjacent PCIe pins (212,214,216 and 218)
Area of isolation (242,244,246 and 248), to reduce the crosstalk between adjacent PCIe pins.It is provided with pin row 220
PCIe pins 222, PCIe pins 224, PCIe pins 226 and PCIe pins 228, respectively with area of isolation 242, area of isolation
244th, area of isolation 246 and area of isolation 248 are adjacent, and PCIe pins with area of isolation adjacent thereto line with by arrow
The orientation of pin row indicated by first 260 is vertical.
As shown in Fig. 2 area of isolation (242) is not provided with pin so that the phase on area of isolation (242) place pin row 210
The distance between adjacent PCIe pins (212 and 214) be more than pin arrange between pin (252 and 222) adjacent on 220 away from
From.The region relative with area of isolation 242 need not set pad on printed circuit board (PCB) 200, be used so as to provide more spaces
In setting lead, one or more of 220 pins are arranged to connect pin.
As shown in Fig. 2 golden finger 232 is connected to the PCIe pins 212 of pin row 210, connection by PCIe interface lead
The lead that golden finger 234 arranges the PCIe pins 152 in 220 with pin is corresponding with area of isolation 242 from printed circuit board (PCB) 200
Region passes through.And the lead also same area of isolation from printed circuit board (PCB) 200 of the PCIe pins 222 in connection PCIe rows 220
Region passes through corresponding to 242.Due to being not provided with pin in area of isolation 242 so that same area of isolation on printed circuit board (PCB) 200
Region corresponding to 242 need not set pad, so as on printed circuit board (PCB) 200 with can be accommodated in region corresponding to area of isolation 242
More leads pass through.
Alternatively, all PCIe interface leads are located at the same layer of printed circuit board (PCB), such as superficial layer.
Alternatively, in the case where area of isolation 242 is not provided with pin, on the printed circuit board 200 with area of isolation 242
The setting GND signal vias in corresponding region.
Embodiment three
Fig. 3 illustrates the PCIe connectors of the encapsulating structure and printed circuit board (PCB) according to the chip of the embodiment of the present application three.
In the present embodiment, chip-packaging structure 30 is disposed with printed circuit board (PCB) 300.In Fig. 3, chip-packaging structure 30 wraps
Include pin row 310 and pin row 320.
With reference to figure 3, in embodiment three, set on pin row 310 between adjacent PCIe pins (312,314,316 and 318)
There is area of isolation (342,344 and 346), to reduce the crosstalk between adjacent PCIe pins.PCIe is provided with pin row 320
Pin 352 and PCIe pins 354, it is adjacent with area of isolation 344 with area of isolation 342 respectively, and PCIe pins (352,354) are same
The line of area of isolation (342,344) adjacent thereto is vertical with the orientation arranged as the pin indicated by arrow 360.Pin
In row 320, non-PCIe pins are set between PCIe pins, in order to the wiring of PCIe pins, and/or reduce PCIe pins it
Between interference.Referring to Fig. 3, for example, setting power pins between the PCIe pins 352 and PCIe pins 354 of pin row 320
322 (being indicated by Vss).
As shown in figure 3, area of isolation (342,344,346) is not provided with pin so that in area of isolation (for example, isolated area
Domain 342) the distance between adjacent PCIe pins (312 and 314) are more than pin and arrange adjacent on 320 draw on place's pin row 310
The distance between pin (PCIe pins 352 and power pins 322).Same area of isolation (342,344,346) on printed circuit board (PCB) 300
Relative region need not set pad, be used to set lead so as to provide more spaces, to connect one in pin row 320
Individual or multiple pins.
As shown in figure 3, golden finger area 330 includes multiple golden fingers (332,334,336,362,364,366).Golden finger
332 are connected to the PCIe pins 312 of pin row 310 by PCIe interface lead, and connection golden finger 334 is arranged in 320 with pin
The lead of PCIe pins 352 passes through from printed circuit board (PCB) 300 with region corresponding to area of isolation 342.And connect another draw
The lead of PCIe pins 372 in pin row also passes through from printed circuit board (PCB) 300 with region corresponding to area of isolation 342.Due to
Pin is not provided with area of isolation 342 so that need not be set and be welded with region corresponding to area of isolation 342 on printed circuit board (PCB) 300
Disk, so as to pass through with more leads can be accommodated in region corresponding to area of isolation 342 on printed circuit board (PCB) 300.
With continued reference to Fig. 3, PCIe interface lead connection golden finger 362 and PCIe pins 314.Connect golden finger 364 with
The lead of PCIe pins 354 passes through from printed circuit board (PCB) 300 corresponding to the region of isolated area 344.Connect golden finger 366 with
Region of the lead of PCIe pins 374 also corresponding to isolated area 344 from printed circuit board (PCB) 300 passes through.
In Fig. 3 embodiment, the PCIe pins in pin row 320 are not adjacent to each other, also, the PCIe in pin row 320
Pin with pin row 310 in isolated area it is adjacent, in order to connect pin row 320 in PCIe pins PCIe interface lead from
The region for corresponding to the isolated area that pin row 310 provides on printed circuit board (PCB) passes through.Similarly, including PCIe pins 372 with
In the pin row of PCIe pins 374, PCIe pins are also not adjacent to each other.
Alternatively, all PCIe interface leads are located at the same layer of printed circuit board (PCB), such as superficial layer.
Example IV
Fig. 4 is the schematic diagram according to the encapsulating structure of the chip of the embodiment of the present application four.
As shown in figure 4, encapsulating structure 40 includes pin row 410, pin row 420, pin row 430 and pin row 440.It is self-styled
The outside (edge of encapsulating structure 40) of the plane adjacent with pad area of assembling structure 40 is to inner side (center of encapsulating structure 40)
Set gradually pin row 410, pin row 420, pin row 430 and pin row 440.410, pin row 420, pin row are arranged in pin
430 and pin row 440 PCIe pins are set, the pin row 410 on encapsulating structure 40, pin row 420, pin row 430 and are drawn
Pin arranges 440 regions and is referred to as PCIe pin areas.PCIe pin areas are arranged on the edge of encapsulating structure.Pin row 750, pin row
710th, pin row 720 and pin row 740 arrange in the horizontal direction.
With reference to figure 4, area of isolation is provided with (for example, isolation between (at least part) adjacent PCIe pins on pin row 410
Region 416), to reduce the crosstalk between adjacent PCIe pins, and provided to accommodate PCIe interface lead on printed circuit board (PCB)
Space.On pin row 420 area of isolation (such as area of isolation 426) is provided between adjacent PCIe pins.By area of isolation
416 and perpendicular to horizontal direction (in Fig. 4 pin arrange 410 and 420 extend directions) straight line pass through area of isolation 426.Also
It is to say that area of isolation 416 and area of isolation 426 are set at same position in the horizontal direction.As shown in figure 4, in area of isolation
It is not provided with pin.
On pin row 430 and pin row 440, in vertical direction, (pin arranges the side of 410 and 420 extensions in Fig. 4
To) and be provided with PCIe pins by the straight line of area of isolation (416,426).Alternatively, on pin row 430 and pin row 440,
PCIe pins also are provided with the straight line of vertical direction and the PCIe pins of process pin row 410.
Fig. 5 is the partial enlarged drawing in the region 450 of Fig. 4 encapsulating structure.
In embodiment shown in Fig. 5,410 (referring also to Fig. 4) of pin row pin 412 and pin 414, pin row 420 (
Referring to Fig. 4) pin 422 and pin 424, pin arranges 430 (referring also to Fig. 4) pin 432, and pin row 440 (referring also to
Pin 442 Fig. 4), it is PCIe pins.
Encapsulating structure 40 includes area of isolation 416 between PCIe pins 412 and PCIe pins 414, and encapsulating structure 40 exists
Include area of isolation 426 between PCIe pins 422 and PCIe pins 424.PCIe pins 432 are adjacent with area of isolation 426, PCIe
Pin 442 is adjacent with PCIe pins 432, and PCIe pins 442, PCIe pins 432, area of isolation 416 and area of isolation 426
Generally arranging point-blank (has the horizontal level being substantially the same) in Fig. 5.
When encapsulating structure 40 is coupled to printed circuit board (PCB), the PCIe interface lead 482 on printed circuit board (PCB) connects PCIe
Pin 412, the PCIe interface lead 484 on printed circuit board (PCB) connect PCIe pins 422, and the PCIe interface on printed circuit board (PCB) is drawn
Line 486 connects PCIe pins 432, and the connection PCIe of PCIe interface lead 488 pins 442 on printed circuit board (PCB).
PCIe interface lead 484 passes through from printed circuit board (PCB) with region corresponding to area of isolation 416, PCIe interface lead
486 pass through from printed circuit board (PCB) with region corresponding to area of isolation 416, and PCIe interface lead 488 is from printed circuit board (PCB)
On passed through with region corresponding to area of isolation 416.PCIe interface lead 484 is from printed circuit board (PCB) with the correspondence of area of isolation 426
Region pass through, PCIe interface lead 486 passes through from printed circuit board (PCB) with region corresponding to area of isolation 426, and PCIe
Service wire 488 passes through from printed circuit board (PCB) with region corresponding to area of isolation 426.By provide area of isolation 416 with every
From region 426 so that the lead of the PCIe pins on the pin row at the edge away from chip-packaging structure 40, can easily exist
Set on printed circuit board (PCB).
Alternatively, three times of the width of area of isolation 416 and area of isolation 426 more than the width of PCIe interface lead.Phase
Ying Di, the width on printed circuit board (PCB) with region corresponding to area of isolation 416 and area of isolation 426 are more than PCIe interface lead
Three times of width.
Alternatively, on printed circuit board (PCB) corresponding to area of isolation 426 region set at least three PCIe interface leads with
Couple PCIe pins.A part for three PCIe interface leads passes through the area for corresponding to area of isolation 416 on printed circuit board (PCB)
Domain.
Alternatively, pin row 410 and pin row 420 are provided with multiple area of isolation, and the pad area of printed circuit board (PCB) is included together
Region corresponding to each area of isolation.
Alternatively, PCIe interface lead all on printed circuit board (PCB) is located at same layer (such as the surface of printed circuit board (PCB)
Layer), the manufacture craft of printed circuit board (PCB) is simplified, reduces cost of manufacture.
Alternatively, in the case where area of isolation is not provided with pin, on a printed circuit corresponding to the area of area of isolation
Domain sets power supply or GND signal vias.
In the present embodiment, the region on printed circuit board (PCB) corresponding to area of isolation carries for the PCIe interface lead of PCIe pins
For cabling space, the wiring difficulty of the PCIe interface lead on printed circuit board (PCB) is reduced.
Although having been described for the preferred embodiment of the application, those skilled in the art once know basic creation
Property concept, then can make other change and modification to these embodiments.So appended claims be intended to be construed to include it is excellent
Select embodiment and fall into having altered and changing for the application scope.Obviously, those skilled in the art can be to the application
Various changes and modification are carried out without departing from spirit and scope.So, if these modifications and variations of the application
Belong within the scope of the application claim and its equivalent technologies, then the application is also intended to exist comprising these changes and modification
It is interior.
Claims (10)
1. a kind of encapsulating structure of chip, the encapsulating structure is used to accommodate chip, and is soldered to the pad of printed circuit board (PCB)
Area, the pad area include multiple pads, it is characterised in that the edge of the encapsulating structure plane adjacent with the pad area
Place is provided with PCIe pin areas；The PCIe pin areas include at least two row's pins；At least at least portion of each row of two row's pins
It is the PCIe pins for coupling PCIe interface lead to separate pin；
Wherein, at least two row's pins include first row pin and second row pin, and the first row pin is arranged on described
The outside relative to the second row pin of the plane adjacent with the pad area of encapsulating structure；The first row pin edge
First direction arranges, and the second row pin arranges in the first direction；
The first area of isolation is provided with the first row pin between adjacent PCIe pins, is set on the second row pin
PCIe pins so that pass through by the PCIe pins on the second row pin and perpendicular to the straight line of the first direction
First area of isolation.
2. the encapsulating structure of chip according to claim 1, it is characterised in that first area of isolation, which is provided with, to be used for
The pin of coupling power lead or ground lead.
3. the encapsulating structure of chip according to claim 1, it is characterised in that be not provided with drawing in first area of isolation
Pin so that distance between PCIe pins adjacent on the first row pin at first area of isolation is more than described the
The distance between adjacent pin on two row's pins.
4. the encapsulating structure of chip according to claim 1, it is characterised in that the pad area of printed circuit board (PCB) includes
First area between two pads welded respectively with the PCIe pins of the first area of isolation both sides, in firstth area
Domain sets at least one the first PCIe interface leads to couple the PCIe pins of the second row pin.
5. the encapsulating structure of chip according to claim 4, it is characterised in that the PCIe pin areas also include the 3rd row
Pin, at least part pin of the 3rd row's pin are the PCIe pins for coupling PCIe interface lead；
3rd row's pin be arranged on the plane adjacent with the pad area of the encapsulating structure relative to described second
Arrange the inner side of pin；
At least one the second PCIe interface leads are set to couple the PCIe pins of the 3rd row's pin in the first area.
6. the encapsulating structure of chip according to claim 4, it is characterised in that the first row pin is provided with multiple first
Area of isolation, the pad area of printed circuit board (PCB) include multiple first areas, and each first area is the same as one of institute
It is corresponding to state the first area of isolation.
7. the encapsulating structure of the chip according to claim any one of 1-6, it is characterised in that all PCIe interfaces
Lead is located at the same layer of the printed circuit board (PCB).
8. a kind of printed circuit board (PCB), including the encapsulating structure of pad area and the chip being arranged on the pad area；
The pad area includes multiple pads, it is characterised in that the side of the encapsulating structure plane adjacent with the pad area
PCIe pin areas are provided with edge；The PCIe pin areas include at least two row's pins；At least each row of two row's pins is at least
Part pin is the PCIe pins for coupling PCIe interface lead；
Wherein, at least two row's pins include first row pin and second row pin, and the first row pin is arranged on described
The outside relative to the second row pin of the plane adjacent with the pad area of encapsulating structure；The first row pin edge
First direction arranges, and the second row pin arranges in the first direction；
The first area of isolation is provided with the first row pin between adjacent PCIe pins, is set on the second row pin
PCIe pins so that pass through by the PCIe pins on the second row pin and perpendicular to the straight line of the first direction
First area of isolation.
9. printed circuit board (PCB) according to claim 8, it is characterised in that the pad area of printed circuit board (PCB) includes difference
First area between two pads welded with the PCIe pins of the first area of isolation both sides, sets in the first area
At least one the first PCIe interface leads are put to couple the PCIe pins of the second row pin.
10. printed circuit board (PCB) according to claim 9, it is characterised in that also draw including the 3rd row the PCIe pin areas
Pin, at least part pin of the 3rd row's pin are the PCIe pins for coupling PCIe interface lead；
3rd row's pin be arranged on the plane adjacent with the pad area of the encapsulating structure relative to described second
Arrange the inner side of pin；
At least one the second PCIe interface leads are also set up in the first area to couple the PCIe of the 3rd row's pin to draw
Pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720780830.XU CN206961822U (en) | 2017-06-30 | 2017-06-30 | The encapsulating structure and printed circuit board (PCB) of chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720780830.XU CN206961822U (en) | 2017-06-30 | 2017-06-30 | The encapsulating structure and printed circuit board (PCB) of chip |
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| CN206961822U true CN206961822U (en) | 2018-02-02 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111400988A (en) * | 2018-12-27 | 2020-07-10 | 北京忆芯科技有限公司 | Bump (Bump) board layout method for integrated circuit chip |
| WO2020214149A1 (en) * | 2019-04-15 | 2020-10-22 | Hewlett-Packard Development Company, L.P. | Printed circuit boards with solder joints of higher melting temperatures and traces coupling electrical contacts at differing positions |
| CN112638034A (en) * | 2019-09-24 | 2021-04-09 | 启碁科技股份有限公司 | Electronic device, mainboard thereof and packaging system module |
| CN115348721A (en) * | 2022-07-28 | 2022-11-15 | 苏州浪潮智能科技有限公司 | Signal connection structure and circuit board |
| WO2023133874A1 (en) * | 2022-01-17 | 2023-07-20 | 京东方科技集团股份有限公司 | Display module, fabrication method therefor, and display apparatus thereof |
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2017
- 2017-06-30 CN CN201720780830.XU patent/CN206961822U/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111400988A (en) * | 2018-12-27 | 2020-07-10 | 北京忆芯科技有限公司 | Bump (Bump) board layout method for integrated circuit chip |
| CN111400988B (en) * | 2018-12-27 | 2023-08-22 | 北京忆芯科技有限公司 | Bump (Bump) pad layout method for integrated circuit chip |
| WO2020214149A1 (en) * | 2019-04-15 | 2020-10-22 | Hewlett-Packard Development Company, L.P. | Printed circuit boards with solder joints of higher melting temperatures and traces coupling electrical contacts at differing positions |
| CN112638034A (en) * | 2019-09-24 | 2021-04-09 | 启碁科技股份有限公司 | Electronic device, mainboard thereof and packaging system module |
| CN112638034B (en) * | 2019-09-24 | 2022-05-27 | 启碁科技股份有限公司 | Electronic device, mainboard thereof and packaging system module |
| WO2023133874A1 (en) * | 2022-01-17 | 2023-07-20 | 京东方科技集团股份有限公司 | Display module, fabrication method therefor, and display apparatus thereof |
| CN115348721A (en) * | 2022-07-28 | 2022-11-15 | 苏州浪潮智能科技有限公司 | Signal connection structure and circuit board |
| CN115348721B (en) * | 2022-07-28 | 2024-01-23 | 苏州浪潮智能科技有限公司 | Signal connection structure and circuit board |
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