CN111400988B - Bump (Bump) pad layout method for integrated circuit chip - Google Patents
Bump (Bump) pad layout method for integrated circuit chip Download PDFInfo
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- CN111400988B CN111400988B CN201811613847.1A CN201811613847A CN111400988B CN 111400988 B CN111400988 B CN 111400988B CN 201811613847 A CN201811613847 A CN 201811613847A CN 111400988 B CN111400988 B CN 111400988B
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Abstract
Bump (Bump) disk layout methods for integrated circuit chips are provided. A Bump (Bump) disk layout method in an integrated circuit design is provided, comprising: placing a circuit unit; selecting one or more circuit units sensitive to the influence of the bump pad from the placed circuit units; acquiring one or more sensitive areas where the one or more circuit units are located; placing a bump disc on the surface layer of the designed integrated circuit; identifying one or more bump pads located in corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit; and adjusting the positions of the one or more bump pads to be away from the one or more sensitive areas in the corresponding areas of the surface layer of the integrated circuit.
Description
Technical Field
The application relates to the field of integrated circuits, in particular to a method for reasonably distributing bump pads of an integrated circuit chip on the surface of the chip so as to improve the yield of the chip.
Background
With the rapid development of semiconductor technology, the system integration of semiconductor integrated circuits is higher and the area is larger. The increase in area causes the leads to lengthen, thereby introducing a problem of IR Drop (voltage Drop due to current multiplied by resistance, IR Drop). To address the problem of IR Drop, more and more integrated circuit CHIPs began to choose designs using FLIP-CHIP. To implement the flip-chip package, a plurality of bumps (bumps) are provided on the surface of the chip as contact areas for connecting the leads inside the chip with the external package solder balls.
Disclosure of Invention
However, the bump has a large size (relative to the leads and elements of the chip) itself presses against the surroundings due to gravity, which is affected by pressure or the like during the bump growth (Bumping). Particularly, when a pressure sensitive circuit, particularly an analog circuit such as a PLL (Phase-locked Loop), is present in a region adjacent to the bump inside the chip, the presence of the bump may cause instability of the electrical characteristics of the chip and a decrease in the yield of the chip flow.
The inventors have further found that the VCO (Voltage Controlled Oscillator ) in a PLL is particularly sensitive to bumps. Therefore, the application is provided to avoid the PLL, especially the VCO of the PLL, in the area where the PLL is located when the bumps are laid out, so as to reduce the influence of the bumps on the chip yield and enable the chip to be produced in a smooth quantity.
According to a first aspect of the present application, there is provided a Bump (Bump) disk layout method in a first integrated circuit design according to the first aspect of the present application, comprising: placing a circuit unit; selecting one or more circuit units sensitive to the influence of the bump pad from the placed circuit units; acquiring one or more sensitive areas where the one or more circuit units are located; placing a bump disc on the surface layer of the designed integrated circuit; identifying one or more bump pads located in corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit; and adjusting the positions of the one or more bump pads to be away from the one or more sensitive areas in the corresponding areas of the surface layer of the integrated circuit.
The bump pad layout method in the first integrated circuit design according to the first aspect of the present application provides the bump pad layout method in the second integrated circuit design according to the first aspect of the present application, further comprising: and if the position of the first bump pad, which enables the first bump pad to leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and does not violate the constraint condition of the design of the integrated circuit, cannot be found, deleting the first bump pad.
The bump pad layout method in the first or second integrated circuit design according to the first aspect of the present application provides the bump pad layout method in the third integrated circuit design according to the first aspect of the present application, further comprising: for a first bump pad positioned in a corresponding area of a first sensitive area on the surface layer of the integrated circuit, determining the center of the first sensitive area in the first corresponding area of the surface layer of the integrated circuit; the position of the first bump pad is changed in a direction away from the center of the first corresponding region such that the first bump pad is separated from the first corresponding region.
The bump pad layout method in the first integrated circuit design according to the first aspect of the present application provides the bump pad layout method in the fourth integrated circuit design according to the first aspect of the present application, further comprising: if the position of the first bump disc, which enables the first bump disc to leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and does not violate the constraint condition of the design of the integrated circuit, cannot be found, the first bump disc is marked as a state to be deleted; and adjusting the positions of other bump pads except the first bump pad in the one or more bump pads to enable the other bump pads to be separated from the corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit.
The bump pad layout method in the fourth integrated circuit design according to the first aspect of the present application provides the bump pad layout method in the fifth integrated circuit design according to the first aspect of the present application, further comprising: and deleting all the salient point discs marked as the state to be deleted.
According to one of the bump pad layout methods in the first to fifth integrated circuit designs of the first aspect of the present application, there is provided the bump pad layout method in the sixth integrated circuit design of the first aspect of the present application, wherein the one or more circuit units are analog circuit units.
A bump pad layout method in a sixth integrated circuit design according to the first aspect of the present application provides the bump pad layout method in a seventh integrated circuit design according to the first aspect of the present application, wherein the one or more circuit units are PLL units, radio frequency units and/or analog to digital conversion units.
The bump pad layout method in the seventh integrated circuit design according to the first aspect of the present application provides the bump pad layout method in the eighth integrated circuit design according to the first aspect of the present application, the one or more sensitive areas are areas where VCOs of the PLL unit are located.
According to one of the bump pad layout methods in the first to eighth integrated circuit designs of the first aspect of the present application, there is provided the bump pad layout method in the ninth integrated circuit design of the first aspect of the present application, further comprising: RDL design is performed to establish a connection between the bump pad and the circuit unit.
According to one of the bump pad layout methods in the first to ninth integrated circuit designs of the first aspect of the present application, there is provided the bump pad layout method in the tenth integrated circuit design of the first aspect of the present application, wherein the one or more sensitive areas are corresponding areas of a surface layer of the integrated circuit, and are areas obtained by projecting the one or more sensitive areas onto the surface layer of the designed integrated circuit.
According to one of the bump pad layout methods in the tenth integrated circuit design of the first aspect of the present application, there is provided the bump pad layout method in the ninth integrated circuit design of the eleventh aspect of the present application, wherein the one or more sensitive areas are located at each layer of the integrated circuit having the 3D structure or at a plurality of layers adjacent to the surface layer.
According to a second aspect of the present application there is provided a first computer according to the second aspect of the present application comprising a memory, a processor and a program stored on the memory and executable on the processor, characterized in that the processor is adapted to perform one of the bump pad layout methods in the integrated circuit design according to the first aspect of the present application when executing the program.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a top view of a chip according to an embodiment of the application;
FIG. 2 illustrates a schematic diagram of a bump layout on a chip according to an embodiment of the present application;
FIG. 3 illustrates a schematic diagram of a bump layout on a chip according to yet another embodiment of the present application; and
fig. 4 shows a flow chart of a chip design according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Fig. 1 shows a top view of a chip. In fig. 1, the normal to the chip surface is parallel to the line of sight.
A plurality of Bump pads (Bump pads) are arranged on the surface layer of the chip, and bumps are grown at the positions of the Bump pads. The bump pad is connected with the lead. Leads connect the bump pads to other circuit units or electrical components of other chips. The layer where the leads connecting the bump pads are located is referred to as RDL (redistribution layer ), and the network formed by the leads connecting the bump pads is referred to as RDL network. The bump pads may also be directly disposed on the top metal of the chip.
It will be appreciated that the RDL network may be located at a different layer of the chip than the bump and that when the bump is visible, the leads of the RDL network cannot be directly observed due to the obstruction of the chip structure.
Fig. 2 shows a schematic diagram of a layout of bumps on a chip according to an embodiment of the application.
The surface layer of the chip is provided with a plurality of bump pads. While below the skin, the area indicated by block 240, is placed with the PLL unit. And the PLL unit comprises a VCO which occupies the area indicated by the shaded box 260.
In accordance with an embodiment of the present application, since the VCO is sensitive to the effects of bumps, the underlying VCO region is avoided in block 260 when bump pads are placed on the surface of the chip. Referring to FIG. 2, block 260 has 4 bumped pads (210, 212, 214, and 216) around corresponding locations of the skin. By changing the placement of these bumps, it is separated from the corresponding area of the surface layer by a sufficient distance from block 260. By way of example, referring also to fig. 2, bump pad 220 and bump pad 222 are moved rightward and bump pad 210 and bump pad 212 are moved leftward relative to the original position of the bump pad. And, because bump pad 222 is moved, the spacing between the leads of coupling bump pad 222 and the leads of coupling bump pad 230 is too small, and bump pad 230 is moved to the right so that the spacing between the leads of coupling RDL network meets the specified constraints. By changing the positions where the 4 bump pads (210, 212, 214, and 216) are placed so that they avoid the corresponding areas of the block 260 on the surface of the chip, factors such as pressure formed during the bump growth process will not have a significant effect on the electrical characteristics of the VCO circuit of the area 260, thereby ensuring the quality and stability of the PLL.
The other bump pads in fig. 2 are disposed at their original positions because the lower layer of the area where these bump pads are located has no circuit sensitive to the influence of the bump pads such as pressure.
Fig. 3 shows a schematic diagram of a bump layout on a chip according to a further embodiment of the application.
In the area of the chip shown in fig. 3, a plurality of VCO areas are provided, illustrated by blocks (310, 320, 330 and 340), respectively.
Taking block 310 as an example, 2 bump pads (shown as 350 and 352) should be placed according to the default arrangement rules of bump pads. Since block 310 is occupied by a VCO, the corresponding chip surface area cannot be bumped. Moreover, because there is a constraint on the pitch of the adjacent bump pads, the pitch of the adjacent bump pads is not less than a specified threshold, and an attempt to adjust bump pads 350 and bump pads 352 cannot find a suitable position on the surface layer of the chip. In case that the placement requirements of the bump pads are in conflict with those of the VCO corresponding area, the placement requirements of the VCO corresponding area are preferentially satisfied, thereby deleting the two bump pads (350 and 352) causing the conflict.
Similarly, the bump pads need to be deleted or not placed in the corresponding surface areas of the boxes (320, 330, and 340) where the VCO is located.
Fig. 4 shows a flow chart of a chip design according to an embodiment of the application.
The chip design flow shown in fig. 4 is applied after, for example, a layout (Floorplan) design. One or more circuit cells of the designed chip are laid out (410). From among the electrical units that complete the layout, a circuit unit that is sensitive to the influence (e.g., pressure) caused by the bumps is selected. For example, a PLL unit, an analog-to-digital conversion unit, a radio frequency unit, or other analog circuit unit is selected. The circuit elements that are sensitive to the selected impact on the bumps are marked with their sensitive areas (420). For example, for PLL units, VCO regions are labeled where pressure is sensitive, for radio frequency units, where the receiver and transmitter are located, for analog to digital conversion units, where the sampling circuits are located, etc. In addition to being sensitive to pressure, some analog circuits are sensitive to disturbances in signal transmission or to temperature changes caused by current thermal effects. Still alternatively, in a chip, e.g. of a 3D structure, the sensitive area is present in one or more layers of the 3D structure.
With continued reference to fig. 4, a bump pad (430) is placed in a surface region of the chip. The bump pads are provided in plural, and are typically placed in an array form at equal intervals on the chip surface. For the one or more bumped pads placed, it is identified whether they are located in the corresponding areas of the die surface as noted in step 420 (440). The corresponding region of the sensitive region on the surface layer of the chip is, for example, a region formed by projecting the sensitive region on the surface layer of the chip with respect to the surface layer on which the bump pad is placed. The sensitive area may have the same size and shape as its corresponding area in the surface layer, or the same shape may be scaled but different sizes. For a chip of a 3D structure, the sum of areas formed by projection of the sensitive area of each layer (or a plurality of layers adjacent to the surface layer) of the 3D structure on the surface layer is taken as the sensitive area of the chip of the 3D structure on the corresponding area of the surface layer.
For the bump pad located in the corresponding area of the sensitive area, the bump pad is moved away from the sensitive area by adjusting the position of the bump pad, or the bump pad is deleted (450). For example, the sensitive area is determined to be at the center of the corresponding area of the chip surface, the position of the bump pad is changed in a direction away from the center with respect to the center, or the bump pad is moved in a direction away from the center on a line connecting the bump pad and the center. Still alternatively, the bump pad is moved in a direction parallel to the long or short sides of the paper surface of fig. 1 to 3, and the bump pad is moved away from the center. If the bump pad can be found by moving the bump pad, so that the bump pad is separated from the sensitive area in the corresponding area of the chip surface, and other constraint conditions of the chip design are not violated (for example, the distance between the bump pad and other bump pads is not smaller than a specified threshold), the bump pad is placed at the found position. If the positions meeting all the constraint conditions cannot be found to place the bump disc, deleting the bump disc. As yet another example, for a bump pad located in a corresponding area of the sensitive area, the bump pad and surrounding bump pad or pads are moved in their entirety to find a suitable location for placement of the bump pad. Still alternatively, for a bump pad where a suitable placement location cannot be found, it is temporarily marked as to be deleted, instead of deleting the bump pad, and the process goes to step 440, and other bump pads located in the surface area corresponding to the sensitive area are processed.
After step 450, turning to step 440, other bumped pads located in the corresponding surface area of the sensitive area are processed. If there is no bump pad on the surface area corresponding to the sensitive area, turning to step 460, RDL (redistribution layer) design is performed to establish connection between the bump pad and each electrical component (circuit unit).
Optionally, in step 440, if there are some bumped discs marked as to-be-deleted, after other bumped discs are placed in place, a suitable location is again found for those bumped discs marked as to-be-deleted by the process. If the proper position still cannot be found, the bump pads are deleted.
According to the embodiment of the application, the corresponding areas of the sensitive areas are identified in the surface layer provided with the salient points by identifying the sensitive areas in one or more layers in the chip, and the salient point disc is prevented from being placed in the corresponding areas, so that the influence of the salient point disc on the sensitive areas in the chip is reduced or even eliminated, and the success rate and the yield of chip flow are improved.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A Bump (Bump) disk layout method in an integrated circuit design, comprising:
placing a circuit unit;
selecting one or more circuit units sensitive to the influence of the bump pad from the placed circuit units;
acquiring one or more sensitive areas where the one or more circuit units are located;
placing a bump disc on the surface layer of the designed integrated circuit;
identifying one or more bump pads located in corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit; and
and adjusting the positions of the one or more bump pads to be away from the corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit.
2. The method of claim 1, further comprising:
if the position of the first bump disc, which enables the first bump disc to leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and does not violate the constraint condition of the design of the integrated circuit, cannot be found, the first bump disc is deleted;
wherein the constraint includes that the pitch of adjacent bump pads is not less than a specified threshold.
3. The method of claim 1 or 2, further comprising:
for a first bump pad positioned in a corresponding area of a first sensitive area on the surface layer of the integrated circuit, determining the center of the first sensitive area in the first corresponding area of the surface layer of the integrated circuit;
the position of the first bump pad is changed in a direction away from the center of the first corresponding region such that the first bump pad is separated from the first corresponding region.
4. The method of claim 1, further comprising:
if the position of the first bump disc, which enables the first bump disc to leave the corresponding area of the one or more sensitive areas on the surface layer of the integrated circuit and does not violate the constraint condition of the design of the integrated circuit, cannot be found, the first bump disc is marked as a state to be deleted; and
adjusting the positions of other bump pads except the first bump pad in the one or more bump pads to enable the other bump pads to leave the corresponding areas of the one or more sensitive areas on the surface layer of the integrated circuit;
wherein the constraint includes that the pitch of adjacent bump pads is not less than a specified threshold.
5. The method of claim 4, further comprising:
and deleting all the salient point discs marked as the state to be deleted.
6. The method of claim 5, wherein
The one or more sensitive areas are areas where VCOs of the PLL unit are located.
7. The method of claim 1 or 2, further comprising:
RDL design is performed to establish a connection between the bump pad and the circuit unit.
8. The method according to claim 1 or 2, wherein
The one or more sensitive areas are corresponding areas of the surface layer of the integrated circuit, and are areas obtained by projecting the one or more sensitive areas onto the surface layer of the designed integrated circuit.
9. The method of claim 8, wherein
The one or more sensitive areas are located at each layer of the integrated circuit having the 3D structure or at multiple layers adjacent to the surface layer.
10. A computer comprising a memory, a processor and a program stored on the memory and executable on the processor, wherein the processor, when executing the program, implements a Bump (Bump) disk layout method in an integrated circuit design as claimed in any one of claims 1-9.
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| CN201811613847.1A CN111400988B (en) | 2018-12-27 | 2018-12-27 | Bump (Bump) pad layout method for integrated circuit chip |
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| CN201811613847.1A CN111400988B (en) | 2018-12-27 | 2018-12-27 | Bump (Bump) pad layout method for integrated circuit chip |
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| CN111400988B true CN111400988B (en) | 2023-08-22 |
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