CN112638034A - Electronic device, mainboard thereof and packaging system module - Google Patents
Electronic device, mainboard thereof and packaging system module Download PDFInfo
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- CN112638034A CN112638034A CN201910905081.2A CN201910905081A CN112638034A CN 112638034 A CN112638034 A CN 112638034A CN 201910905081 A CN201910905081 A CN 201910905081A CN 112638034 A CN112638034 A CN 112638034A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/184—Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
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Abstract
The electronic device comprises an electronic device, a mainboard and a system packaging module, wherein the system packaging module comprises a module substrate, a plurality of first pins and a plurality of second pins; the module substrate comprises a module substrate surface, wherein the module substrate surface comprises a first pin configuration area and a second pin configuration area, and the second pin configuration area surrounds the first pin configuration area; the first pins are arranged in the first pin configuration area, wherein a first pin space exists between two adjacent first pins; the second pins are arranged in the second pin arrangement area, wherein a second pin space exists between two adjacent second pins, and the first pin space is larger than the second pin space. The invention can use a single mainboard for system packaging modules with different designs, thereby greatly reducing the development cost of products, and providing higher structural strength and increasing the reliability by the dense arrangement of the second pins of the outer ring.
Description
Technical Field
The present invention relates to a system packaging module, a motherboard and an electronic device, and more particularly, to a system packaging module, a motherboard and an electronic device with high versatility.
Background
The pin design of the conventional system packaging module and the contact design of the corresponding motherboard are developed according to the requirements of specific products, and a single motherboard cannot be used for system packaging modules with different designs. This results in an excessive production cost of the product.
Therefore, it is desirable to provide an electronic device, a motherboard thereof and a packaging system module to solve the above problems.
Disclosure of Invention
Embodiments of the present invention provide a system in package module to solve the problems of the prior art, the system in package module includes a module substrate, a plurality of first pins and a plurality of second pins; the module substrate comprises a module substrate surface, wherein the module substrate surface comprises a first pin configuration area and a second pin configuration area, and the second pin configuration area surrounds the first pin configuration area; the first pins are arranged in the first pin configuration area, wherein a first pin space exists between two adjacent first pins; the second pins are arranged in the second pin arrangement area, wherein a second pin space exists between two adjacent second pins, and the first pin space is larger than the second pin space.
In one embodiment, the ratio between the first lead pitch and the second lead pitch is 1.05: 1.
in an embodiment, the system in package module further includes a power supply unit, a ground unit, and a general purpose input/output unit, the first pin layout area includes a common area and a non-common area, the non-common area surrounds the common area, the first pins include a plurality of common pins and a plurality of non-common pins, the common pins are disposed in the common area, the non-common pins are disposed in the non-common area, and the common pins are coupled to the power supply unit, the ground unit, and the general purpose input/output unit.
In one embodiment, the system in package module further includes an inter-layer high speed interface unit coupled to the non-shared pins.
In one embodiment, the system in package module further includes an outer layer high speed interface unit coupled to at least a portion of the second pins, wherein the outer layer high speed interface unit is different from the inner layer high speed interface unit.
In one embodiment, the first pins are arranged in a matrix in a first axial direction and a second axial direction, the first axial direction is perpendicular to the second axial direction, the second pins are arranged in a matrix in a third axial direction and a fourth axial direction, the third axial direction is perpendicular to the fourth axial direction, and an included angle between the first axial direction and the third axial direction is 45 degrees.
In one embodiment, the second lead disposing area includes a module identification area, and an identification distance exists between two adjacent second leads in the module identification area, and the identification distance is greater than the second lead distance.
In one embodiment, the second pins include a first pin row, a second pin row and a third pin row, the second pin row is located between the first pin row and the third pin row, and the module identification area is located in one of the first pin row, the second pin row and the third pin row.
In an embodiment, the present invention further provides a motherboard, the motherboard including a motherboard substrate, a plurality of first contacts and a plurality of second contacts; the motherboard substrate comprises a motherboard substrate surface, the motherboard substrate surface comprises a first contact configuration area and a second contact configuration area, and the second contact configuration area surrounds the first contact configuration area; the first contacts are arranged in the first contact arrangement area, wherein a first contact distance exists between every two adjacent first contacts; the second contacts are arranged in the second contact arrangement area, wherein a second contact interval exists between every two adjacent second contacts, and the first contact intervals are larger than the second contact intervals.
In one embodiment, the first contacts are arranged in a matrix in a first axial direction and a second axial direction, the first axial direction is perpendicular to the second axial direction, the second contacts are arranged in a matrix in a third axial direction and a fourth axial direction, the third axial direction is perpendicular to the fourth axial direction, and an included angle between the first axial direction and the third axial direction is 45 degrees.
In one embodiment, the second contact arrangement area includes a board identification area, and a third contact pitch exists between two adjacent second contacts in the board identification area, and the third contact pitch is greater than the second contact pitch.
In one embodiment, the second contacts include a first contact row, a second contact row and a third contact row, the second contact row is located between the first contact row and the third contact row, and the motherboard identification area is located in one of the first contact row, the second contact row and the third contact row.
In an embodiment, the present invention further provides an electronic device, which includes one of a first system in package module and a second system in package module, and a motherboard in a selectable manner; the motherboard comprises a motherboard substrate, a plurality of first contacts and a plurality of second contacts, wherein the motherboard substrate comprises a motherboard substrate surface, the motherboard substrate surface comprises a first contact configuration area and a second contact configuration area, the second contact configuration area surrounds the first contact configuration area, the first contacts are arranged in the first contact configuration area, a first contact interval exists between every two adjacent first contacts, the second contacts are arranged in the second contact configuration area, a second contact interval exists between every two adjacent second contacts, the first contact intervals are larger than the second contact intervals, and the size of the first system packaging module is smaller than that of the second system packaging module.
In one embodiment, the first SoC module includes a first module substrate, a plurality of first leads and a plurality of second leads; the first module substrate comprises a first module substrate surface, the first module substrate surface comprises a first pin configuration area and a second pin configuration area, and the second pin configuration area surrounds the first pin configuration area; the first pins are arranged in the first pin configuration area, wherein a first pin space exists between two adjacent first pins; the second pins are arranged in the second pin arrangement area, wherein a second pin space exists between two adjacent second pins, wherein the first pin space is larger than the second pin space, the first pins are suitable for being connected with the first contacts, and the second pins are suitable for being connected with partial second contacts.
In one embodiment, the second SoC module includes a second module substrate, a plurality of third leads and a plurality of fourth leads; the second module substrate comprises a second module substrate surface, the second module substrate surface comprises a third pin configuration area and a fourth pin configuration area, and the fourth pin configuration area surrounds the third pin configuration area; the third pins are arranged in the third pin configuration area, wherein a third pin space exists between two adjacent third pins; the fourth pins are arranged in the fourth pin arrangement area, wherein a fourth pin space exists between two adjacent fourth pins, wherein the third pin space is larger than the fourth pin space, the third pins are suitable for being connected with the first contacts, and the fourth pins are suitable for being connected with at least part of the second contacts.
In one embodiment, the size of the first lead arrangement area is equal to the size of the third lead arrangement area.
In an embodiment, the second lead arrangement area is smaller than the fourth lead arrangement area.
In an embodiment, the first soc module further includes a first power supply unit, a first ground unit, and a first general-purpose i/o unit, the first pin layout area includes a first common area and a first non-common area, the first non-common area surrounds the first common area, the first pins include a plurality of first common pins and a plurality of first non-common pins, the first common pins are disposed in the first common area, the first non-common pins are disposed in the first non-common area, and the first common pins are coupled to the first power supply unit, the first ground unit, and the first general-purpose i/o unit.
In an embodiment, the second soc module further includes a second power supply unit, a second ground unit, and a second general-purpose i/o unit, the third pin layout area includes a second common area and a second non-common area, the second non-common area surrounds the second common area, the third pins include a plurality of second common pins and a plurality of second non-common pins, the second common pins are disposed in the second common area, the second non-common pins are disposed in the second non-common area, and the second common pins are coupled to the second power supply unit, the second ground unit, and the second general-purpose i/o unit.
In one embodiment, the first SoC module further includes a first high speed interface unit coupled to the first non-shared pin, the first high speed interface unit including a first number of high speed interface channels, the second SoC module further includes a second high speed interface unit coupled to the second non-shared pin, the second high speed interface unit including a second number of high speed interface channels, the second number of high speed interface channels being greater than the first number of high speed interface channels.
The electronic device of the embodiment of the invention can be universally used for system packaging modules (such as a first system packaging module and a second system packaging module) with different designs by a single mainboard. Therefore, the development cost of the product can be greatly reduced. In addition, in the embodiment of the invention, the second lead arrangement area surrounds the first lead arrangement area, and the first lead intervals are larger than the second lead intervals. In other words, the second leads of the outer ring are arranged densely, so that higher structural strength can be provided and reliability can be increased.
Drawings
Fig. 1 shows a system in package module (first system in package module) according to an embodiment of the present invention.
Fig. 2A shows a block diagram of a part of components of a system in package module (first system in package module) according to an embodiment of the present invention.
Fig. 2B shows another part of the component block diagram of the system in package module (first system in package module) according to the embodiment of the invention.
Fig. 2C shows a block diagram of a part of the system-in-package module (first system-in-package module) according to the embodiment of the present invention.
FIG. 3 shows a motherboard according to an embodiment of the present invention.
Fig. 4 shows an electronic device according to an embodiment of the invention.
Fig. 5 shows a detailed structure of a second system in package module according to an embodiment of the invention.
Fig. 6A shows a block diagram of a portion of the system-in-package module according to an embodiment of the invention.
FIG. 6B is a block diagram of another portion of the second system in package module according to an embodiment of the invention.
Description of the main component symbols:
s1 system packaging module and first system packaging module
11 first pin
11A common pin and first common pin
11B unshared pin and first unshared pin
12 second pin
12A first lead row
12B second lead row
12C third Pin column
13 Module substrate, first Module substrate
131 first lead configuration area
131A common area, first common area
131B non-common area, first non-common area
132 second lead configuration region
133 module identification region, first module identification region
139 module substrate surface, first module substrate surface
141 power supply unit, first power supply unit
142 grounding unit and first grounding unit
143 general-purpose input/output unit, first general-purpose input/output unit
144 inner layer high-speed interface unit, first high-speed interface unit
145 outer layer high-speed interface unit
d11 first lead spacing
d12 second lead spacing
d13 identification pitch, first identification pitch
X1 first axial direction
Y1 second axial direction
Third axial direction of X2
Y2 fourth axial direction
M mainboard
31 first contact
32 second contact
32A first contact array
32B second contact array
32C third contact array
33 host base material
331 first contact arrangement area
332 second contact arrangement region
333 host identification area
339 host substrate surface
d31 first contact spacing
d32 second contact spacing
d33 third contact spacing
S2 second system packaging module
21 third pin
21A second common pin
21B second unshared pin
22 fourth pin
22A fourth Pin column
22B fifth Pin column
22C sixth pin row
23 second Module substrate
231 third lead arrangement area
231A second common area
231B second unshared area
232 fourth lead configuration area
233 second module identification area
239 second module substrate surface
241 second power supply unit
242 second ground unit
243 second general-purpose input/output unit
244 second high speed interface unit
d21 third lead spacing
d22 fourth lead spacing
d23 second recognition pitch
Detailed Description
Referring to fig. 1, a system in package module (first system in package module) S1 according to an embodiment of the present invention includes a module substrate (first module substrate) 13, a plurality of first leads 11 and a plurality of second leads 12. The module substrate 13 includes a module substrate surface (first module substrate surface) 139, the module substrate surface 139 includes a first lead arrangement region 131 and a second lead arrangement region 132, and the second lead arrangement region 132 surrounds the first lead arrangement region 131. The first leads 11 are disposed in the first lead disposition region 131, wherein a first lead spacing d11 exists between two adjacent first leads 11. The second leads 12 are disposed in the second lead disposition region 132, wherein a second lead spacing d12 exists between two adjacent second leads 12, and the first lead spacing d11 is greater than the second lead spacing d 12.
In one embodiment, the ratio between the first lead pitch and the second lead pitch is 1.05: 1.
fig. 2A shows a partial component block diagram of the system packaging module S1 according to an embodiment of the present invention. With reference to fig. 1 and 2A, in an embodiment, the system-in-package module S1 further includes a power supply unit (a first power supply unit) 141, a ground unit (a first ground unit) 142, and a general-purpose input/output unit (a first general-purpose input/output unit) 143, the first pin layout area 131 includes a common area (a first common area) 131A and a non-common area (a first non-common area) 131B, and the non-common area 131B surrounds the common area 131A. Referring to fig. 1 again, the first pins 11 include a plurality of common pins 11A and a plurality of non-common pins 11B, the common pins 11A are disposed in the common area 131A, the non-common pins 11B are disposed in the non-common area 131B, and the common pins 11A are coupled to the power supply unit 141, the ground unit 142 and the general-purpose input/output unit 143.
Fig. 2B shows another partial block diagram of the system packaging module S1 according to the embodiment of the present invention. In one embodiment, the system in package module further includes an inner high speed interface unit (first high speed interface unit) 144, the inner high speed interface unit 144 is coupled to the non-common pins 11B.
Fig. 2C shows a block diagram of a part of the system packaging module S1 according to an embodiment of the present invention. In one embodiment, the system in package module S1 further includes an outer layer high speed interface unit 145, the outer layer high speed interface unit 145 being coupled to at least a portion of the second pins 12, wherein the outer layer high speed interface unit 145 is different from the inner layer high speed interface unit 144. In one embodiment, the inner high speed interface unit 144 may include a second generation PCIE interface and a third generation PCIE interface. The outer-layer high-speed interface unit 145 may include a fourth generation PCIE interface.
Referring again to fig. 1, in one embodiment, the first leads 11 are arranged in a matrix in a first axial direction X1 and a second axial direction Y1, the first axial direction X1 is perpendicular to the second axial direction Y1. The second leads 12 are arranged in a matrix in a third axial direction X2 and a fourth axial direction Y2, the third axial direction X2 is perpendicular to the fourth axial direction Y2, and an included angle between the first axial direction X1 and the third axial direction X2 is 45 degrees.
In one embodiment, the first lead spacing d11 can be 1.79mm, and the second lead spacing d12 can be 1.27 mm. In the third axial direction X2 and the fourth axial direction Y2, a pin spacing d11 'exists between two adjacent first pins 11, and the pin spacing d11' may be 2.54 mm.
Referring to fig. 1 again, in one embodiment, the second lead disposing region 132 includes a module identification region (first module identification region) 133, and an identification distance (first identification distance) d13 exists between two adjacent second leads 12 in the module identification region 133, and the identification distance d13 is greater than the second lead distance d 12.
Referring to fig. 1 again, in an embodiment, the second leads 12 include a first lead row 12A, a second lead row 12B and a third lead row 12C, the second lead row 12B is located between the first lead row 12A and the third lead row 12C, and the module identification area 133 is located in one of the first lead row 12A, the second lead row 12B and the third lead row 12C. In one embodiment, the first lead row 12A is adjacent to the first lead arrangement region 131, and the third lead row 12C is located at the outer edge of the second lead arrangement region 132. In this embodiment, the module identification area 133 is located in the third pin row 12C.
Referring to fig. 3, in an embodiment, the present invention further provides a motherboard M including a motherboard substrate 33, a plurality of first contacts 31 and a plurality of second contacts 32. The motherboard substrate 33 includes a motherboard substrate surface 339, and the motherboard substrate surface 339 includes a first contact arrangement region 331 and a second contact arrangement region 332, and the second contact arrangement region 332 surrounds the first contact arrangement region 331. The first contacts 31 are disposed in the first contact arrangement area 331, wherein a first contact spacing d31 exists between two adjacent first contacts 31. The second contacts 32 are disposed in the second contact arrangement region 332, wherein a second contact spacing d32 exists between two adjacent second contacts 32, and the first contact spacing d31 is greater than the second contact spacing d 32.
Referring to fig. 3, in an embodiment, the first contacts 31 are arranged in a matrix manner in a first axial direction X1 and a second axial direction Y1, the first axial direction X1 is perpendicular to the second axial direction Y1, the second contacts 32 are arranged in a matrix manner in a third axial direction X2 and a fourth axial direction Y2, the third axial direction X2 is perpendicular to the fourth axial direction Y2, and an included angle between the first axial direction X1 and the third axial direction X2 is 45 degrees.
Referring to fig. 3, in one embodiment, the second contact arrangement region 332 includes a board identification region 333, a third contact pitch d33 exists between two adjacent second contacts 32 in the board identification region 333, and the third contact pitch d33 is greater than the second contact pitch d 32.
In the embodiment of the present invention, the board identification region 333 corresponds to the module identification region 133, so that when the system on package module S1 is installed on the board M, the board identification region 333 and the module identification region 133 provide alignment functions.
In one embodiment, the second contacts 32 include a first contact row 32A, a second contact row 32B, and a third contact row 32C, the second contact row 32B is located between the first contact row 32A and the third contact row 32C, and the board identification area 333 is located in one of the first contact row 32A, the second contact row 32B, and the third contact row 32C.
Referring to fig. 4, in an embodiment, the present invention further provides an electronic device E, which optionally includes one of the first soc module S1 and a second soc module S2, and the motherboard M. The first SoC module S1 is smaller in size than the second SoC module S2.
In this embodiment, the details of the first system packaging module S1 are described above, and therefore are not described herein.
In this embodiment, the first leads 11 of the first system in package module S1 are adapted to connect to the first contacts 31, and the second leads 12 are adapted to connect to part of the second contacts 32, in conjunction with fig. 1, 3 and 4.
Fig. 5 shows a detailed structure of a second system in package module according to an embodiment of the invention. Referring to fig. 5, in this embodiment, the second system in package module S2 includes a second module substrate 23, a plurality of third leads 21 and a plurality of fourth leads 22. The second module substrate 23 includes a second module substrate surface 239, the second module substrate surface 239 includes a third lead placement region 231 and a fourth lead placement region 232, and the fourth lead placement region 232 surrounds the third lead placement region 231. The third leads 21 are disposed in the third lead disposition region 231, wherein a third lead spacing d21 exists between two adjacent third leads 21. The fourth leads 22 are disposed in the fourth lead disposing region 232, wherein a fourth lead spacing d22 exists between two adjacent fourth leads 22, wherein the third lead spacing d21 is greater than the fourth lead spacing d22, wherein the third leads 21 are adapted to connect with the first contacts 31, and the fourth leads 22 are adapted to connect with at least a portion of the second contacts 32.
With reference to fig. 1 and 5, in an embodiment, the size of the first lead disposing region 131 is equal to the size of the third lead disposing region 231. The second lead arrangement region 132 is smaller than the fourth lead arrangement region 232.
In the embodiment of the invention, the size of the first contact layout area 331 of the motherboard M is equal to the size of the first lead layout area 131 of the first system in package module S1. Similarly, the size of the first contact layout area 331 of the motherboard M is equal to the size of the third lead layout area 231 of the second system in package module S2.
Fig. 6A shows a partial component block diagram of the second system packaging module S2 according to an embodiment of the present invention. With reference to fig. 5 and 6A, in an embodiment, the second system-on-package module S2 further includes a second power supply unit 241, a second ground unit 242, and a second general-purpose input/output unit 243, the third pin arrangement region 231 includes a second common region 231A and a second non-common region 231B, the second non-common region 231B surrounds the second common region 231A, the third pins 21 include a plurality of second common pins 21A and a plurality of second non-common pins 21B, the second common pins 21A are disposed in the second common region 231A, the second non-common pins 21B are disposed in the second non-common region 231B, and the second common pins 21A are coupled to the second power supply unit 241, the second ground unit 242, and the second general-purpose input/output unit 243.
Referring to fig. 5 again, in one embodiment, the fourth lead disposing area 232 includes a second module identification area 233, a second identification distance d23 exists between two adjacent fourth leads 22 in the second module identification area 233, and the second identification distance d23 is greater than the fourth lead distance d 22.
Referring to fig. 5 again, in an embodiment, the fourth pins 22 include a fourth pin row 22A, a fifth pin row 22B and a sixth pin row 22C, the fifth pin row 22B is located between the fourth pin row 22A and the sixth pin row 22C, and the second module identification area 233 is located in one of the fourth pin row 22A, the fifth pin row 22B and the sixth pin row 22C. In this embodiment, the second module identification area 233 is located in the fifth pin row 22B.
With reference to fig. 2B and fig. 6B, in an embodiment, the first system in package module S1 includes a first high speed interface unit 144, the first high speed interface unit 144 is coupled to the first non-shared pin 11B, the first high speed interface unit 144 includes a first number of high speed interface channels, the second system in package module S2 further includes a second high speed interface unit 244, the second high speed interface unit 244 is coupled to the second non-shared pin 21B, the second high speed interface unit 244 includes a second number of high speed interface channels, and the second number of high speed interface channels is greater than the first number of high speed interface channels.
Referring to fig. 1, in an embodiment, the common area (first common area) 131A and/or the non-common area (first non-common area) 131B may include blank areas therein, and the disclosure does not limit the present invention.
Referring to fig. 5, in an embodiment, passive components may be disposed between the fourth pins 21 in the third pin disposing region 231, and the disclosure does not limit the present invention.
The electronic device of the embodiment of the invention can be universally used for system packaging modules (such as a first system packaging module and a second system packaging module) with different designs by a single mainboard. Therefore, the development cost of the product can be greatly reduced. In addition, in the embodiment of the invention, the second lead arrangement area surrounds the first lead arrangement area, and the first lead intervals are larger than the second lead intervals. In other words, the second leads of the outer ring are arranged densely, so that higher structural strength can be provided and reliability can be increased.
Although the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (20)
1. A system-in-package module, comprising:
the module substrate comprises a module substrate surface, wherein the module substrate surface comprises a first pin arrangement area and a second pin arrangement area, and the second pin arrangement area surrounds the first pin arrangement area;
the first pins are arranged in the first pin configuration area, wherein a first pin interval exists between every two adjacent first pins; and
the plurality of second pins are arranged in the second pin configuration area, wherein a second pin interval exists between two adjacent second pins, and the first pin interval is larger than the second pin interval.
2. The system in package module of claim 1, wherein a ratio between the first pin pitch and the second pin pitch is 1.05: 1.
3. the system-in-package module as claimed in claim 1, further comprising a power supply unit, a ground unit and a general purpose input/output unit, wherein the first pin layout area includes a common area and a non-common area, the non-common area surrounds the common area, the first pins include a plurality of common pins and a plurality of non-common pins, the common pins are disposed in the common area, the non-common pins are disposed in the non-common area, and the common pins are coupled to the power supply unit, the ground unit and the general purpose input/output unit.
4. The system in package module of claim 3, further comprising an inter-layer high speed interface unit coupled to the non-shared pins.
5. The system in package module of claim 4, further comprising an outer layer high speed interface unit coupled to at least a portion of the second pins, wherein the outer layer high speed interface unit is different from the inner layer high speed interface unit.
6. The system in package module of claim 1, wherein the first leads are arranged in a matrix in a first axial direction and a second axial direction, the first axial direction is perpendicular to the second axial direction, the second leads are arranged in a matrix in a third axial direction and a fourth axial direction, the third axial direction is perpendicular to the fourth axial direction, and the first axial direction and the third axial direction form an angle of 45 degrees.
7. The system in package module of claim 1, wherein the second lead layout area comprises a module identification area, and an identification distance exists between two adjacent second leads in the module identification area, the identification distance being greater than the second lead distance.
8. The system in package module of claim 7, wherein the second pins comprise a first pin row, a second pin row and a third pin row, the second pin row is located between the first pin row and the third pin row, and the module identification area is located in one of the first pin row, the second pin row and the third pin row.
9. A motherboard, comprising:
the motherboard substrate comprises a motherboard substrate surface, the motherboard substrate surface comprises a first contact configuration area and a second contact configuration area, and the second contact configuration area surrounds the first contact configuration area;
the first contacts are arranged in the first contact arrangement area, and a first contact distance exists between every two adjacent first contacts; and
the second contacts are arranged in the second contact arrangement area, a second contact interval exists between every two adjacent second contacts, and the first contact intervals are larger than the second contact intervals.
10. The host board of claim 9 wherein the first contacts are arranged in a matrix in a first axis and a second axis, the first axis being perpendicular to the second axis, the second contacts are arranged in a matrix in a third axis and a fourth axis, the third axis being perpendicular to the fourth axis, the first axis and the third axis being at an angle of 45 degrees.
11. The motherboard of claim 9, wherein the second contact layout area includes a motherboard identification area in which a third contact pitch exists between two adjacent second contacts, the third contact pitch being greater than the second contact pitch.
12. The motherboard of claim 11 wherein the second contacts include a first contact row, a second contact row, and a third contact row, the second contact row being between the first contact row and the third contact row, the motherboard identification area being located in one of the first contact row, the second contact row, and the third contact row.
13. An electronic device optionally including one of a first system in package module and a second system in package module, the electronic device further comprising:
a motherboard, the motherboard includes a motherboard substrate, a plurality of first contacts and a plurality of second contacts, wherein the motherboard substrate includes a motherboard substrate surface, the motherboard substrate surface includes a first contact configuration area and a second contact configuration area, the second contact configuration area surrounds the first contact configuration area, the first contacts are disposed in the first contact configuration area, a first contact spacing exists between two adjacent first contacts, the second contacts are disposed in the second contact configuration area, wherein a second contact spacing exists between two adjacent second contacts, wherein the first contact spacing is larger than the second contact spacing,
wherein the first system in package module is smaller in size than the second system in package module.
14. The electronic device of claim 13, wherein the first system in package module comprises:
a first module substrate, wherein the first module substrate comprises a first module substrate surface, the first module substrate surface comprises a first pin arrangement area and a second pin arrangement area, and the second pin arrangement area surrounds the first pin arrangement area;
the first pins are arranged in the first pin configuration area, wherein a first pin interval exists between every two adjacent first pins; and
a plurality of second pins arranged in the second pin arrangement area, wherein a second pin space exists between two adjacent second pins, wherein the first pin space is larger than the second pin space,
the first pins are suitable for being connected with the first contacts, and the second pins are suitable for being connected with the second contacts of the connecting part.
15. The electronic device of claim 14, wherein the second system in package module comprises:
a second module substrate, wherein the second module substrate comprises a second module substrate surface, the second module substrate surface comprises a third pin arrangement area and a fourth pin arrangement area, and the fourth pin arrangement area surrounds the third pin arrangement area;
the plurality of third pins are arranged in the third pin configuration area, wherein a third pin space exists between two adjacent third pins; and
a plurality of fourth leads disposed in the fourth lead disposition region, wherein a fourth lead spacing exists between two adjacent fourth leads, wherein the third lead spacing is greater than the fourth lead spacing,
the third pins are suitable for being connected with the first contacts, and the fourth pins are suitable for being connected with at least part of the second contacts.
16. The electronic device of claim 15, wherein the first lead arrangement area has a size equal to that of the third lead arrangement area.
17. The electronic device of claim 16, wherein the second lead arrangement area is smaller in size than the fourth lead arrangement area.
18. The electronic device of claim 17, wherein the first system in package module further comprises a first power supply unit, a first ground unit, and a first general-purpose i/o unit, the first pin layout area includes a first common area and a first non-common area, the first non-common area surrounds the first common area, the first pins include a plurality of first common pins and a plurality of first non-common pins, the first common pins are disposed in the first common area, the first non-common pins are disposed in the first non-common area, and the first common pins are coupled to the first power supply unit, the first ground unit, and the first general-purpose i/o unit.
19. The electronic device of claim 18, wherein the second system in package module further comprises a second power supply unit, a second ground unit, and a second general purpose input/output unit, the third pin layout area includes a second common area and a second non-common area, the second non-common area surrounds the second common area, the third pins include a plurality of second common pins and a plurality of second non-common pins, the second common pins are disposed in the second common area, the second non-common pins are disposed in the second non-common area, and the second common pins are coupled to the second power supply unit, the second ground unit, and the second general purpose input/output unit.
20. The system in package module of claim 19, wherein the first system in package module further comprises a first high speed interface unit coupled to the first non-shared pin, the first high speed interface unit comprising a first number of high speed interface channels, the second system in package module further comprising a second high speed interface unit coupled to the second non-shared pin, the second high speed interface unit comprising a second number of high speed interface channels, the second number of high speed interface channels being greater than the first number of high speed interface channels.
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