CN110911384A - Embedded passive bridge chip and application thereof - Google Patents
Embedded passive bridge chip and application thereof Download PDFInfo
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- CN110911384A CN110911384A CN201911318403.XA CN201911318403A CN110911384A CN 110911384 A CN110911384 A CN 110911384A CN 201911318403 A CN201911318403 A CN 201911318403A CN 110911384 A CN110911384 A CN 110911384A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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Abstract
The invention discloses an embedded passive bridging chip, which is internally provided with at least one U-shaped conductive connecting wire, wherein the left end and the right end of the U-shaped conductive connecting wire are respectively connected to the same external chip or two external chips. The invention can realize the interconnection between the chips, the interconnection between the chips and the packaging substrate or the PCB, and the high-density connection of all layers in the packaging substrate; different line widths can be adopted to meet the transmission requirements of different signals; no additional routing design is required.
Description
Technical Field
The invention belongs to the technical field of integrated circuit packaging interconnection, and particularly relates to an embedded passive bridge chip and application thereof.
Background
As integrated circuit fabrication technology expands towards smaller process nodes, designing an entire system on a single integrated circuit chip becomes increasingly difficult to implement, and is time consuming and expensive, a solution for packaging multiple chips together to perform the system's functions is emerging, such packaging solutions containing multiple chips sometimes being referred to as System In Package (SiP), multi-chip module (MCM), or multi-chip package. As system complexity increases, conventional packages may require more complex routing layer designs, and may even exceed maximum routing layer design capabilities.
Therefore, an embedded passive bridge chip and applications thereof are urgently needed.
Disclosure of Invention
To address the deficiencies of the prior art, the present invention provides an embedded passive bridge chip that provides ultra-high density interconnections between chips within a package, typically including minimal length traces, that facilitates significantly reducing signal transmission losses and directly improving performance.
In order to solve the technical problems, the invention provides the following technical scheme:
the invention provides an embedded passive bridge chip, wherein at least one U-shaped conductive connecting line is arranged inside the embedded passive bridge chip, and the left end and the right end of the U-shaped conductive connecting line are respectively connected to the same external chip or two external chips.
As a preferred technical solution of the present invention, at least one row of u-shaped conductive connecting lines is distributed from top to bottom, and the left and right ends of the upper row of u-shaped conductive connecting lines are respectively located in the left and right ends of the next row of u-shaped conductive connecting lines; each row is distributed with at least one U-shaped conductive connecting wire, the left ends of any two adjacent U-shaped conductive connecting wires in each row are arranged in a staggered mode, and the right ends of any two adjacent U-shaped conductive connecting wires in each row are arranged in a staggered mode.
As a preferred technical scheme of the invention, the U-shaped conductive connecting lines are distributed in at least one row from left to right, any two adjacent U-shaped conductive connecting lines are connected, the upper surface of the left end of the right U-shaped conductive connecting line is connected with the lower surface of the right end of the left U-shaped conductive connecting line, and the lower core connecting lines are arranged at the left end of the leftmost U-shaped conductive connecting line, the right end of the rightmost U-shaped conductive connecting line and the lower surfaces of the connecting parts of any two adjacent U-shaped conductive connecting lines; each row is distributed with at least one U-shaped conductive connecting wire, the left ends of any two adjacent U-shaped conductive connecting wires in each row are arranged in a staggered mode, and the right ends of any two adjacent U-shaped conductive connecting wires in each row are arranged in a staggered mode.
As a preferred technical solution of the present invention, the embedded passive bridge chip has a through-silicon via vertically penetrating through the embedded passive bridge chip to form at least one conductive connection line, and the top of each conductive connection line is connected to two external chips through solder bumps.
As a preferred technical solution of the present invention, each u-shaped conductive connection wire includes a second chip connecting member, the second chip connecting member includes a second chip conductive layer and two chip micro-through holes, and the two chip micro-through holes are disposed on upper surfaces of left and right ends of the second chip conductive layer.
As a preferred technical scheme of the invention, each U-shaped conductive connecting wire comprises a second chip connecting piece and a first chip connecting piece, and the upper surfaces of the left end and the right end of the second chip connecting piece are respectively connected with at least one first chip connecting piece in sequence; the first chip connecting piece comprises a first chip conducting layer and a chip micro through hole, and the chip micro through hole is formed in the upper surface of the first chip conducting layer; the second chip connecting piece comprises a second chip conducting layer and two chip micro through holes, and the two chip micro through holes are formed in the upper surfaces of the left end and the right end of the second chip conducting layer.
As a preferred technical scheme of the invention, the lower surfaces of the left end and/or the right end of the bottom row of U-shaped conductive connecting lines are/is also connected with a first chip connecting piece.
As a preferred embodiment of the present invention, when the u-shaped conductive connecting lines are distributed in multiple rows from top to bottom, the second chip conductive layers of two adjacent rows of u-shaped conductive connecting lines are arranged by crossing the power/ground layer and the signal layer.
As a preferred technical solution of the present invention, the present invention further provides a package structure having an embedded passive bridge chip on a surface of a package substrate, comprising a first external chip, a second external chip, an embedded passive bridge chip, a package substrate, and a PCB, wherein the embedded passive bridge chip is embedded in the package substrate, at least one "u" -shaped conductive connection line is disposed inside the embedded passive bridge chip, at least one row of the "u" -shaped conductive connection lines is distributed from top to bottom, and left and right ends of a previous row of the "u" -shaped conductive connection lines are respectively located in left and right ends of a next row of the "u" -shaped conductive connection lines; each row is distributed with at least one U-shaped conductive connecting wire, the left ends of any two adjacent U-shaped conductive connecting wires in each row are arranged in a staggered manner, and the right ends of any two adjacent U-shaped conductive connecting wires in each row are arranged in a staggered manner;
the left end and the right end of the U-shaped conductive connecting line are respectively connected with the lower surfaces of the first outer chip and the second outer chip through solder bumps; conductive connecting lines are arranged inside the embedded passive bridge chip and positioned on two sides of the U-shaped conductive connecting line, the tops of the conductive connecting lines on the two sides are respectively connected with the lower surfaces of the first outer chip and the second outer chip through soldering tin bumps, and the bottoms of the conductive connecting lines on the two sides are connected with the PCB sequentially through the first substrate connecting line and the lower soldering tin ball; and a cavity is arranged at any side of the embedded passive bridge chip.
As a preferred technical solution of the present invention, the present invention further provides a package structure having an embedded passive bridge chip on a surface of a package substrate, comprising a first external chip, a second external chip, an embedded passive bridge chip, a package substrate, and a PCB, wherein the embedded passive bridge chip is embedded in the package substrate, at least one "u" -shaped conductive connection line is disposed inside the embedded passive bridge chip, and left and right ends of the "u" -shaped conductive connection line are respectively connected to lower surfaces of the first external chip and the second external chip by bump solder; the lower surfaces of the left end and/or the right end of the U-shaped conductive connecting line are respectively connected with the PCB board through the first substrate connecting line and the lower solder ball in sequence; and a cavity is arranged at any side of the embedded passive bridge chip.
The invention has the beneficial effects that: the invention can realize the interconnection between the chips, the interconnection between the chips and the packaging substrate or the PCB, and the high-density connection of all layers in the packaging substrate; different line widths can be adopted to meet the transmission requirements of different signals; no additional routing design is required.
According to the invention, the silicon through hole directly transmits power or data signals to the chip through the embedded passive bridge chip, and signals can be provided to the internal interconnection of the embedded passive bridge chip from any layer of the PCB or the packaging substrate.
According to the invention, signals/energy can be electrically coupled to the embedded passive bridge chips through the conductive layer of the packaging substrate or the PCB, or can be coupled to another embedded passive bridge chip through the conductive layer of one embedded passive bridge chip, and the signals/energy of all the embedded passive bridge chips can be transmitted only by connecting one embedded passive bridge chip.
The cavity is designed near the embedded passive bridge chip so as to reduce the thermal stress on the embedded passive bridge chip and reduce the difference between the thermal expansion coefficients of the embedded passive bridge chip and the packaging substrate.
Drawings
Fig. 1 is a schematic structural diagram of an embedded passive bridge chip according to the present invention.
Fig. 2 is a schematic diagram illustrating a distribution of solder bumps in an embedded passive bridge chip according to the present invention.
Fig. 3 is a schematic structural diagram of a package structure having an embedded passive bridge chip on a surface of a package substrate according to a first embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a package structure having an embedded passive bridge chip on a surface of a package substrate according to a second embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a left embedded passive bridge chip in a package structure having an embedded passive bridge chip on a surface of a package substrate according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "left", "right", and the like, which refer to the orientation or positional relationship based on the drawings of the specification, are used only for convenience of description and simplification of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
In the description of the present invention, it is to be noted that the terms "connected" and "connected" are electrically connected unless otherwise specifically stated or limited. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In order to achieve the above objects, one embodiment of the present invention provides an embedded passive bridge chip, wherein a plurality of u-shaped conductive connection lines 304 are disposed inside the embedded passive bridge chip 120, and left and right ends of the u-shaped conductive connection lines 304 are respectively connected to one external chip or two external chips.
Specifically, as shown in fig. 1, the present embodiment provides an embedded passive bridge chip, where the embedded passive bridge chip 120 includes 5 chip dielectric layers stacked in sequence from top to bottom, and the 5 chip dielectric layers include a first chip dielectric layer 120-1, a second chip dielectric layer 120-2, a third chip dielectric layer 120-3, a fourth chip dielectric layer 120-4, and a fifth chip dielectric layer 120-5;
three rows of U-shaped conductive connecting lines 304 are distributed from top to bottom, including a first row of U-shaped conductive connecting lines 304, a second row of U-shaped conductive connecting lines 304, and a third row of U-shaped conductive connecting lines 304, each row having 24U-shaped conductive connecting lines 304; each U-shaped conductive connection line 304 in the first row comprises a second chip connection element and two first chip connection elements, wherein the upper surfaces of the left and right ends of the second chip connection element are respectively connected with one first chip connection element, the second chip connection element is located in the second chip dielectric layer 120-2, and the first chip connection element is located in the first chip dielectric layer 120-1;
each U-shaped conductive connection line 304 in the second row comprises a second chip connection element and four first chip connection elements, wherein the upper surfaces of the left and right ends of the second chip connection element are respectively connected with two first chip connection elements in sequence, the second chip connection element is positioned in the third chip dielectric layer 120-3, two chip connection elements are positioned in the second chip dielectric layer 120-2, and the other two chip connection elements are positioned in the first chip dielectric layer 120-1;
the third row of each U-shaped conductive connecting wire 304 comprises a second chip connecting piece and six first chip connecting pieces, wherein the upper surfaces of the left end and the right end of each second chip connecting piece are respectively connected with three first chip connecting pieces in sequence, the second chip connecting pieces are positioned in a fourth chip dielectric layer 120-4, two of the chip connecting pieces are positioned in a third chip dielectric layer 120-3, the other two chip connecting pieces are positioned in a second chip dielectric layer 120-2, and the rest two chip connecting pieces are positioned in a first chip dielectric layer 120-1; the lower surface of the left end of each U-shaped conductive connecting line 304 in the third row is also connected with a first chip connecting piece;
the first chip connecting piece comprises a first chip conducting layer 104 and a chip micro through hole 102, wherein the chip micro through hole 102 is arranged on the upper surface of the first chip conducting layer 104; the second chip connecting piece comprises a second chip conducting layer 106 and two chip micro through holes 102, wherein the two chip micro through holes 102 are arranged on the upper surfaces of the left end and the right end of the second chip conducting layer 106;
the right and left ends of the u-shaped conductive connection line 304 are connected to the first external chip 101 and the second external chip 103, respectively, by solder bumps 107.
In this embodiment, three rows of u-shaped conductive connection lines 304 are distributed from top to bottom, and the second chip conductive layer of two adjacent rows of u-shaped conductive connection lines 304 is formed by crossing the power/ground layer and the signal layer.
As shown in fig. 2, in this embodiment, 24 u-shaped conductive connecting lines 304 are distributed in each row, the left ends of any two adjacent u-shaped conductive connecting lines 304 in each row are staggered, and the right ends of any two adjacent u-shaped conductive connecting lines 304 in each row are staggered. In the present embodiment, the solder bumps are micro bumps and are distributed in a staggered manner, thereby increasing the bump density. The size of the bonding pads is obviously smaller than that of the traditional bonding pads, the space between the bonding pads is also obviously smaller than that of the traditional bonding pads, the size of the bonding pads is small, the space between the bonding pads is short, the packaging density can be improved, and the packaging volume is reduced
As shown in fig. 1, the embedded passive bridge chip 120 provided in this embodiment further has through-silicon vias 108 vertically penetrating through the embedded passive bridge chip 120 to form a set of conductive connection lines 302, and the top of each set of conductive connection lines 302 is connected to the first external chip 101 and the second external chip 103 through solder bumps 107, respectively.
In order to improve the performance of the product, the aperture of the chip micro-via 102 in this embodiment is gradually reduced from top to bottom.
As shown in fig. 3, in order to further optimize the implementation effect of the present invention, in another embodiment of the present invention, the present embodiment provides a package structure with an embedded passive bridge chip on a surface of a package substrate, including a first external chip 101, a second external chip 103, the package substrate 100, an embedded passive bridge chip 120, and a PCB 140, where the embedded passive bridge chip 120 is embedded in the package substrate 100, where a position of the embedded passive bridge chip 120 in the package substrate 100 may be designed according to specific situations, an upper surface of the embedded passive bridge chip 120 may be selected to be flush with an upper surface of the package substrate 100, a lower surface of the embedded passive bridge chip 120 may be selected to be flush with a lower surface of the package substrate 100, and the embedded passive bridge chip 120 may be selected to be integrally embedded in the package substrate 100 and both of the upper surface and the lower surface are located inside an upper surface and a lower surface of the package substrate 100, for the convenience of understanding, the upper surface of the embedded passive bridge chip 120 is flush with the upper surface of the package substrate 100;
in addition, a plurality of "u" -shaped conductive connecting lines 304 are arranged inside the embedded passive bridge chip 120, and the left and right ends of the "u" -shaped conductive connecting lines 304 are respectively connected with the lower surfaces of the first external chip 101 and the second external chip 103 through solder bumps 107; conductive connecting lines 302 are arranged inside the embedded passive bridge chip 120 and positioned on two sides of the U-shaped conductive connecting line 304, the tops of the conductive connecting lines 302 on the two sides are respectively connected with the lower surfaces of the first external chip 101 and the second external chip 103 through solder bumps 107, and the bottoms of the conductive connecting lines 302 on the two sides are connected with the PCB 140 through a first substrate connecting line 306 and lower solder balls 309 in sequence; cavity 412 is provided on either side of embedded passive bridge chip 120. The u-shaped conductive connection lines 304 are distributed in the same manner as the first embodiment. The cavity is designed near the embedded passive bridge chip so as to reduce the thermal stress on the embedded passive bridge chip and reduce the difference between the thermal expansion coefficients of the embedded passive bridge chip and the packaging substrate.
In the embodiment, the second substrate connection lines 308 are further vertically disposed through the package base 100 inside the package substrate 100 and on the left and right sides of the embedded passive bridge chip, the top portions of the second substrate connection lines 308 on the left and right sides are respectively connected to the first outer chip 101 and the second outer chip 103 through the upper solder balls 105, and the bottom portions of the second substrate connection lines 308 on the left and right sides are respectively connected to the PCB 140 through the lower solder balls 309.
Specifically, the embedded passive bridge chip of the present embodiment is connected in three ways:
first, the first chip 101 may be coupled to the second chip 103 using an embedded passive bridge chip 120 embedded in the package substrate 100. The first chip 101 and the second chip 103 are mounted on the embedded passive bridge chip 120 by using solder bumps 107, and the embedded passive bridge chip is interconnected by using a conductive connection line 304 shaped like a Chinese character 'u';
second, the package substrate 100 and the PCB 140 may communicate with the first chip 101 and the second chip 103 through the embedded passive bridge chip 120. Signals of the packaging substrate and the PCB are connected with the embedded passive bridge chip through the first conductive adhesive 104, and the transmission of the signals to the first chip 101 and the second chip 103 is realized through the chip micro-through hole 102 and the chip conductor 106.
Third, vertical transmission may be achieved through the embedded passive bridge chip by providing signals or power to at least one chip through-silicon vias 108 in embedded passive bridge chip 120.
As shown in fig. 4, in order to further optimize the effect of the present invention, in another embodiment of the present invention, the embodiment provides a package structure with an embedded passive bridge chip on the surface of a package substrate, which comprises a first outer chip 101, a second outer chip 103, a package substrate 100, an embedded passive bridge chip 120 and a PCB 140, wherein the first outer chip 101 and the second outer chip 103 are distributed at intervals from left to right, the package substrate 100 comprises 4 substrate outer electric layers which are sequentially stacked from top to bottom, the 4 substrate electric layers comprise a first substrate dielectric layer 100-1, a second substrate dielectric layer 100-2, a third substrate dielectric layer 100-3 and a fourth substrate dielectric layer 100-4, and the embedded passive bridge chip 120 is embedded in the second substrate dielectric layer 100-2 and the third substrate dielectric layer 100-3 of the package substrate 100 at intervals from left to right;
a plurality of u-shaped conductive connecting lines 304 are disposed inside the embedded passive bridge chip 120, three rows of u-shaped conductive connecting lines 304 are distributed from left to right in the left embedded passive bridge chip 120, and one row of u-shaped conductive connecting lines 304 is distributed in the right embedded passive bridge chip 120.
The position of the embedded passive bridge chip 120 in the package substrate 100 may be designed according to specific situations, the upper surface of the embedded passive bridge chip 120 may be selected to be flush with the upper surface of the package substrate 100, the lower surface of the embedded passive bridge chip 120 may also be selected to be flush with the lower surface of the package substrate, the embedded passive bridge chip 120 may also be selected to be integrally embedded in the package substrate 100, and the upper surface and the lower surface of the embedded passive bridge chip 120 are respectively located at the inner sides of the upper surface and the lower surface of the package substrate 100.
The embedded passive bridge chip 120 on the left side realizes the connection between the first external chip 101 and the second external chip 103, and the connection between the first external chip 101 and the second external chip 103 and the package substrate respectively; the embedded passive bridge chip 120 on the right side realizes connection between two connection points in the second outer chip 103, connection between the second outer chip 103 and the next outer chip, and connection between the second outer chip and the package substrate.
As shown in fig. 5, the u-shaped conductive connection lines 304 of the embedded passive bridge chip 120 on the left side include a first row of u-shaped conductive connection lines 304, a second row of u-shaped conductive connection lines 304, and a third row of u-shaped conductive connection lines 304, the upper surfaces of the left ends of the second row of u-shaped conductive connection lines 304 are connected to the lower surface of the right end of the first row of u-shaped conductive connection lines 304, the upper surfaces of the left ends of the third row of u-shaped conductive connection lines 304 are connected to the lower surface of the right end of the second row of u-shaped conductive connection lines 304, the left ends of the first row of u-shaped conductive connection lines 304 and the lower surfaces of the right ends of the third row of u-shaped conductive connection lines 304 are provided with lower core connection lines, each row has at least one u-shaped conductive connection line 304, and the specific number is set according to requirements;
each U-shaped conductive connecting wire 304 in the first row comprises a conductive layer 504 and two micro-through holes 502, the two micro-through holes 502 are arranged on the upper surfaces of the left end and the right end of the conductive layer 504, the upper surface of the micro-through hole 502 on the left side is connected with the lower surface of the first outer chip 101 through a first upper interconnection conductive pad 416-1, a connection micro-through hole, a substrate conductive layer 403, a substrate micro-through hole 405 and a solder bump 107 which are sequentially connected, and the upper surface of the micro-through hole 502 on the right side is connected with the lower surface of the first outer chip 101 through a third upper interconnection conductive pad 416-3, a connection micro-through hole, a substrate conductive layer 403, a substrate micro-through hole 405 and a solder bump;
each U-shaped conductive connection wire 304 in the second row comprises two conductive layers 504 and three micro-through holes 502, the upper surface of the left end of the first conductive layer is connected with a first micro-through hole, the first micro-through hole is also connected to the lower surface of the right end of the conductive layer of the U-shaped conductive connection wire 304 in the first row, and the upper surface of the right end of the first conductive layer is connected with the lower surface of the second outer chip 103 through a second micro-through hole, a second conductive layer, a third micro-through hole, a fourth upper interconnection conductive pad 416-4, a connection micro-through hole, a substrate conductive layer 403, a substrate micro-through hole 405 and a solder bump 107 which are sequentially connected;
each U-shaped conductive connecting wire 304 in the third row comprises three conductive layers 504 and four micro-through holes 502, the upper surface of the left end of the first conductive layer is connected with a first micro-through hole, the first micro-through hole is also connected to the lower surface of the right end of the first conductive layer of the U-shaped conductive connecting wire 304 in the second row, and the upper surface of the right end of the first conductive layer in the third row is connected with the lower surface of the second outer chip 103 through a second micro-through hole, a second conductive layer, a third micro-through hole, a third conductive layer, a fourth micro-through hole, a second upper interconnecting conductive pad 416-2, a connecting micro-through hole, a substrate conductive layer 403, a substrate micro-through hole 405 and a solder bump 107 which are sequentially connected;
the lower surface of the left end of the first row of conductive layers is also sequentially connected with a first micro-via, a first conductive layer, a second micro-via, a second conductive layer, a third micro-via, a third conductive layer, a first lower interconnection conductive pad 418-1, a left substrate interconnection conductive layer 410, a substrate via 404, and a substrate via conductive layer 402;
the lower surface of the right end of the third row of conducting layers is also sequentially connected with a first micro through hole, a first conducting layer, a second lower interconnection conducting pad 418-2, a right substrate interconnection conducting layer 410, a substrate through hole 404 and a substrate through hole conducting layer 402; the substrate interconnect conductive layer 410 on the right side is also in contact with the lower surface of the embedded passive bridge chip 120 on the right side.
The right embedded passive bridge chip 120 includes a row of u-shaped conductive connecting lines 304, the lower surfaces of the left and right ends of the row of u-shaped conductive connecting lines 304 are provided with lower chip connecting lines, the row has at least one u-shaped conductive connecting line 304, and the specific number is set according to the requirement;
each U-shaped conductive connecting wire 304 in the row comprises a conductive layer 504 and two micro-through holes 502, the two micro-through holes 502 are arranged on the upper surfaces of the left end and the right end of the conductive layer 504, the upper surface of the left micro-through hole 502 is connected with the lower surface of the first outer chip 101 through a first upper interconnection conductive pad 416-1, a connection micro-through hole, a substrate conductive layer 403, a substrate micro-through hole 405 and a solder bump 107 which are sequentially connected, and the upper surface of the right micro-through hole 502 is connected with the lower surface of the first outer chip 101 through a third upper interconnection conductive pad 416-3, a connection micro-through hole, a substrate conductive layer 403, a substrate micro-through hole 405 and a solder bump 107 which are sequentially connected;
the lower surface of the left end of the row of conducting layers is also sequentially connected with a first micro-via, a first conducting layer, a second micro-via, a second conducting layer, a third micro-via, a third conducting layer, a first lower interconnection conducting pad 418-1, a left substrate interconnection conducting layer 410, a substrate via 404 and a substrate via conducting layer 402;
the lower surface of the right end of the row of conducting layers is also sequentially connected with a first micro through hole, a first conducting layer, a second lower interconnection conducting pad 418-2, a right substrate interconnection conducting layer 410, a substrate through hole 404 and a substrate through hole conducting layer 402; each left substrate interconnection conductive layer 410 and each right substrate interconnection conductive layer 410 connected to the row of conductive layers 504 in the right embedded passive bridge chip 120 are in one-to-one correspondence with each right substrate interconnection conductive layer 410 connected to the third row of conductive layers in the left embedded passive bridge chip 120, so that signal/energy transmission between the left embedded passive bridge chip 120 and the right embedded passive bridge chip 120 can be realized.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that various changes, modifications and substitutions can be made without departing from the spirit and scope of the invention as defined by the appended claims. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An embedded passive bridge chip, characterized in that, at least one U-shaped conductive connection line (304) is provided inside the embedded passive bridge chip (120), and the right and left ends of the U-shaped conductive connection line (304) are respectively connected to the same external chip or two external chips.
2. The embedded passive bridge chip of claim 1, wherein at least one row of u-shaped conductive connecting lines (304) is distributed from top to bottom, and left and right ends of the upper row of u-shaped conductive connecting lines (304) are respectively located in left and right ends of the next row of u-shaped conductive connecting lines (304); each row is distributed with at least one U-shaped conductive connecting wire (304), the left ends of any two adjacent U-shaped conductive connecting wires (304) of each row are arranged in a staggered manner, and the right ends of any two adjacent U-shaped conductive connecting wires (304) of each row are arranged in a staggered manner.
3. The embedded passive bridge chip of claim 1, wherein at least one row of "u" -shaped conductive connecting lines (304) is distributed from left to right, any two adjacent "u" -shaped conductive connecting lines (304) are connected, the upper surface of the left end of the right "u" -shaped conductive connecting line (304) is connected to the lower surface of the right end of the left "u" -shaped conductive connecting line (304), and the lower core connecting lines are disposed on the left end of the leftmost "u" -shaped conductive connecting line (304), the right end of the rightmost "u" -shaped conductive connecting line (304), and the lower surfaces of the connecting portions of any two adjacent "u" -shaped conductive connecting lines (304); each row is distributed with at least one U-shaped conductive connecting wire (304), the left ends of any two adjacent U-shaped conductive connecting wires (304) of each row are arranged in a staggered manner, and the right ends of any two adjacent U-shaped conductive connecting wires (304) of each row are arranged in a staggered manner.
4. The embedded passive bridge chip according to claim 1, wherein the embedded passive bridge chip (120) is provided with through-silicon vias (108) vertically penetrating the embedded passive bridge chip (120) to form at least one conductive connection line (302), and the top of each conductive connection line (302) is connected to the outer chip through a solder bump (107).
5. The embedded passive bridge chip of claim 2 or 3, wherein each U-shaped conductive connection line (304) comprises a second chip connection element, the second chip connection element comprises a second chip conductive layer (106) and two chip micro-vias (102), and the two chip micro-vias (102) are disposed on the upper surfaces of the left and right ends of the second chip conductive layer (106).
6. The embedded passive-bridging chip of claim 5, wherein each U-shaped conductive connection (304) comprises a second chip connection element and a first chip connection element, and at least one first chip connection element is sequentially connected to the upper surfaces of the left and right ends of the second chip connection element respectively; the first chip connecting piece comprises a first chip conducting layer (104) and a chip micro through hole (102), wherein the chip micro through hole (102) is arranged on the upper surface of the first chip conducting layer (104); the second chip connecting piece comprises a second chip conducting layer (106) and two chip micro through holes (102), wherein the two chip micro through holes (102) are formed in the upper surfaces of the left end and the right end of the second chip conducting layer (106).
7. The embedded passive bridge chip of claim 6, wherein a first chip connection is further connected to the bottom surface of the left and/or right ends of the bottom row of U-shaped conductive connection lines (304).
8. The embedded passive bridge chip of claim 6, wherein when the U-shaped conductive connection lines (304) are distributed in multiple rows from top to bottom, the second chip conductive layer of two adjacent rows of U-shaped conductive connection lines (304) is formed by crossing the power/ground layer and the signal layer.
9. A packaging structure with an embedded passive bridge chip on the surface of a packaging substrate is characterized by comprising a first outer chip (101), a second outer chip (103), an embedded passive bridge chip (120), the packaging substrate (100) and a PCB (140), wherein the embedded passive bridge chip (120) is embedded in the packaging substrate (100), at least one U-shaped conductive connecting line (304) is arranged inside the embedded passive bridge chip (120), at least one row of the U-shaped conductive connecting lines (304) is distributed from top to bottom, and the left end and the right end of the U-shaped conductive connecting line (304) in the previous row are respectively positioned in the left end and the right end of the U-shaped conductive connecting line (304) in the next row; each row is distributed with at least one U-shaped conductive connecting line (304), the left ends of any two adjacent U-shaped conductive connecting lines (304) of each row are arranged in a staggered manner, and the right ends of any two adjacent U-shaped conductive connecting lines (304) of each row are arranged in a staggered manner;
the left end and the right end of the U-shaped conductive connecting wire (304) are respectively connected with the lower surfaces of the first outer chip (101) and the second outer chip (103) through solder bumps (107); conductive connecting lines (302) are arranged inside the embedded passive bridge chip (120) and positioned on two sides of the U-shaped conductive connecting line (304), the tops of the conductive connecting lines (302) on the two sides are respectively connected with the lower surfaces of the first outer chip (101) and the second outer chip (103) through soldering tin bumps (107), and the bottoms of the conductive connecting lines (302) on the two sides are connected with the PCB (140) through the first substrate connecting line (306) and the lower soldering tin ball (309) in sequence; and a cavity (412) is arranged on any side of the embedded passive bridge chip (120).
10. A packaging structure with embedded passive bridge chips on the surface of a packaging substrate is characterized by comprising at least two outer chips, at least one embedded passive bridge chip (120), the packaging substrate (100) and a PCB (140), wherein the outer chips are sequentially distributed at intervals from left to right, the embedded passive bridge chips (120) are sequentially embedded in the packaging substrate (100) at intervals from left to right, at least one U-shaped conductive connecting line (304) is arranged inside the embedded passive bridge chip (120), and the left end and the right end of the U-shaped conductive connecting line (304) are respectively connected with the lower surfaces of the outer chips through soldering tin bumps (107); the lower surfaces of the left end and/or the right end of the U-shaped conductive connecting line (304) are respectively connected with the PCB (140) through a first substrate connecting line (306) and a lower solder ball (309) in sequence; and a cavity (412) is arranged on any side of the embedded passive bridge chip (120).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911318403.XA CN110911384A (en) | 2019-12-19 | 2019-12-19 | Embedded passive bridge chip and application thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911318403.XA CN110911384A (en) | 2019-12-19 | 2019-12-19 | Embedded passive bridge chip and application thereof |
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| CN110911384A true CN110911384A (en) | 2020-03-24 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113327911A (en) * | 2021-04-23 | 2021-08-31 | 浙江毫微米科技有限公司 | Redistribution layer structure and preparation method thereof, packaging structure and preparation method thereof |
| CN113764394A (en) * | 2021-09-08 | 2021-12-07 | 中科芯集成电路有限公司 | SIP packaging structure based on embedded integrated pull-up and pull-down resistor IPD |
-
2019
- 2019-12-19 CN CN201911318403.XA patent/CN110911384A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113327911A (en) * | 2021-04-23 | 2021-08-31 | 浙江毫微米科技有限公司 | Redistribution layer structure and preparation method thereof, packaging structure and preparation method thereof |
| CN113327911B (en) * | 2021-04-23 | 2022-11-25 | 浙江毫微米科技有限公司 | Redistribution layer structure and preparation method thereof, packaging structure and preparation method thereof |
| CN113764394A (en) * | 2021-09-08 | 2021-12-07 | 中科芯集成电路有限公司 | SIP packaging structure based on embedded integrated pull-up and pull-down resistor IPD |
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