CN102232259B - 用于改进串扰衰减的插座 - Google Patents

用于改进串扰衰减的插座 Download PDF

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CN102232259B
CN102232259B CN200980149115.4A CN200980149115A CN102232259B CN 102232259 B CN102232259 B CN 102232259B CN 200980149115 A CN200980149115 A CN 200980149115A CN 102232259 B CN102232259 B CN 102232259B
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insulation displacement
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CN102232259A (zh
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F·M·斯特拉卡
R·L·泰拉斯
J·J·吉尔曼
V·J·瓦伊特库斯
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Panduit Corp
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    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H01R13/6464—Means for preventing cross-talk by adding capacitive elements
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    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/46—Bases; Cases
    • H01R13/516—Means for holding or embracing insulating body, e.g. casing, hoods
    • H01R13/518—Means for holding or embracing insulating body, e.g. casing, hoods for holding or embracing several coupling parts, e.g. frames
    • H—ELECTRICITY
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    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6473—Impedance matching
    • H—ELECTRICITY
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    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6473—Impedance matching
    • H01R13/6474—Impedance matching by variation of conductive properties, e.g. by dimension variations
    • H01R13/6476—Impedance matching by variation of conductive properties, e.g. by dimension variations by making an aperture, e.g. a hole
    • H—ELECTRICITY
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    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/648—Protective earth or shield arrangements on coupling devices, e.g. anti-static shielding  
    • H01R13/658—High frequency shielding arrangements, e.g. against EMI [Electro-Magnetic Interference] or EMP [Electro-Magnetic Pulse]
    • H—ELECTRICITY
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    • H01R24/00—Two-part coupling devices, or either of their cooperating parts, characterised by their overall structure
    • H01R24/58—Contacts spaced along longitudinal axis of engagement
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    • H01R24/00—Two-part coupling devices, or either of their cooperating parts, characterised by their overall structure
    • H01R24/60—Contacts spaced along planar side wall transverse to longitudinal axis of engagement
    • H01R24/62—Sliding engagements with one side only, e.g. modular jack coupling devices
    • H01R24/64—Sliding engagements with one side only, e.g. modular jack coupling devices for high frequency, e.g. RJ 45
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    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0228—Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors
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    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector
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Abstract

本申请描述了一种用于改进串扰衰减的插座。该插座具有罩壳、箔层、印刷电路板以及至少一对绝缘层剥离触点和通孔，该箔层至少部分地封围罩壳。每对绝缘触点和通孔与差分信号相关联。导电迹线柱在印刷电路板上引导成在箔层附近靠近板的边缘，从而通过将迹线柱电连接至更远离箔片的通孔而至少部分地平衡从一对绝缘层剥离触点和通孔之一到箔层的耦合与从该对绝缘层剥离触点和通孔之另一到箔层的耦合。

Description

用于改进串扰衰减的插座
背景技术
存在一种在用于近端串扰和远端串扰(NEXT和FEXT)、以及外来近端串扰和外来远端串扰(ANEXT和AFEXT)的信道中获得更大的余量的持续需求。NEXT和FEXT的主源发生在插头/插座组合的插头内，并通常在插座内被补偿。外来串扰的主源是耦合在信道之间、尤其是相邻插座之间的共模噪声，并转换成差分外来串扰(模式转换)。 
附图说明
图1是本发明的具有箔层屏蔽件的插座的一实施例的立体图； 
图2是本发明的具有箔层屏蔽件的插座的另一实施例的立体图； 
图3是沿图1中剖面线3-3所取的剖面图，示出了本发明的用于粘合箔层材料的堆叠结构； 
图4是示出由于沿着相邻插座之间的插座箔层屏蔽件的共模传播而发生的外来串扰的示意图，该外来串扰转换回插座中的差分串扰； 
图5是本发明的通信系统一实施例的局部立体图； 
图6是本发明的模块化插座一实施例的分解立体图； 
图7示出了图6插座的一些方面的立体图； 
图8是图6插座的插头接口触点的立体图； 
图9是图6的插座的多层柔性电路板的透视立体图； 
图10是图9的柔性电路板的示意图； 
图11是图6的插座的多层刚性电路板的透视立体图； 
图12是图11的刚性电路板的示意图； 
图13是示出了根据本发明如何通过使用裂开箔层阻止沿着插座箔层屏蔽件的共模传播来减少外来串扰的示意图； 
图14是本发明的具有箔层屏蔽件的插座的另一实施例的立体分解图，其中箔层屏蔽件是连续的，但金属层具有间隙； 
图15是本发明的具有箔层屏蔽件的插座的另一实施例的立体分解图，其中箔层屏蔽件是连续的，但金属层仅仅存在于底部和一侧上； 
图16是本发明的具有箔层屏蔽件的插座的另一实施例的立体分解图，其中箔层屏蔽件是连续的，但箔层的可选区域具有金属层；以及 
图17是本发明的具有箔层屏蔽件的插座的另一实施例的立体分解图，其中箔层屏蔽件由于连续金属化而是连续的，但箔层仅仅包括单侧和顶部。 
对应的附图标记在若干附图中标示对应的部件。这里阐述的实例说明书了本发明的一些较佳实施例，但是这些实例并不构造成以任何方式限制本发明的范围。 
具体实施方式
在2008年8月20日提交的、名称为“High-Speed Connector with Multi-Stage Compensation”的美国临时专利申请61/090,403中，以一种在500MHz处、超过TIA 6A类标准的改进6A类(CAT6A)RJ45插座设计描述了补偿方法和设备，以参见的方式引入该临时专利申请，就好像这里已经完全阐述了一样。该插座针对行业需求以对近端串扰(NEXT)、远端串扰(FEXT)和返回损耗获得更大余量，从而满足苛刻消费者的需求。此外，该插座减少了插座内发生的差模-共模转换和共模-差模转换(这里称为“模式转换”)，从而改进了系统的外来串扰性能。 
美国专利申请公布2006/0134995披露了通信插座，这些通信插座设有导电覆盖层，从而在插座彼此并排安装时，减少绝缘层剥离触点(IDC)处连接器之间的ANEXT量，也以参见的方式引入该专利申请公布，就好像这里已经完全阐述了一样。这些导电层或箔层也是以上引用的美国临时专利申请61/090,403的部分。 
在其它进展中，与高频处的插座返回损耗余量相对应，本发明针对信道中的一些电流限制和持久链接性能。在本发明的一个实施例中，插座传输线部件可包括插头接口触点(PIC)、柔性电路板、刚性电路板电路元件和IDC，PIC 与插头匹配、绕分线器卷绕并与刚性电路板接口，柔性电路板绕该分线器卷绕且其部件与PIC接触，IDC也与刚性电路板接口并允许电缆中的线与IDC连接。插头/PIC、柔性板、刚性板的PIC区和刚性板的补偿区可被认为是第一阻抗区；刚性板的IDC通孔区和IDC可被认为是第一阻抗区之后的第二阻抗区。假如插座连接器具有相对低阻抗区(第一阻抗区)之后的相对高阻抗区(第二阻抗区)，则在低频处有较大的返回损耗余量，而在高频处有较小的返回损耗余量。仅有第一低阻抗区而没有第二相对高阻抗区的插座在低频处有较小的余量，而在高频处有较大的相对余量(与具有低阻抗区之后的相对高阻抗区的插座相比)。当幅值与上述相反时，诸如插座具有高阻抗区之后的低阻抗区，这个关系同样适用，其中低阻抗区的阻抗增大改进了返回损耗。 
在目前的插座设计中，线对4-5通常是在高频处具有最差返回损耗余量的线对。一般来说，线对4-5具有由插头/PIC、柔性板、刚性板的PIC区和刚性板的补偿区引起的低阻抗区，后跟由相应IDC和线盖引起的高阻抗区。本发明的一特征是，减小高阻抗区的阻抗，从而返回损耗在低频处变得相对较差，而在高频处改进余量，这导致相对于CAT6A规格总体改进的返回损耗余量。由于阻抗和电容之间的关系通常遵循Z＝√(L/C)，在高阻抗区增大电容，以减小高阻抗区的阻抗。 
在许多插座聚集在一区域内的接线板或插座板中，在这些相邻的插座之间会发生高程度的外来串扰。这个原理的先前理解指出：这个耦合主要是由于相邻插头和插座中的相邻导线和翼片、尤其是彼此相邻延伸的平行部分发生接近而引起的感应差分耦合。图1和2的箔层标签设计针对这个问题。在图1中，插座组件20包括插座22和粘附安装的箔层标签或屏蔽件24。例如，插座22可以是CAT6A插座设计。或者，也可使用其它插座，诸如CAT6、CAT7或其它。图2示出了插座组件26，该插座组件包括插座22和具有延伸侧29的粘附安装箔层标签28。这些箔层标签24、28主要用来减少发生在相邻插座之间的外来串扰量，这是因为由于不相邻插座相对远离，所以不相邻插座的耦合程度已经非常低。尽管在图1-2中未示出，但是插座20、26通常可包括图6所示的线盖和图6的其它元件。箔层标签包括粘合材料、金属衬层、随后的漆层和保护涂层，如图3所示。 
然而，已经观察到，在具有高程度共模噪声的通道环境中，箔层屏蔽件为共模电流流至和流过相邻插座提供电连接(包括围绕插座的导电路径，各相邻插座有电容耦合)，如图4所示。这是不相邻插座之间的外来串扰的主要原因，还进一步增大了相邻插座之间的外来串扰量。当若干插座(每个插座包括如图1和2所示包括箔层屏蔽件)彼此相邻时，由于相邻箔层之间的大量电容耦合，在插座之间存在用于共模电流行进的非常低损耗的路径，本发明的至少一个实施例针对这个问题。 
在本发明的另一方面，希望在插头/插座组合内的所有不同线对组合之间具有平衡的电容负载和电感负载，从而使模式转换最小化。还希望每个不同线对相对于插座周围部件的箔层标签设计得到平衡，从而进一步减小模式转换。 
这里描述了一种带有箔层标签和改进刚性电路板的插座的新颖设计，其除了针对上述问题作出改进之外，还改进了插座上的每个不同线对相对于箔层标签的平衡。本发明减少了插座的模式转换，并改进了外来串扰。 
现在参见附图，更具体地参见图5，示出了通信系统30，该通信系统可包括连接至设备34的通信电缆，诸如接线电缆32和水平电缆33。设备34在图5中显示成接线板，但设备也可以是无源设备或有源设备。无源设备的实例可以是，但不局限于，模块化接线板、打线接线板、耦合接线板、墙插座等。有源设备的实例可以是，但不局限于，如能够在数据中心/无线通信室内发现的以太网切换机、路由器、服务器、物理层管理系统和以太网供电设备；安全装置(摄像头和其它传感器等)以及门禁设备；以及如能够在工作站区域内发现的电话、计算机、传真机、打印机和其它外围设备。通信系统30还可包括机箱、机架、电缆管理和顶置路由系统以及其它这种设备。 
通信电缆32和33显示成未屏蔽扭绞线对(UTP)电缆的形式，更具体地是可以10Gb/s运行的CAT6A电缆。然而，本发明可应用于和/或实施于各种通信电缆的连接。电缆33能够直接端接到设备34中，或者能够端接到诸如RJ45型的各种插头或插座模块40中、插座模块盒和许多其它接插件类型或其组合中。接线电缆32通常端接于插头36。 
图6示出了插座40的更详细分解图，其大体包括罩壳42、鼻部44，该罩壳42匹配RJ45插头，该鼻部44具有八个PIC56，PIC56与插头匹配、绕分线 器60卷绕并与刚性板46接口。刚性板46连接至IDC48和保持IDC的后分线器50。线盖52允许电缆内的导线与IDC连接，这也是图1-2的插头的一部分，但未在图中示出。鼻部44包括柔性电路板54、插头接口触点56、前底分线器58和前顶分线器60。图1和2与图6的不同之处在于：图1和2分别示出两个箔层标签设计24、28，而图6示出改进的箔层标签70(也参见图7)，该箔层标签70具有第一侧72和镜像的第二侧74，其间具有间隙76。这里所述的刚性板46的设计可与所有三种这些箔层24、28和70一起工作。与箔层28一样，箔层标签70包括延伸部78，该延伸部78有助于减少插头与相邻插座中的PIC之间的耦合。 
如图8和图9-10分别所示，串扰补偿部件可被包括在PIC 56和柔性板54上。具体参见图11和12，刚性板46也包括串扰补偿部件(与插头串扰部件的极性相同或相反)，这些串扰补偿部件具体在图12中标出，但C45是例外。C45通过如前所述减小第二阻抗区的较高阻抗来改进线对4-5中在高频处的返回损耗余量。尽管返回损耗由于该修改而在低频处变得较差，但总体的余量在所关注的频带上得到了改进。刚性板46包括点阵型补偿，也在美国临时专利申请61/090,403中有描述。 
本发明的一个新颖方面是：它针对存在于插座上的所有线对和箔层标签之间的天然不平衡耦合。这种不平衡的主要原因示于图6中。靠近插座边缘的IDC48(插脚5、2、6、7)比不靠近插座边缘的IDC 48(插脚4、1、3、8)更强地电容耦合至箔层。这对于线对4-5和线对1-2尤其如此，其中，IDC 5和2靠近箔层，而IDC 1和4远离箔层。 
图11中示出了用于相对于箔层屏蔽件来平衡线对的刚性板解决方案的一实施例。在该实施例中，刚性板46具有四个导电迹线层。IDC通孔接纳并保持IDC。IDC通孔在图11中板的顶边处标为5′-4′-1′-2′，在板的底边处标为7′-8′-3′-6′，还是在各层上将一些迹线互连起来的镀金属穿孔。信号或噪声可尤其通过IDC通孔和IDC 5′、2′、6′以及7′较强地耦合至箔层标签70。例如对于线对4-5来说，IDC通孔5′和IDC 5′比IDC通孔4′和IDC 4′更靠近箔层标签70。为了平衡这个线对，导电迹线柱90在箔层70附近被引导至板46的边缘附近，并通过其至PIC通孔4的连接而电连接至迹线4(将PIC通孔4和IDC通孔  4′互连起来的导电迹线)。柱90由此相对于导体5和箔层平衡导体4。附加地和/或替代地，迹线4可引导至相对靠近刚性板46的边缘，以增大至箔层70的耦合。在所示的实施例中，柱90以0.5盎司铜制成0.008英寸宽乘以0.220英寸长(约0.0007英寸厚)，但也可采用其它厚度、宽度和长度。 
类似地，例如对于线对1-2来说，IDC通孔2′和IDC 2′比IDC通孔1′和IDC1′更靠近箔层70。为了平衡这个线对，导电迹线柱92在箔层70附近被引导至板46的边缘附近，并经由镀金属穿孔94连接至迹线1(将PIC通孔1和IDC通孔1′互连起来的导电迹线)。柱92类似于柱90；然而，因为刚性板46上的空间限制，柱92仅仅是0.005英寸宽乘以0.075英寸长，也由1盎司铜制成(约0.0014英寸厚加上附加镀层以实现0.002-0.0035的厚度)，但也可采用其它厚度、宽度和长度。为了补偿该相对短的长度，12线对还通过将迹线1移动到非常靠近板边缘(靠近箔层70)来平衡，镀金属穿孔94提供第三维度(板厚度)中的显著表面积，其也电容耦合至箔层70，在导体1和箔层70之间给出较强耦合，由此相对于箔层70平衡12线对。大致在96处的各未镀金属穿孔减少更靠近NEXT补偿区域的迹线4和5之间的电容，从而通过较好的阻抗匹配减少补偿元件对返回损耗的影响。 
图13中示出了使用裂开箔层、相对于箔层的线对平衡结果。本发明由于相对于箔层的线对平衡而在箔层上实现了较小的共模电流I’，裂开箔层消除了用于将共模电流从相邻插座传播至相邻插座的低损耗路径。由于本发明的改进，已经显示外来串扰余量的总体改进为至少4dB。此外，本发明可有利地用于图1、2、6和14的每个对称箔层设计，但是图1和2的设计将不具有裂开屏蔽件的特征和优点。图14包括具有金属化间隙的连续单件箔层。 
在本发明的其它方面，穿孔100(在图11中示出)是指具有与C45相反的效应，但是不必要的话可去除穿孔98。相对于美国临时专利申请61/090,403，电容C24的增加和C15的消除改进了线对组合45-12上的NEXT。下面是与美国临时专利申请61/090,403的一些其它比较。与新电感L3L一起使用导电迹线L3将迹线3连接至C38，使用点阵补偿并改进36-78NEXT。改变L6的定向以使其远离刚性板的侧部减少了至箔层的耦合。移动C58和C16的位置适应了本发明的新布线图。 
图15-17的对称箔层设计通常需要对于图11所示平衡电路的修改，诸如刚性板46的侧部上的较小平衡部件，其几乎没有或没有导电屏蔽件。也就是说，较小平衡部件设置在刚性板的特定部分上，不相邻于任何导电箔层或屏蔽件。原理上，每个不同线对需要实现相对于箔层每个部分的平衡，从而多个箔层部分需要每个箔层部分相对于插座平衡。图15示出了箔层标签的一实施例，其中一侧没有任何金属(注意，这里所示的实施例可翻转从而相反侧是金属化的)；图16示出了具有可选金属化区域的箔层标签的一实施例；以及图17示出了箔层标签的一实施例，该箔层标签是L形的金属化箔层，其中插座的一侧和顶部或底部被箔层覆盖，留出一侧没有任何覆盖。注意，图17所示的实施例可通过使相反侧具有箔层且去除图17所示一侧来作出修改。 
本发明的替代实施例包括带有图11电路板的插座，但电容C15位于IDC通孔1和5之间，或者包括带有图11电路板的插座，但电容C24与连接至其的任何迹线从板上完全去除。本发明的另外替代实施例消除了柔性板。 
尽管本发明已经描述成具有较佳设计，但本发明还可在本说明书的精神和范围内作出修改。本申请因此旨在使用其总体原理覆盖本发明的任何变型、用途或改适。 

Claims (14)

1.一种用于改进串扰衰减的插座，包括：
罩壳；
箔层，所述箔层至少部分地封围所述罩壳；
印刷电路板；
第一绝缘层剥离触点和第二绝缘层剥离触点，所述第一绝缘层剥离触点比所述第二绝缘层剥离触点靠近所述箔层，所述第一绝缘层剥离触点和所述第二绝缘层剥离触点与第一差分信号相关联；以及
第一导电迹线柱，所述第一导电迹线柱电连接至引导成靠近所述印刷电路板的边缘并靠近所述箔层的所述第二绝缘层剥离触点，所述第一导电迹线柱构造成对于所述第一差分信号至少部分地平衡从所述第一绝缘层剥离触点到所述箔层的耦合与从所述第二绝缘层剥离触点到所述箔层的耦合。
2.如权利要求1所述的用于改进串扰衰减的插座，其特征在于，还包括与所述第一绝缘层剥离触点相关联的第一通孔和与所述第二绝缘层剥离触点相关联的第二通孔，所述第一导电迹线柱还构造成对于所述第一差分信号至少部分地平衡从所述第一通孔到所述箔层的耦合与从所述第二通孔到所述箔层的耦合。
3.如权利要求2所述的用于改进串扰衰减的插座，其特征在于，还包括分线器。
4.如权利要求3所述的用于改进串扰衰减的插座，其特征在于，还包括线盖。
5.如权利要求4所述的用于改进串扰衰减的插座，其特征在于，还包括插头接口触点。
6.如权利要求1所述的用于改进串扰衰减的插座，其特征在于，还包括所述印刷电路板上与所述第一差分信号相关联的信号迹线，所述信号迹线的一部分靠近所述印刷电路板的边缘并靠近所述箔层，从而有助于对于所述第一差分信号平衡从所述第一绝缘层剥离触点到所述箔层的耦合与从所述第二绝缘层剥离触点到所述箔层的耦合。
7.如权利要求2所述的用于改进串扰衰减的插座，其特征在于，还包括所述印刷电路板上与所述第一差分信号相关联的信号迹线，所述信号迹线的一部分靠近所述印刷电路板的边缘并靠近所述箔层，从而有助于对于所述第一差分信号平衡从所述第一绝缘层剥离触点和所述第一通孔到所述箔层的耦合与从所述第二绝缘层剥离触点和所述第二通孔到所述箔层的耦合。
8.如权利要求1所述的用于改进串扰衰减的插座，其特征在于，还包括：
第三绝缘层剥离触点和第四绝缘层剥离触点，所述第三绝缘层剥离触点和所述第四绝缘层剥离触点与第二差分信号相关联，所述第三绝缘层剥离触点比所述第四绝缘层剥离触点靠近所述箔层；以及
第二导电迹线柱，所述第二导电迹线柱引导成靠近所述印刷电路板的边缘并靠近所述箔层，并还构造成对于所述第二差分信号至少部分地平衡从所述第三绝缘层剥离触点到所述箔层的耦合与从所述第四绝缘层剥离触点到所述箔层的耦合。
9.如权利要求8所述的用于改进串扰衰减的插座，其特征在于，还包括与所述第三绝缘层剥离触点相关联的第三通孔和与所述第四绝缘层剥离触点相关联的第四通孔，所述第二导电迹线柱还构造成对于所述第二差分信号至少部分地平衡从所述第三通孔到所述箔层的耦合与从所述第四通孔到所述箔层的耦合。
10.如权利要求8所述的用于改进串扰衰减的插座，其特征在于，还包括分线器。
11.如权利要求10所述的用于改进串扰衰减的插座，其特征在于，还包括线盖。
12.如权利要求11所述的用于改进串扰衰减的插座，其特征在于，还包括插头接口触点。
13.如权利要求8所述的用于改进串扰衰减的插座，其特征在于，还包括所述印刷电路板上与所述第二差分信号相关联的信号迹线，所述信号迹线的一部分靠近所述印刷电路板的边缘并靠近所述箔层，从而有助于平衡从所述第三绝缘层剥离触点到所述箔层的耦合与从所述第四绝缘层剥离触点到所述箔层的耦合。
14.如权利要求9所述的用于改进串扰衰减的插座，其特征在于，还包括所述印刷电路板上与所述第二差分信号线对相关联的信号迹线，所述信号迹线的一部分靠近所述印刷电路板的边缘并靠近所述箔层，从而有助于平衡从所述第三绝缘层剥离触点和所述第三通孔到所述箔层的耦合与从所述第四绝缘层剥离触点和所述第四通孔到所述箔层的耦合。
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