CN102224593A - 功率mos晶体管器件及包括其的开关装置 - Google Patents
功率mos晶体管器件及包括其的开关装置 Download PDFInfo
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- CN102224593A CN102224593A CN200880132060.1A CN200880132060A CN102224593A CN 102224593 A CN102224593 A CN 102224593A CN 200880132060 A CN200880132060 A CN 200880132060A CN 102224593 A CN102224593 A CN 102224593A
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Abstract
一种晶体管功率开关器件(700),包括用于承载半导体主体的第一面(104)和第二面(106)之间的电流的垂直晶体管元件(108)的阵列,晶体管元件(108)的阵列包括第一面(104)处的第一半导体类型的源极区(114)的阵列、插入在源极区(114)和第二面(106)之间的与第一类型相反的第二半导体类型的至少一个p区(122、124、126)、以及至少一个控制电极(116),用于以可开关方式控制电流流过p区(122、124、126),以及传导层(110),接触源极区(114)并且通过至少一个绝缘层(120)与控制电极(116)绝缘。该开关器件还包括与晶体管(108)阵列电气并联的至少一个反向偏置垂直雪崩二极管(702),用于在器件的截止状态中传导第一面(104)和第二面(106)之间的击穿电流,并且具有与第一面(104)和传导层(110)接触的第二半导体类型的第一电流承载二极管区(704)和与第二面(106)电气连接的第一半导体类型的第二半导体区(706)。该开关器件还包括在每个雪崩二极管上接合到传导层(110)的电气连接引脚(128)。
Description
技术领域
本发明涉及晶体管功率开关器件。
背景技术
美国专利申请公开US 2006-0145252描述了一种包括垂直绝缘栅极MOSFET阵列的晶体管功率开关器件。其晶体管功率开关器件的操作特性在导通电阻和关态(stand-off)电压方面基本上是非常令人满意的。然而,如同其他晶体管功率开关器件,在某些环境中其遭受雪崩击穿。
雪崩击穿是在绝缘和半导体材料中都可以发生的现象。它是一种形式的电流倍增,其可允许非常大的电流在那些在其他情况下是良好绝缘体的材料内流动,当材料中的电场大地足以将自由电子加速到在它们撞击材料中的原子时能够碰撞其他电子使其成为自由电子的点:因此自由电子的数目随着新生成的粒子成为该过程的一部分而迅速增加。由于关联电场可以感生电流倍增并且引起过度(如果没有限制)的电流流动以及器件的破坏,因此该现象可以提出操作电压的上限。
晶体管功率开关的雪崩击穿易于由非箝位电感开关(UIS)引起。诸如金属-氧化物-硅场效应晶体管(MOSFET)的功率晶体管固有地具有极快的开关速度。快的开关速度可以导致不常在较慢的开关电路中遇到的器件应力。实际上,开关速度可以很快,使得在器件关断时,电路中的小寄生电感可以引起明显的过压瞬态。如果得到的电压瞬态足够大,则可以迫使开关晶体管进入雪崩,诸如MOSFET的情况下的漏极-源极雪崩。可以要求晶体管无故障地承受许大量重复的雪崩击穿发生。
美国专利申请公开20070176231描述了一种MOSFET晶体管功率开关器件,其中,一些晶体管单元具有不同的台面(槽栅极之间的区)尺寸。在较大的晶体管单元中利用重体蚀刻来减少闩住基极电阻(pinched-base resistance)。该蚀刻移除台面区中的硅,其随后被替换为较低阻抗的铝。没有接收该蚀刻的许多较小的晶体管单元用于增加器件电流容量。通过确保较大的较低闩住基极单元具有较低的BVDSS击穿电压来将雪崩电流引导至这些单元,给出了对较小单元的雪崩保护的措施。
发明内容
本发明提供了如所附权利要求中描述的晶体管功率开关器件和功率开关装置。
通过参考下面描述的实施例,本发明的这些和其他方面将是明显的并且得到阐明。
附图说明
将参考附图仅通过示例的方式描述本发明的另外的细节、方面和实施例。附图中的元件是为了简单和清楚而图示,并且不一定依比例绘制。
图1示出了美国专利申请第10/518158的公知晶体管功率开关器件的一部分的俯视图,
图2示出了沿图1的线A-A′取的图1的器件的截面,
图3示出了沿图1的线B-B′取的图1的器件的截面,
图4示出了不具有本发明的雪崩二极管保护的晶体管功率开关器件的示例的一部分的俯视图,
图5示出了沿图4的线A-A′取的图4的示例的截面,
图6示出了沿图4的线B-B′取的图4的示例的截面,
图7示出了通过示例的方式给出的具有雪崩二极管保护的根据本发明的实施例的晶体管功率开关器件的示例的一部分的俯视图,
图8示出了沿图7的线A-A′取的图7的示例的截面,
图9示出了沿图7的线B-B′取的图7的示例的截面,
图10示出了图7的器件的示意性等效电路图,
图11示出了图7的器件的示例的较大部分的俯视图,
图12示出了与图11类似的图7的示例的一部分的俯视图,其示出了本发明的实施例的一个示例中的引脚线的配置,
图13示出了与图12相似的图7的示例的部分的俯视图,示出了本发明的实施例的一个示例中的引脚线的配置,
图14示出了曲线图,该曲线图示出了与图4中示出的类型的器件相比,图7中示出的类型的器件对重复的非箝位电感性开关电流脉冲的鲁棒性,以及
图15示出了将图7的器件应用于功率开关装置中的示例的示意图。
具体实施方式
现将描述本发明的细节,其包括本发明的示例性方面和实施例。参考附图和下面的描述,相同的附图标记用于标示相同或功能类似的元件,并且旨在以高度简化的示图方式图示示例性实施例的主要特征。而且,附图并非旨在描绘实际实施例的每个特征,也不旨在描绘所描绘的元件的相对尺寸,并且并不依比例绘制。
图1至图3示出了美国专利申请公开US 2006-0145252中描述的类型的晶体管功率开关器件100,其包括基本单元的阵列,每个基本单元包括垂直绝缘栅极金属氧化物硅场效应晶体管(MOSFET)108。该类型的器件被制造有高单元密度,有源半导体衬底的每平方厘米上具有数十万个甚或数百万个单元,以便于减小导通状态电阻,同时避免击穿和非箝位电感性开关(UIS)电压的相当的劣化。应当认识到,附图仅示出了单元总数的非常小的一部分,并且不必依比例绘制。
晶体管功率开关器件100是n型器件,但是p型器件也是可以的。晶体管功率开关器件100包括由第一半导体类型(在该示例中是n型)的衬底101形成的半导体主体,其呈现相对的第一面104和第二面106。晶体管功率开关器件100进一步包括垂直晶体管元件108的阵列,其在操作中承载所述第一面104和第二面106之间的电流。漏电极112接触由晶体管元件108共享的衬底101所形成的n型漏极区102的第二面106,并且淀积在第一面104上的源电极110接触垂直晶体管元件108的分离的n型源极掺杂区114。阵列的晶体管元件108包括:在第一面104处的第一半导体类型的第一电流承载晶体管区114(在该示例中是n型源极掺杂区)的阵列;以及,插入第一半导体源极区和第二面106之间的与第一类型相反的第二半导体类型的至少一个第二电流承载晶体管区(在该示例中是p型区)122、124、126。衬底101中的第二区包括:轻掺杂p型高电压(PHV)主体或阱、区122和PHV区122内的较重掺杂的p型掺杂(PSD)区124,以及插入在PSD域区124和源极区114之间的硼保护注入(BPI)区126。尽管MOSFET基本单元108可以包括彼此分离的第二主体区,但是在该示例中,主体区在第一源极区114之间和之下被合并在一起,以形成单个主体区122。垂直MOSFET基本单元108的阵列还包括栅电极116,用于以可开关方式控制主体区122中的所述电流的流动。再一次,尽管可以提供连接的栅电极的阵列,但是在该示例中,栅电极是单个栅电极层的元件。电极不一定是金属的,而是可以由其他传导材料制成,诸如,多晶硅。衬底的漏极区102、p区122、124、126和源极区114在衬底的面104处出现。栅电极116通过绝缘层118与面104绝缘,并且栅电极116通过绝缘层120与源电极110绝缘并且绝缘间隔物121使栅电极的边缘绝缘。在下文中,由层118、116、120组成的块被称为“栅极层叠”。衬底101中的第二区包括:轻掺杂p型高电压(PHV)主体或阱;区122和PHV区122内的较重掺杂p型掺杂(PSD)区124;以及插入在PSD区124和源极区114之间的硼保护注入(BPI)区126。
各种适当的制造方法可用于产生晶体管功率开关器件100。美国专利申请10申请公开US 2006-0145252 518158描述了一种制造包括垂直绝缘栅极MOSFET的阵列的晶体管功率开关器件的方法,该方法可以适用于制造根据本发明的器件。
美国专利申请公开US 2006-0145252的晶体管功率开关器件100可以提供鲁棒性UIS免疫性,特别是因为主体区被合并以提供单个PHV主体区122。然而,当增加通过场效应晶体管的十字形分支的雪崩电流时,可以激活寄生双极型npn晶体管。
图4至图6图示了与器件100类似的晶体管功率开关器件400的示例,但是其中,在基本单元的臂的末端处以及在它们的中心404处,由在基本单元内的面104处出现的PSD区124提供了额外的PSD接触402,在该情况下向源电极110提供了四个额外的PSD接触402。为了适应额外的PSD接触,在分支的末端处修改栅极层叠和源极区的形状,如图4中所示。这些额外的PSD接触在不激活寄生双极型npn晶体管的情况下增加了FET可以承受的雪崩电流容量。
在晶体管功率开关器件400中,接触传导层110的垂直晶体管元件108中的每一个的源极区114包括多个臂,该多个臂在第一面104处朝着阵列的相邻垂直晶体管元件108的源极区114的臂径向延伸。PHV主体区122在源极区114的臂周围和下面延伸。PHV主体区122通过PSD区124和BPI区126连接到传导层110,BPI区在源极区的每一个内向上延伸通过BPI区上方的层,以在与垂直晶体管元件108的源极区114的每个臂的末端相邻的PSD 124接触位置402处在第一面104处接触传导层110。PHV主体区122还通过PSD区124和BPI区126连接到传导层110,在源极区的每一个内向上延伸以在垂直晶体管元件108的每个源极区114的中心的接触位置404处在第一面104处接触传导层110。源极区114的每个臂的末端在接触位置402周围的第一面104处被扩大。
更详细地,如图4中所示,基本MOSFET单元108的栅极层叠和源极区114被形成为十字形状,其具有伸长的臂和臂的扩大的圆形末端。臂的每一个在远离末端的位置处都具有最小宽度,并且在扩大的圆形末端处,臂具有比最小宽度更大的宽度的位置。更具体地,在示出的示例中,臂在扩大的圆形末端处得位置处具有最大宽度。通过在面104上形成栅极层叠并且在层的材料中蚀刻十字形状来初始地限定这些形状。
衬底101中的第二主体或阱、区包括轻掺杂p型高电压(PHV)主体区122和PHV主体区122内的较重掺杂p型掺杂(PSD)区124的阵列。例如,通过在形成栅极层116、118和120之后使掺杂剂从面104扩散到衬底中,使用栅极层叠作为掩膜来使基本单元的分离的PHV区与栅极层叠中的开口自动对准并且然后使掺杂剂在衬底中垂直和横向地伸展受控的距离,使得基本单元的分离的PHV区在单元之间合并在一起以形成连续的PHV主体区122,来形成PHV区。在n型源极区114的扩散之前,p型掺杂剂在与未来的源极区114对准的位置处被覆盖注入(blanket implanted)在栅极层叠中的开口中,以形成硼保护注入主体区(BPI)126,其将呈现源极区114的面下面的层,BPI区在每个基本单元的源极区114的末端和中心内在面104处出现,以防止臂的末端处的穿通效应。
源极区114是在形成合并的PHV区之后形成的。可以通过光掩蔽面104处的基本单元的每个十字形栅极层开口的中心中的圆形PSD接触区404和扩大末端中的圆形PSD接触区域402,并且在除了圆形PSD接触区域402和404之外的栅极层叠中的开口中从面104将n型掺杂剂注入并且扩散到衬底中,来形成源极区114。然后通过注入形成PSD主体接触区124。所注入的n型和p型掺杂剂通过退火被同时激活。
在图4至图6的示例中,除用于接触栅电极116的区域外,源电极110连续覆盖MOSFET基本单元108的阵列,并且通过栅极层叠116至120中的开口实现与源极区114的电气接触并且还通过接触402和404处的BPI区126以及通过PSD区124实现与PHV区124的电气接触,以确保即使在十字形基本单元的臂末端处不存在用于触发寄生源主体-漏极双极结型晶体管结构的偏置电压。栅电极116在面104处与PHV主体区124重叠,使得在操作中,相对于源电极110施加到栅电极116的正电压将产生主体区122中的反型层,其在栅电极下面在面104处的PHV区122中形成沟道,该沟道在相对于源电极114将正电压施加到漏电极112时该沟道传导器件的导通电流。导通电流从漏电极112朝着与漏极区102和PHV主体区122之间的pn结相邻的面104向上流动,并且然后流过栅电极下面的沟道到达所有FET 108的源极区114。栅电极可以是所有基本单元108共用的单个层,或者可以包括具有适当的电气连接的多于一个的层。对栅电极的接触(图1至图3或图4至图6中未示出)可以呈现在器件100或400的边缘处。对漏电极112的接触可以通过将器件100或400安装到其壳体(图1至图3或图4至图6中未示出)来实现。可以通过在直接位于MOSFET 108上方的位置处将电气连接引脚128接合到源电极110的传导层来实现对源电极110的电气接触。在该示例中,电气连接引脚128是接合导线。
在操作中,在截止状态中,通过将栅极短接到源极,漏极-源极电压使衬底101中的PHV主体区122和漏极区102之间的p-n结反向偏置。当电压由于例如UIS而增加到PHV主体区122和漏极区102之间的p-n结超过阈值的值时,p-n结由于雪崩效应而击穿,如图2、图5和图6中的垂直箭头所示。源极区114的臂的末端处的PHV区122通过PSD和BPI区对源电极110的电气连接402防止由于例如漏电流而沿着PHV区122中的源极区114的臂的电压梯度的建立。源极区的中心处的PHV区122对源电极110的电气连接404进一步有助于防止这样的电压梯度。相对于图1至图3的另外的可比较的器件,图4至图6的开关器件的雪崩电流容量在截止状态中增加。
然而,栅极层叠被插入在源电极110和衬底101之间,并且限制了与衬底101密切接触的源电极110的区域。该接触区域的限制不仅集中了电流的流动,增加了局部电流密度并且使由于电流流过衬底的电阻性材料而引起的热生成的局部化,而且栅极层叠的电气绝缘也是热绝缘,限制了源电极材料提取生成的热的能力。在一个示例中,由于对于30V的漏极-源极电压,在UIS条件下流过器件400的电流可以到达数百安培,因此发热效应是显著的。
图7至图9图示了根据本发明的实施例的示例的晶体管功率开关器件700,其包括与图4至图6的晶体管类似的垂直绝缘栅极金属氧化物硅场效应晶体管(MOSFET)108的阵列。此外,器件700包括半导体主体101中的反向偏置垂直雪崩二极管702,其与晶体管108的阵列电气并联,用于在器件的截止状态中传导器件700的面104和106之间的击穿电流,二极管702具有与传导源电极层110接触的第一电流承载区704,以及与第二面106电气连接并且位于第一电流承载区704下面的第二半导体区706。重复雪崩二极管702的第一电流承载区704具有与MOEFET 108的p区122至126相同的第二传导类型,并且第二半导体区706具有与MOSFET 108的漏极区102相同的第一传导类型,在该示例中是n型。
在功率开关器件700的操作中,在MOSFET 108的导通状态中,通过略大于MOSFET 108的阈值电压Vth的电压,栅极116相对于源电极110被正向偏置,并且漏电极相对于源电极110被正向偏置,重复雪崩二极管702在该条件下被反向偏置。
在MOSFET 108的正常操作中,在导通状态中,电流首先从漏电极区102中的漏电极112朝着PHV主体区122的外周处的面104向上传递,然后在MOSFET 108的源极区114的外周处横向通过PHV区122中的栅电极下面的沟道。在MOSFET 108的截止状态中,栅电极116被短接到源电极110,通过二极管720的雪崩电流首先垂直传递通过衬底101中的第二电流承载区706,然后通过第一电流承载区704的层,呈现如图8和图9中的粗箭头所示的使热生成最小化的短路电流传导路径。MOSFET 108中的雪崩电流还垂直传递通过p区122、124和126,但是由插入的栅极层叠116至120限制为小于MOSFET 108阵列的总面积的面104处的合计面积(aggregate area),如图8和9中的细箭头所示。传导源电极层110覆盖雪崩二极管702以及MOSFET 108,并且第一电流承载区704与传导电极层110的电气和热接触在面104处的二极管702的第一电流承载区704的基本上整个面积上是连续的,未受到任何绝缘体材料层的阻碍。雪崩二极管702的尺寸被确定为承受重复雪崩电流,并且在下文中将被称为重复雪崩二极管702。因此,使电流密度最小化,并且使由电流在二极管702中生成的热通过源电极110的排放最小化。
更详细地,在本发明的实施例的该示例中,二极管702的第一电流承载区704包括轻掺杂p型PHV主体区708、PHV区708内的较重掺杂PSD区710以及从PSD区710延伸到面104并且接触源电极110的BPI区712。在本发明的实施例的该示例中,使用适当的掩蔽,PHV主体区708、PSD区710和BPI区712与MOSFET 108的PHV主体区122、PSD区124和BPI区126的制造步骤同时形成。
图10示出了器件700的等效电路1000的示例,图示了总共M个MOSFET基本单元中的一个以及总共N个重复雪崩二极管中的一个。节点1002表示MOSFET 108的NSD源极区114和PHV主体区122之间的p-n结的n型侧,p型侧由节点1004表示并且p-n结由二极管1006表示。电阻器RSource表示节点1002和源电极110之间串联的源极区114的材料的电阻。节点1008表示MOSFET 108的n型漏极区102和PHV主体区122之间的p-n结的n型侧,p型侧由节点1004表示并且p-n结由二极管1010表示。电阻器Rdrain表示在节点1008和漏电极112之间串联的漏极区102的材料的电阻。电阻器Rbulk表示由二极管1004和1010表示的p-n结的p型侧和与源电极110的连接之间串联的PHV、PSD和BPI p区122、124和126的材料的电阻。
重复雪崩二极管702与晶体管108的阵列并联地电气连接,用于分别在第二面106和第一面104处在漏电极112和源电极110之间传导器件的截止状态中的击穿电流。重复雪崩二极管702的n型区706与其p型区之间的p-n结由二极管1012表示,n型侧被连接到节点1008。电阻器1014表示由二极管1012表示的p-n结的p型侧和与源电极110的连接之间串联的p区704的材料的电阻。p区704形成与传导源电极层110接触的第一电流承载区并且重复雪崩二极管702的n型区706形成与第二面106处的漏电极112电气连接的第二半导体区。
在本发明的实施例的一个示例中,存在用于MOSFET 108的阵列的一个重复雪崩二极管702。代替如图2和图3或图5和图6中在MOSFET 108的阵列上方的位置处将电气连接引脚128接合到源电极110,如图8和图9中所示,在重复雪崩二极管702的第一电流承载区704上方的位置处将电气连接引脚128接合到源电极110的传导层。由于该定位,当源电极110和漏电极112之间的电压达到击穿电压时,电场在衬底101内的二极管702中集中,其在MOSFET 108之前首先传导雪崩电流。与晶体管108不同,二极管702中的电流不受绝缘体层的阻碍,使得二极管中的雪崩电流与图1至图3或图5和图6的MOSFET中的情况相比不太集中。而且,不存在插入在源电极110和二极管702之间的绝缘体层,使得接触二极管702的源电极110的面积能够完全用于将热传导远离二极管。如示,在本发明的实施例的该示例中,电气连接引脚128包括导线,该远离源电极110的传导层延伸以便于耗散来自二极管702的热。
初始地,大部分雪崩电流传递通过具有小于垂直MOSFET 108的击穿电压的重复雪崩二极管702,但是随着雪崩电流继续,重复雪崩二极管702温度增加,其击穿电压增加并且MOSFET 108在更大程度上参与传导漏电极112和源电极110之间的雪崩电流。
在上文描述的本发明的实施例的示例中,二极管702的面积(并且更具体地,在第一面104处并且接触源电极传导层110的p区704的面积)适用于连接引脚的直径和接合到接触部的长度,并且比单独的MOSFET 108的面积大了若干个量级。如上文提到的,应当认识到,附图没有依比例绘制。在一个示例中,单独的MOSFET基本单元108测得为50至100μm2,并且电气连接引脚线128的直径约为250至380μm,而二极管702测得为500000μm2。然而,阵列中的MOSFET比二极管多若干个量级,使得在该示例中重复雪崩二极管的面积呈现为在总管芯面积的10%和30%之间。
在本发明的示例性的另一示例中,器件700在单个管芯上的半导体主体101中包括多个反向偏置重复雪崩二极管702,每个二极管702由一个或多个MOSFET单元阵列围绕。图11示出了该类型的器件1100的示例,其包括十四个二极管702。在另一示例中,器件1100包括十个二极管702和六十万个MOSFET单元108。
在图11和图12中图示的类型的本发明的实施例的一个示例中,器件1200包括在每个重复雪崩二极管702的第一电流承载区704上方的位置1202处接合到源电极110的传导层的各个导线电气连接引脚128。在图12的示例中,单个导线电气连接引脚128在重复雪崩二极管的每一个上方的位置处接合到源电极110的传导层。
在图11和图13中图示的类型的本发明的实施例的又一示例中,器件1300包括在多于一个重复雪崩二极管702的第一电流承载区上方的多个位置1302处接合到源电极110的传导层的一个或多个导线电气连接引脚128。在该示例中,相同导线电气连接引脚128被接合在两个重复雪崩二极管702上方。
在本发明的实施例的又一示例中,在重复雪崩二极管702上方在源电极110上生长电气传导接触凸起,并且然后通过连接128接触。在源电极110的传导层上可以使用各种电气连接材料,诸如铝带、铜柱、金或焊接凸起。
图14示出了由虚线1400所示的关于图4至图6中图示类型的晶体管功率开关器件400的UIS重复雪崩测试的结果与由实线1402所示的关于具有相同的管芯尺寸和类似的制造工艺的图7至图9中图示类型的晶体管功率开关器件700的类似测试的结果的比较。获得了器件的鲁棒性的十倍的改进。应当认识到,使用管芯面积的一部分用于二极管702减少了可用于MOSFET 108的管芯面积,这与器件400相比可以增加了开关器件700的导通电阻Rdson。然而,与器件400相比,器件700的UIS鲁棒性的改进使得能够将其各种操作特性调整到不同的折衷,补偿Rdson的增加。
根据本发明的实施例的诸如700的晶体管功率开关器件可以用于具有供电线上的寄生电感的应用。图15示出了功率开关装置1500中的晶体管功率开关器件的应用的示例,其包括与跨越蓄电池1514的负荷1520串联连接的功率开关器件1502。控制单元1516控制施加到功率开关的栅电极的电压。在操作中,控制单元1516根据需要接通和关断功率开关器件1502。
在功率开关器件1502的关断阶段期间,由蓄电池1514和功率开关器件1502之间的电气连接呈现寄生电感1526,并且该寄生电感1526生成反电动势,其可以使施加到电路的电压超过关断状态功率开关器件的击穿电压,在该情况下功率开关器件1502传导雪崩电流。功率开关器件中的二极管702有助于功率开关器件1502对重复这样的雪崩击穿的鲁棒性。
在前面的说明书中,已经参考本发明的实施例的特定示例描述了本发明。然而,明显的是,在不偏离所附权利要求中阐述的本发明的更广泛的精神和范围的情况下可以进行各种修改和改变。例如,连接可以是适合于例如经由中间设备传送来自或去往各个节点、单元或器件的信号的任何类型的连接。因此,除非另外暗指或陈述,否则连接可以是例如直接连接或间接连接。
在上下文允许的情况下,应当理解,这里描述的半导体衬底可以是任何半导体材料或者材料的组合,诸如砷化镓、硅锗、绝缘体上硅(SOI)、硅、单晶硅等及以上的组合。
在实现本发明的装置包括本领域的技术人员公知的电子组件和电路组成的情况下,电路细节没有被解释为任何超出被认为理解和认识本发明的基本概念必需的程度。
在上下文允许的情况下,如果有的话,说明书和权利要求中的术语“前”、“后”、“顶”、“底”、“上”、“下”等用于描述性目的,不一定用于描述永久性的相对位置或顺序。应当理解,如此使用的术语在适当的情形下可以互换,使得这里描述的本发明的实施例例如,能够在不同于这里图示或另外描述的取向的其他取向上进行操作。
在上下文允许的情况下,图示的硬件元件可以是位于单个集成电路上或者相同器件中的电路,或者可以包括彼此互连的多个分离的集成电路或者分离的器件。而且,本发明的实施例中的硬件元件可以由本发明的实施例中的软件或代码表示来替换。
此外,应当认识到,在本发明的实施例中描述和示出的电路元件的功能和/或操作之间的边界仅是说明性的。多个操作的功能可以被组合为单个操作,和/或单个操作的功能可以分布在另外的操作中。而且,替代实施例可以包括特定操作的多个实例,并且在各种其他实施例中操作的顺序可以变更。
在权利要求中,置于括号之间的任何附图标记不应被解释为限制权利要求。在上下文允许的情况下,诸如“第一”和“第二”的术语用于在这些术语描述的元件之间任意进行区分,并且这些术语不一定意在指示这样的元件的时间或者其他优先顺序。
权利要求书(按照条约第19条的修改)
1.一种晶体管功率开关器件(700),包括:半导体主体(101),所述半导体主体(101)呈现相对的第一面(104)和第二面(106),所述开关器件包括:用于承载所述第一面和所述第二面之间电流的垂直晶体管元件(108)阵列,所述晶体管元件(108)阵列包括:所述第一面(104)处的第一半导体类型的第一电流承载晶体管区(114)阵列;至少一个第二电流承载晶体管区(122、124、126),所述至少一个第二电流承载晶体管区(122、124、126)具有与所述第一类型相反的第二半导体类型并且被插入在所述第一半导体区(114)和所述第二面(106)之间;以及,至少一个控制电极(116),所述至少一个控制电极用于以可开关方式允许所述电流在所述器件的导通状态下在前向方向上流过所述第二晶体管区(122、124、126)并且在所述器件的截止状态下关断所述电流的流动;以及,传导层(110),所述传导层接触所述第一电流承载区(114)并且通过至少一个绝缘层(120)与所述控制电极(116)绝缘,
所述开关器件还包括:至少一个垂直雪崩二极管(702),所述至少一个垂直雪崩二极管(702)在与所述晶体管(108)阵列电气并联的所述半导体主体(101)中并且被配置成使得在所述器件的截止状态下所述雪崩二极管(702)以及所述晶体管(108)阵列传导所述第一面(104)和所述第二面(106)之间的击穿电流,所述垂直雪崩二极管(702)在所述器件的所述导通状态下被反向偏置并且具有与所述第一面(104)和与所述传导层(110)接触的所述第二半导体类型的第一电流承载二极管区(704)和与所述第二面(106)电气连接的所述第一半导体类型的第二半导体区(706)。
2.根据权利要求1所述的晶体管功率开关器件,还包括电气连接引脚(128),所述电气连接引脚(128)在所述第一电流承载二极管区(704)上方的位置处被接合到所述传导层(110)。
3.根据权利要求2所述的晶体管功率开关器件,其中,所述电气连接引脚(128)包括导线,所述导线远离所述传导层(110)延伸,以便于耗散来自所述二极管(702)的热。
4.根据权利要求2所述的晶体管功率开关器件,其中,所述电气连接引脚(128)包括所述传导层(110)顶部上的接触凸起,以便于耗散来自所述二极管(402)的热。
5.根据权利要求2或3所述的晶体管功率开关器件,在所述半导体主体(101)中包括多个所述反向偏置雪崩二极管(702),其中,所述电气连接引脚(128)中的至少一个在每个所述雪崩二极管(702)的所述第一电流承载二极管区(704)上方被接合到所述传导层(110)。
6.根据权利要求4所述的晶体管功率开关器件,其中,所述电气连接引脚(128)的至少一个在多于一个的所述雪崩二极管(702)的所述第一电流承载二极管区(704)上方的多个位置处被接合到所述传导层(110)。
7.根据前述权利要求中的任何一项所述的晶体管功率开关器件,其中,每个所述第一电流承载晶体管区(114)接触所述传导层(110)的面积基本上小于所述反向偏置雪崩二极管(702)的所述第一电流承载二极管区(704)接触所述传导层(110)的面积。
8.根据前述权利要求7所述的晶体管功率开关器件,其中,所述反向偏置雪崩二极管(702)在所述第一面(104)处具有的面积比每个所述晶体管元件(108)大了多于一个量级。
9.根据前述权利要求中的任何一项所述的晶体管功率开关器件,其中,所述反向偏置雪崩二极管(702)具有小于所述阵列的所述垂直晶体管元件的击穿电压。
10.根据前述权利要求中的任何一项所述的晶体管功率开关器件,其中,所述晶体管元件(108)阵列包括:所述第二半导体类型的轻掺杂高电压区(122)和所述轻掺杂高电压区内的所述第二半导体类型的较重掺杂区(124)的阵列,并且所述反向偏置雪崩二极管(702)包括:所述第二半导体类型的轻掺杂主体区(708)以及所述区轻掺杂主体区(708)内的所述第二半导体类型的较重掺杂区(710),所述反向偏置雪崩二极管(702)的所述轻掺杂主体区(708)和所述较重掺杂区(710)已经与所述晶体管元件(108)的对应区同时形成。
11.根据前述权利要求中任何一项所述的晶体管功率开关器件,其中,所述垂直晶体管元件(108)包括场效应晶体管,所述场效应晶体管的第一电流承载晶体管区(114)包括源极区,所述场效应晶体管的第二电流承载晶体管区(122、124、126)包括至少一个主体区,所述场效应晶体管的控制电极(116)包括至少一个栅电极,并且所述场效应晶体管包括与所述第二面(106)电气连接的至少一个漏极区(102),所述至少一个绝缘层包括使所述控制电极(116)与所述垂直晶体管元件的所述第一电流承载晶体管区和所述第二电流承载晶体管区(114、122、124、126)绝缘的层(118)以及使所述控制电极(116)与所述至少一个传导层绝缘的层(120、121)。
12.根据权利要求11所述的晶体管功率开关器件,其中,接触所述传导层(110)的每个所述垂直晶体管元件(108)的所述源极区(114)包括多个臂,所述多个臂在所述第一面(104)处朝着所述阵列的相邻垂直晶体管元件(108)的源极区(114)的臂径向延伸,所述至少一个主体区(122、124、126)在所述源极区(114)的所述臂的周围和下面延伸并且在所述垂直晶体管元件(108)之间合并以形成连续的主体区,并且所述至少一个主体区(122、124、126)在每个所述源极区内向上延伸,以在与所述源极区(114)的每个所述臂的末端相邻的接触位置(402)处在所述第一面(104)处接触所述传导层(110)。
13.根据权利要求12所述的晶体管功率开关器件,其中,所述至少一个p区(122、124、126)还在每个所述源极区内向上延伸,以在所述垂直晶体管元件(108)的每个所述源极区(114)的中心的接触位置(404)处在所述第一面(104)处接触所述传导层(110)。
14.根据权利要求12或13所述的晶体管功率开关器件,其中,所述源极区(114)的每个所述臂的所述末端在所述接触位置(402)周围在所述第一面(104)处被扩大。
15.一种功率开关装置,包括根据前述权利要求中的任何一项所述的晶体管功率开关器件(700)以及用于将操作电压施加到所述晶体管功率开关器件的电压源(1514、1516)。
Claims (13)
1.一种晶体管功率开关器件(700),包括半导体主体(101),所述半导体主体(101)呈现相对的第一面(104)和第二面(106),所述开关器件包括用于承载所述第一面和所述第二面之间电流的垂直晶体管元件(108)阵列,所述晶体管元件(108)阵列包括:所述第一面(104)处的第一半导体类型的第一电流承载晶体管区(114)阵列;至少一个第二电流承载晶体管区(122、124、126),所述至少一个第二电流承载晶体管区(122、124、126)具有与所述第一类型相反的第二半导体类型并且被插入在所述第一半导体区(114)和所述第二面(106)之间;以及,至少一个控制电极(116),所述至少一个控制电极用于以可开关方式控制所述电流流过所述第二晶体管区(122、124、126);以及,传导层(110),所述传导层接触所述第一电流承载区(114)并且通过至少一个绝缘层(120)与所述控制电极(116)绝缘,
所述开关器件还包括:与所述晶体管(108)阵列电气并联的所述半导体主体(101)中的至少一个反向偏置垂直雪崩二极管(702),用于在所述器件的截止状态下传导所述第一面(104)和所述第二面(106)之间的击穿电流,并且具有与所述第一面(104)和与所述传导层(110)接触的所述第二半导体类型的第一电流承载二极管区(704)和与所述第二面(106)电气连接的所述第一半导体类型的第二半导体区(706)。
2.根据权利要求1所述的晶体管功率开关器件,还包括电气连接引脚(128),所述电气连接引脚(128)在所述第一电流承载二极管区(704)上方的位置处被接合到所述传导层(110)。
3.根据权利要求2所述的晶体管功率开关器件,其中,所述电气连接引脚(128)包括导线,所述导线远离所述传导层(110)延伸,以便于耗散来自所述二极管(702)的热。
4.根据权利要求2所述的晶体管功率开关器件,其中,所述电气连接引脚(128)包括所述传导层(110)顶部上的接触凸起,以便于耗散来自所述二极管(402)的热。
5.根据权利要求2或3所述的晶体管功率开关器件,在所述半导体主体(101)中包括多个所述反向偏置雪崩二极管(702),其中,所述电气连接引脚(128)中的至少一个在每个所述雪崩二极管(702)的所述第一电流承载二极管区(704)上方被接合到所述传导层(110)。
6.根据权利要求4所述的晶体管功率开关器件,其中,所述电气连接引脚(128)的至少一个在多于一个的所述雪崩二极管(702)的所述第一电流承载二极管区(704)上方的多个位置处被接合到所述传导层(110)。
7.根据前述权利要求中的任何一项所述的晶体管功率开关器件,其中,每个所述第一电流承载晶体管区(114)接触所述传导层(110)的面积基本上小于所述反向偏置雪崩二极管(702)的所述第一电流承载二极管区(704)接触所述传导层(110)的面积。
8.根据前述权利要求中的任何一项所述的晶体管功率开关器件,其中,所述反向偏置雪崩二极管(702)具有小于所述阵列的所述垂直晶体管元件的击穿电压。
9.根据前述权利要求中的任何一项所述的晶体管功率开关器件,其中,所述垂直晶体管元件(108)包括场效应晶体管,所述场效应晶体管的第一电流承载晶体管区(114)包括源极区,所述场效应晶体管的第二电流承载晶体管区(122、124、126)包括至少一个主体区,所述场效应晶体管的控制电极(116)包括至少一个栅电极,并且所述场效应晶体管包括与所述第二面(106)电气连接的至少一个漏极区(102),所述至少一个绝缘层包括使所述控制电极(116)与所述垂直晶体管元件的所述第一流承载晶体管区和所述第二电流承载晶体管区(114、122、124、126)绝缘的层(118)以及使所述控制电极(116)与所述至少一个传导层绝缘的层(120、121)。
10.根据权利要求9所述的晶体管功率开关器件,其中,接触所述传导层(110)的每个所述垂直晶体管元件(108)的所述源极区(114)包括多个臂,所述多个臂在所述第一面(104)处朝着所述阵列的相邻垂直晶体管元件(108)的源极区(114)的臂径向延伸,所述至少一个主体区(122、124、126)在所述源极区(114)的所述臂的周围和下面延伸,并且在每个所述源极区内向上延伸,以在与所述源极区(114)的每个所述臂的末端相邻的接触位置(402)处在所述第一面(104)处接触所述传导层(110)。
11.根据权利要求10所述的晶体管功率开关器件,其中,所述至少一个p区(122、124、126)还在每个所述源极区内向上延伸,以在所述垂直晶体管元件(108)的每个所述源极区(114)的中心的接触位置(404)处在所述第一面(104)处接触所述传导层(110)。
12.根据权利要求10或11所述的晶体管功率开关器件,其中,所述源极区(114)的每个所述臂的所述末端在所述接触位置(402)周围在所述第一面(104)处被扩大。
13.一种功率开关装置,包括根据前述权利要求中的任何一项所述的晶体管功率开关器件(700)以及用于将操作电压施加到所述晶体管功率开关器件的电压源(1514、1516)。
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